1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 12 #include "pinctrl-rockchip.h" 13 14 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 15 { 16 /* pwm0-0 */ 17 .bank_num = 0, 18 .pin = 26, 19 .func = 1, 20 .route_offset = 0x50, 21 .route_val = BIT(16), 22 }, { 23 /* pwm0-1 */ 24 .bank_num = 3, 25 .pin = 21, 26 .func = 1, 27 .route_offset = 0x50, 28 .route_val = BIT(16) | BIT(0), 29 }, { 30 /* pwm1-0 */ 31 .bank_num = 0, 32 .pin = 27, 33 .func = 1, 34 .route_offset = 0x50, 35 .route_val = BIT(16 + 1), 36 }, { 37 /* pwm1-1 */ 38 .bank_num = 0, 39 .pin = 30, 40 .func = 2, 41 .route_offset = 0x50, 42 .route_val = BIT(16 + 1) | BIT(1), 43 }, { 44 /* pwm2-0 */ 45 .bank_num = 0, 46 .pin = 28, 47 .func = 1, 48 .route_offset = 0x50, 49 .route_val = BIT(16 + 2), 50 }, { 51 /* pwm2-1 */ 52 .bank_num = 1, 53 .pin = 12, 54 .func = 2, 55 .route_offset = 0x50, 56 .route_val = BIT(16 + 2) | BIT(2), 57 }, { 58 /* pwm3-0 */ 59 .bank_num = 3, 60 .pin = 26, 61 .func = 1, 62 .route_offset = 0x50, 63 .route_val = BIT(16 + 3), 64 }, { 65 /* pwm3-1 */ 66 .bank_num = 1, 67 .pin = 11, 68 .func = 2, 69 .route_offset = 0x50, 70 .route_val = BIT(16 + 3) | BIT(3), 71 }, { 72 /* sdio-0_d0 */ 73 .bank_num = 1, 74 .pin = 1, 75 .func = 1, 76 .route_offset = 0x50, 77 .route_val = BIT(16 + 4), 78 }, { 79 /* sdio-1_d0 */ 80 .bank_num = 3, 81 .pin = 2, 82 .func = 1, 83 .route_offset = 0x50, 84 .route_val = BIT(16 + 4) | BIT(4), 85 }, { 86 /* spi-0_rx */ 87 .bank_num = 0, 88 .pin = 13, 89 .func = 2, 90 .route_offset = 0x50, 91 .route_val = BIT(16 + 5), 92 }, { 93 /* spi-1_rx */ 94 .bank_num = 2, 95 .pin = 0, 96 .func = 2, 97 .route_offset = 0x50, 98 .route_val = BIT(16 + 5) | BIT(5), 99 }, { 100 /* emmc-0_cmd */ 101 .bank_num = 1, 102 .pin = 22, 103 .func = 2, 104 .route_offset = 0x50, 105 .route_val = BIT(16 + 7), 106 }, { 107 /* emmc-1_cmd */ 108 .bank_num = 2, 109 .pin = 4, 110 .func = 2, 111 .route_offset = 0x50, 112 .route_val = BIT(16 + 7) | BIT(7), 113 }, { 114 /* uart2-0_rx */ 115 .bank_num = 1, 116 .pin = 19, 117 .func = 2, 118 .route_offset = 0x50, 119 .route_val = BIT(16 + 8), 120 }, { 121 /* uart2-1_rx */ 122 .bank_num = 1, 123 .pin = 10, 124 .func = 2, 125 .route_offset = 0x50, 126 .route_val = BIT(16 + 8) | BIT(8), 127 }, { 128 /* uart1-0_rx */ 129 .bank_num = 1, 130 .pin = 10, 131 .func = 1, 132 .route_offset = 0x50, 133 .route_val = BIT(16 + 11), 134 }, { 135 /* uart1-1_rx */ 136 .bank_num = 3, 137 .pin = 13, 138 .func = 1, 139 .route_offset = 0x50, 140 .route_val = BIT(16 + 11) | BIT(11), 141 }, 142 }; 143 144 #define RK3228_PULL_OFFSET 0x100 145 146 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 147 int pin_num, struct regmap **regmap, 148 int *reg, u8 *bit) 149 { 150 struct rockchip_pinctrl_priv *priv = bank->priv; 151 152 *regmap = priv->regmap_base; 153 *reg = RK3228_PULL_OFFSET; 154 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; 155 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 156 157 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); 158 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 159 } 160 161 #define RK3228_DRV_GRF_OFFSET 0x200 162 163 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 164 int pin_num, struct regmap **regmap, 165 int *reg, u8 *bit) 166 { 167 struct rockchip_pinctrl_priv *priv = bank->priv; 168 169 *regmap = priv->regmap_base; 170 *reg = RK3228_DRV_GRF_OFFSET; 171 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; 172 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 173 174 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); 175 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 176 } 177 178 static struct rockchip_pin_bank rk3228_pin_banks[] = { 179 PIN_BANK(0, 32, "gpio0"), 180 PIN_BANK(1, 32, "gpio1"), 181 PIN_BANK(2, 32, "gpio2"), 182 PIN_BANK(3, 32, "gpio3"), 183 }; 184 185 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 186 .pin_banks = rk3228_pin_banks, 187 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 188 .label = "RK3228-GPIO", 189 .type = RK3288, 190 .grf_mux_offset = 0x0, 191 .iomux_routes = rk3228_mux_route_data, 192 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 193 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 194 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 195 }; 196 197 static const struct udevice_id rk3228_pinctrl_ids[] = { 198 { 199 .compatible = "rockchip,rk3228-pinctrl", 200 .data = (ulong)&rk3228_pin_ctrl 201 }, 202 { } 203 }; 204 205 U_BOOT_DRIVER(pinctrl_rk3228) = { 206 .name = "rockchip_rk3228_pinctrl", 207 .id = UCLASS_PINCTRL, 208 .of_match = rk3228_pinctrl_ids, 209 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 210 .ops = &rockchip_pinctrl_ops, 211 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 212 .bind = dm_scan_fdt_dev, 213 #endif 214 .probe = rockchip_pinctrl_probe, 215 }; 216