1*e7ae4cf2SDavid Wu // SPDX-License-Identifier: GPL-2.0+
2*e7ae4cf2SDavid Wu /*
3*e7ae4cf2SDavid Wu * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4*e7ae4cf2SDavid Wu */
5*e7ae4cf2SDavid Wu
6*e7ae4cf2SDavid Wu #include <common.h>
7*e7ae4cf2SDavid Wu #include <dm.h>
8*e7ae4cf2SDavid Wu #include <dm/pinctrl.h>
9*e7ae4cf2SDavid Wu #include <regmap.h>
10*e7ae4cf2SDavid Wu #include <syscon.h>
11*e7ae4cf2SDavid Wu
12*e7ae4cf2SDavid Wu #include "pinctrl-rockchip.h"
13*e7ae4cf2SDavid Wu
14*e7ae4cf2SDavid Wu #define RK3036_PULL_OFFSET 0x118
15*e7ae4cf2SDavid Wu #define RK3036_PULL_PINS_PER_REG 16
16*e7ae4cf2SDavid Wu #define RK3036_PULL_BANK_STRIDE 8
17*e7ae4cf2SDavid Wu
rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)18*e7ae4cf2SDavid Wu static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
19*e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap,
20*e7ae4cf2SDavid Wu int *reg, u8 *bit)
21*e7ae4cf2SDavid Wu {
22*e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv;
23*e7ae4cf2SDavid Wu
24*e7ae4cf2SDavid Wu *regmap = priv->regmap_base;
25*e7ae4cf2SDavid Wu *reg = RK3036_PULL_OFFSET;
26*e7ae4cf2SDavid Wu *reg += bank->bank_num * RK3036_PULL_BANK_STRIDE;
27*e7ae4cf2SDavid Wu *reg += (pin_num / RK3036_PULL_PINS_PER_REG) * 4;
28*e7ae4cf2SDavid Wu
29*e7ae4cf2SDavid Wu *bit = pin_num % RK3036_PULL_PINS_PER_REG;
30*e7ae4cf2SDavid Wu };
31*e7ae4cf2SDavid Wu
32*e7ae4cf2SDavid Wu static struct rockchip_pin_bank rk3036_pin_banks[] = {
33*e7ae4cf2SDavid Wu PIN_BANK(0, 32, "gpio0"),
34*e7ae4cf2SDavid Wu PIN_BANK(1, 32, "gpio1"),
35*e7ae4cf2SDavid Wu PIN_BANK(2, 32, "gpio2"),
36*e7ae4cf2SDavid Wu };
37*e7ae4cf2SDavid Wu
38*e7ae4cf2SDavid Wu static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
39*e7ae4cf2SDavid Wu .pin_banks = rk3036_pin_banks,
40*e7ae4cf2SDavid Wu .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
41*e7ae4cf2SDavid Wu .label = "RK3036-GPIO",
42*e7ae4cf2SDavid Wu .type = RK3036,
43*e7ae4cf2SDavid Wu .grf_mux_offset = 0xa8,
44*e7ae4cf2SDavid Wu .pull_calc_reg = rk3036_calc_pull_reg_and_bit,
45*e7ae4cf2SDavid Wu };
46*e7ae4cf2SDavid Wu
47*e7ae4cf2SDavid Wu static const struct udevice_id rk3036_pinctrl_ids[] = {
48*e7ae4cf2SDavid Wu {
49*e7ae4cf2SDavid Wu .compatible = "rockchip,rk3036-pinctrl",
50*e7ae4cf2SDavid Wu .data = (ulong)&rk3036_pin_ctrl
51*e7ae4cf2SDavid Wu },
52*e7ae4cf2SDavid Wu {}
53*e7ae4cf2SDavid Wu };
54*e7ae4cf2SDavid Wu
55*e7ae4cf2SDavid Wu U_BOOT_DRIVER(pinctrl_rockchip) = {
56*e7ae4cf2SDavid Wu .name = "rk3036-pinctrl",
57*e7ae4cf2SDavid Wu .id = UCLASS_PINCTRL,
58*e7ae4cf2SDavid Wu .of_match = rk3036_pinctrl_ids,
59*e7ae4cf2SDavid Wu .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
60*e7ae4cf2SDavid Wu .ops = &rockchip_pinctrl_ops,
61*e7ae4cf2SDavid Wu #if !CONFIG_IS_ENABLED(OF_PLATDATA)
62*e7ae4cf2SDavid Wu .bind = dm_scan_fdt_dev,
63*e7ae4cf2SDavid Wu #endif
64*e7ae4cf2SDavid Wu .probe = rockchip_pinctrl_probe,
65*e7ae4cf2SDavid Wu };
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