1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pin Control driver for SuperH Pin Function Controller. 4 * 5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart 6 * 7 * Copyright (C) 2008 Magnus Damm 8 * Copyright (C) 2009 - 2012 Paul Mundt 9 * Copyright (C) 2017 Marek Vasut 10 */ 11 12 #define DRV_NAME "sh-pfc" 13 14 #include <common.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <dm/pinctrl.h> 18 #include <linux/io.h> 19 #include <linux/sizes.h> 20 21 #include "sh_pfc.h" 22 23 enum sh_pfc_model { 24 SH_PFC_R8A7790 = 0, 25 SH_PFC_R8A7791, 26 SH_PFC_R8A7792, 27 SH_PFC_R8A7793, 28 SH_PFC_R8A7794, 29 SH_PFC_R8A7795, 30 SH_PFC_R8A7796, 31 SH_PFC_R8A77970, 32 SH_PFC_R8A77990, 33 SH_PFC_R8A77995, 34 }; 35 36 struct sh_pfc_pin_config { 37 u32 type; 38 }; 39 40 struct sh_pfc_pinctrl { 41 struct sh_pfc *pfc; 42 43 struct sh_pfc_pin_config *configs; 44 45 const char *func_prop_name; 46 const char *groups_prop_name; 47 const char *pins_prop_name; 48 }; 49 50 struct sh_pfc_pin_range { 51 u16 start; 52 u16 end; 53 }; 54 55 struct sh_pfc_pinctrl_priv { 56 struct sh_pfc pfc; 57 struct sh_pfc_pinctrl pmx; 58 }; 59 60 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) 61 { 62 unsigned int offset; 63 unsigned int i; 64 65 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { 66 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; 67 68 if (pin <= range->end) 69 return pin >= range->start 70 ? offset + pin - range->start : -1; 71 72 offset += range->end - range->start + 1; 73 } 74 75 return -EINVAL; 76 } 77 78 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) 79 { 80 if (enum_id < r->begin) 81 return 0; 82 83 if (enum_id > r->end) 84 return 0; 85 86 return 1; 87 } 88 89 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) 90 { 91 switch (reg_width) { 92 case 8: 93 return readb(mapped_reg); 94 case 16: 95 return readw(mapped_reg); 96 case 32: 97 return readl(mapped_reg); 98 } 99 100 BUG(); 101 return 0; 102 } 103 104 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 105 u32 data) 106 { 107 switch (reg_width) { 108 case 8: 109 writeb(data, mapped_reg); 110 return; 111 case 16: 112 writew(data, mapped_reg); 113 return; 114 case 32: 115 writel(data, mapped_reg); 116 return; 117 } 118 119 BUG(); 120 } 121 122 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) 123 { 124 return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32); 125 } 126 127 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) 128 { 129 void __iomem *unlock_reg = 130 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 131 132 if (pfc->info->unlock_reg) 133 sh_pfc_write_raw_reg(unlock_reg, 32, ~data); 134 135 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data); 136 } 137 138 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 139 const struct pinmux_cfg_reg *crp, 140 unsigned int in_pos, 141 void __iomem **mapped_regp, u32 *maskp, 142 unsigned int *posp) 143 { 144 unsigned int k; 145 146 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg; 147 148 if (crp->field_width) { 149 *maskp = (1 << crp->field_width) - 1; 150 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); 151 } else { 152 *maskp = (1 << crp->var_field_width[in_pos]) - 1; 153 *posp = crp->reg_width; 154 for (k = 0; k <= in_pos; k++) 155 *posp -= crp->var_field_width[k]; 156 } 157 } 158 159 static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 160 const struct pinmux_cfg_reg *crp, 161 unsigned int field, u32 value) 162 { 163 void __iomem *mapped_reg; 164 void __iomem *unlock_reg = 165 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 166 unsigned int pos; 167 u32 mask, data; 168 169 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 170 171 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " 172 "r_width = %u, f_width = %u\n", 173 crp->reg, value, field, crp->reg_width, crp->field_width); 174 175 mask = ~(mask << pos); 176 value = value << pos; 177 178 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); 179 data &= mask; 180 data |= value; 181 182 if (pfc->info->unlock_reg) 183 sh_pfc_write_raw_reg(unlock_reg, 32, ~data); 184 185 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); 186 } 187 188 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, 189 const struct pinmux_cfg_reg **crp, 190 unsigned int *fieldp, u32 *valuep) 191 { 192 unsigned int k = 0; 193 194 while (1) { 195 const struct pinmux_cfg_reg *config_reg = 196 pfc->info->cfg_regs + k; 197 unsigned int r_width = config_reg->reg_width; 198 unsigned int f_width = config_reg->field_width; 199 unsigned int curr_width; 200 unsigned int bit_pos; 201 unsigned int pos = 0; 202 unsigned int m = 0; 203 204 if (!r_width) 205 break; 206 207 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { 208 u32 ncomb; 209 u32 n; 210 211 if (f_width) 212 curr_width = f_width; 213 else 214 curr_width = config_reg->var_field_width[m]; 215 216 ncomb = 1 << curr_width; 217 for (n = 0; n < ncomb; n++) { 218 if (config_reg->enum_ids[pos + n] == enum_id) { 219 *crp = config_reg; 220 *fieldp = m; 221 *valuep = n; 222 return 0; 223 } 224 } 225 pos += ncomb; 226 m++; 227 } 228 k++; 229 } 230 231 return -EINVAL; 232 } 233 234 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, 235 u16 *enum_idp) 236 { 237 const u16 *data = pfc->info->pinmux_data; 238 unsigned int k; 239 240 if (pos) { 241 *enum_idp = data[pos + 1]; 242 return pos + 1; 243 } 244 245 for (k = 0; k < pfc->info->pinmux_data_size; k++) { 246 if (data[k] == mark) { 247 *enum_idp = data[k + 1]; 248 return k + 1; 249 } 250 } 251 252 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", 253 mark); 254 return -EINVAL; 255 } 256 257 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 258 { 259 const struct pinmux_range *range; 260 int pos = 0; 261 262 switch (pinmux_type) { 263 case PINMUX_TYPE_GPIO: 264 case PINMUX_TYPE_FUNCTION: 265 range = NULL; 266 break; 267 268 case PINMUX_TYPE_OUTPUT: 269 range = &pfc->info->output; 270 break; 271 272 case PINMUX_TYPE_INPUT: 273 range = &pfc->info->input; 274 break; 275 276 default: 277 return -EINVAL; 278 } 279 280 /* Iterate over all the configuration fields we need to update. */ 281 while (1) { 282 const struct pinmux_cfg_reg *cr; 283 unsigned int field; 284 u16 enum_id; 285 u32 value; 286 int in_range; 287 int ret; 288 289 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); 290 if (pos < 0) 291 return pos; 292 293 if (!enum_id) 294 break; 295 296 /* Check if the configuration field selects a function. If it 297 * doesn't, skip the field if it's not applicable to the 298 * requested pinmux type. 299 */ 300 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); 301 if (!in_range) { 302 if (pinmux_type == PINMUX_TYPE_FUNCTION) { 303 /* Functions are allowed to modify all 304 * fields. 305 */ 306 in_range = 1; 307 } else if (pinmux_type != PINMUX_TYPE_GPIO) { 308 /* Input/output types can only modify fields 309 * that correspond to their respective ranges. 310 */ 311 in_range = sh_pfc_enum_in_range(enum_id, range); 312 313 /* 314 * special case pass through for fixed 315 * input-only or output-only pins without 316 * function enum register association. 317 */ 318 if (in_range && enum_id == range->force) 319 continue; 320 } 321 /* GPIOs are only allowed to modify function fields. */ 322 } 323 324 if (!in_range) 325 continue; 326 327 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); 328 if (ret < 0) 329 return ret; 330 331 sh_pfc_write_config_reg(pfc, cr, field, value); 332 } 333 334 return 0; 335 } 336 337 const struct pinmux_bias_reg * 338 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, 339 unsigned int *bit) 340 { 341 unsigned int i, j; 342 343 for (i = 0; pfc->info->bias_regs[i].puen; i++) { 344 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { 345 if (pfc->info->bias_regs[i].pins[j] == pin) { 346 *bit = j; 347 return &pfc->info->bias_regs[i]; 348 } 349 } 350 } 351 352 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); 353 354 return NULL; 355 } 356 357 static int sh_pfc_init_ranges(struct sh_pfc *pfc) 358 { 359 struct sh_pfc_pin_range *range; 360 unsigned int nr_ranges; 361 unsigned int i; 362 363 if (pfc->info->pins[0].pin == (u16)-1) { 364 /* Pin number -1 denotes that the SoC doesn't report pin numbers 365 * in its pin arrays yet. Consider the pin numbers range as 366 * continuous and allocate a single range. 367 */ 368 pfc->nr_ranges = 1; 369 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL); 370 if (pfc->ranges == NULL) 371 return -ENOMEM; 372 373 pfc->ranges->start = 0; 374 pfc->ranges->end = pfc->info->nr_pins - 1; 375 pfc->nr_gpio_pins = pfc->info->nr_pins; 376 377 return 0; 378 } 379 380 /* Count, allocate and fill the ranges. The PFC SoC data pins array must 381 * be sorted by pin numbers, and pins without a GPIO port must come 382 * last. 383 */ 384 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { 385 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) 386 nr_ranges++; 387 } 388 389 pfc->nr_ranges = nr_ranges; 390 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL); 391 if (pfc->ranges == NULL) 392 return -ENOMEM; 393 394 range = pfc->ranges; 395 range->start = pfc->info->pins[0].pin; 396 397 for (i = 1; i < pfc->info->nr_pins; ++i) { 398 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) 399 continue; 400 401 range->end = pfc->info->pins[i-1].pin; 402 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 403 pfc->nr_gpio_pins = range->end + 1; 404 405 range++; 406 range->start = pfc->info->pins[i].pin; 407 } 408 409 range->end = pfc->info->pins[i-1].pin; 410 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 411 pfc->nr_gpio_pins = range->end + 1; 412 413 return 0; 414 } 415 416 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev) 417 { 418 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 419 420 return priv->pfc.info->nr_pins; 421 } 422 423 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev, 424 unsigned selector) 425 { 426 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 427 428 return priv->pfc.info->pins[selector].name; 429 } 430 431 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev) 432 { 433 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 434 435 return priv->pfc.info->nr_groups; 436 } 437 438 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev, 439 unsigned selector) 440 { 441 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 442 443 return priv->pfc.info->groups[selector].name; 444 } 445 446 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev) 447 { 448 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 449 450 return priv->pfc.info->nr_functions; 451 } 452 453 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, 454 unsigned selector) 455 { 456 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 457 458 return priv->pfc.info->functions[selector].name; 459 } 460 461 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector) 462 { 463 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 464 struct sh_pfc_pinctrl *pmx = &priv->pmx; 465 struct sh_pfc *pfc = &priv->pfc; 466 struct sh_pfc_pin_config *cfg; 467 const struct sh_pfc_pin *pin = NULL; 468 int i, idx; 469 470 for (i = 1; i < pfc->info->nr_pins; i++) { 471 if (priv->pfc.info->pins[i].pin != pin_selector) 472 continue; 473 474 pin = &priv->pfc.info->pins[i]; 475 break; 476 } 477 478 if (!pin) 479 return -EINVAL; 480 481 idx = sh_pfc_get_pin_index(pfc, pin->pin); 482 cfg = &pmx->configs[idx]; 483 484 if (cfg->type != PINMUX_TYPE_NONE) 485 return -EBUSY; 486 487 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); 488 } 489 490 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, 491 unsigned func_selector) 492 { 493 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 494 struct sh_pfc_pinctrl *pmx = &priv->pmx; 495 struct sh_pfc *pfc = &priv->pfc; 496 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector]; 497 int idx = sh_pfc_get_pin_index(pfc, pin->pin); 498 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 499 500 if (cfg->type != PINMUX_TYPE_NONE) 501 return -EBUSY; 502 503 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION); 504 } 505 506 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector, 507 unsigned func_selector) 508 { 509 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 510 struct sh_pfc_pinctrl *pmx = &priv->pmx; 511 struct sh_pfc *pfc = &priv->pfc; 512 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector]; 513 unsigned int i; 514 int ret = 0; 515 516 for (i = 0; i < grp->nr_pins; ++i) { 517 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 518 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 519 520 if (cfg->type != PINMUX_TYPE_NONE) { 521 ret = -EBUSY; 522 goto done; 523 } 524 } 525 526 for (i = 0; i < grp->nr_pins; ++i) { 527 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); 528 if (ret < 0) 529 break; 530 } 531 532 done: 533 return ret; 534 } 535 #if CONFIG_IS_ENABLED(PINCONF) 536 static const struct pinconf_param sh_pfc_pinconf_params[] = { 537 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 538 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 539 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 540 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 541 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 }, 542 }; 543 544 static void __iomem * 545 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin, 546 unsigned int *offset, unsigned int *size) 547 { 548 const struct pinmux_drive_reg_field *field; 549 const struct pinmux_drive_reg *reg; 550 unsigned int i; 551 552 for (reg = pfc->info->drive_regs; reg->reg; ++reg) { 553 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { 554 field = ®->fields[i]; 555 556 if (field->size && field->pin == pin) { 557 *offset = field->offset; 558 *size = field->size; 559 560 return (void __iomem *)(uintptr_t)reg->reg; 561 } 562 } 563 } 564 565 return NULL; 566 } 567 568 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, 569 unsigned int pin, u16 strength) 570 { 571 unsigned int offset; 572 unsigned int size; 573 unsigned int step; 574 void __iomem *reg; 575 void __iomem *unlock_reg = 576 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 577 u32 val; 578 579 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 580 if (!reg) 581 return -EINVAL; 582 583 step = size == 2 ? 6 : 3; 584 585 if (strength < step || strength > 24) 586 return -EINVAL; 587 588 /* Convert the value from mA based on a full drive strength value of 589 * 24mA. We can make the full value configurable later if needed. 590 */ 591 strength = strength / step - 1; 592 593 val = sh_pfc_read_raw_reg(reg, 32); 594 val &= ~GENMASK(offset + 4 - 1, offset); 595 val |= strength << offset; 596 597 if (unlock_reg) 598 sh_pfc_write_raw_reg(unlock_reg, 32, ~val); 599 600 sh_pfc_write_raw_reg(reg, 32, val); 601 602 return 0; 603 } 604 605 /* Check whether the requested parameter is supported for a pin. */ 606 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, 607 unsigned int param) 608 { 609 int idx = sh_pfc_get_pin_index(pfc, _pin); 610 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 611 612 switch (param) { 613 case PIN_CONFIG_BIAS_DISABLE: 614 return pin->configs & 615 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN); 616 617 case PIN_CONFIG_BIAS_PULL_UP: 618 return pin->configs & SH_PFC_PIN_CFG_PULL_UP; 619 620 case PIN_CONFIG_BIAS_PULL_DOWN: 621 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; 622 623 case PIN_CONFIG_DRIVE_STRENGTH: 624 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; 625 626 case PIN_CONFIG_POWER_SOURCE: 627 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; 628 629 default: 630 return false; 631 } 632 } 633 634 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, 635 unsigned int param, unsigned int arg) 636 { 637 struct sh_pfc *pfc = pmx->pfc; 638 void __iomem *pocctrl; 639 void __iomem *unlock_reg = 640 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 641 u32 addr, val; 642 int bit, ret; 643 644 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 645 return -ENOTSUPP; 646 647 switch (param) { 648 case PIN_CONFIG_BIAS_PULL_UP: 649 case PIN_CONFIG_BIAS_PULL_DOWN: 650 case PIN_CONFIG_BIAS_DISABLE: 651 if (!pfc->info->ops || !pfc->info->ops->set_bias) 652 return -ENOTSUPP; 653 654 pfc->info->ops->set_bias(pfc, _pin, param); 655 656 break; 657 658 case PIN_CONFIG_DRIVE_STRENGTH: 659 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); 660 if (ret < 0) 661 return ret; 662 663 break; 664 665 case PIN_CONFIG_POWER_SOURCE: 666 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 667 return -ENOTSUPP; 668 669 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr); 670 if (bit < 0) { 671 printf("invalid pin %#x", _pin); 672 return bit; 673 } 674 675 if (arg != 1800 && arg != 3300) 676 return -EINVAL; 677 678 pocctrl = (void __iomem *)(uintptr_t)addr; 679 680 val = sh_pfc_read_raw_reg(pocctrl, 32); 681 if (arg == 3300) 682 val |= BIT(bit); 683 else 684 val &= ~BIT(bit); 685 686 if (unlock_reg) 687 sh_pfc_write_raw_reg(unlock_reg, 32, ~val); 688 689 sh_pfc_write_raw_reg(pocctrl, 32, val); 690 691 break; 692 693 default: 694 return -ENOTSUPP; 695 } 696 697 return 0; 698 } 699 700 static int sh_pfc_pinconf_pin_set(struct udevice *dev, 701 unsigned int pin_selector, 702 unsigned int param, unsigned int arg) 703 { 704 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 705 struct sh_pfc_pinctrl *pmx = &priv->pmx; 706 struct sh_pfc *pfc = &priv->pfc; 707 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector]; 708 709 sh_pfc_pinconf_set(pmx, pin->pin, param, arg); 710 711 return 0; 712 } 713 714 static int sh_pfc_pinconf_group_set(struct udevice *dev, 715 unsigned int group_selector, 716 unsigned int param, unsigned int arg) 717 { 718 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 719 struct sh_pfc_pinctrl *pmx = &priv->pmx; 720 struct sh_pfc *pfc = &priv->pfc; 721 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector]; 722 unsigned int i; 723 724 for (i = 0; i < grp->nr_pins; i++) 725 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg); 726 727 return 0; 728 } 729 #endif 730 731 static struct pinctrl_ops sh_pfc_pinctrl_ops = { 732 .get_pins_count = sh_pfc_pinctrl_get_pins_count, 733 .get_pin_name = sh_pfc_pinctrl_get_pin_name, 734 .get_groups_count = sh_pfc_pinctrl_get_groups_count, 735 .get_group_name = sh_pfc_pinctrl_get_group_name, 736 .get_functions_count = sh_pfc_pinctrl_get_functions_count, 737 .get_function_name = sh_pfc_pinctrl_get_function_name, 738 739 #if CONFIG_IS_ENABLED(PINCONF) 740 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params), 741 .pinconf_params = sh_pfc_pinconf_params, 742 .pinconf_set = sh_pfc_pinconf_pin_set, 743 .pinconf_group_set = sh_pfc_pinconf_group_set, 744 #endif 745 .pinmux_set = sh_pfc_pinctrl_pin_set, 746 .pinmux_group_set = sh_pfc_pinctrl_group_set, 747 .set_state = pinctrl_generic_set_state, 748 }; 749 750 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 751 { 752 unsigned int i; 753 754 /* Allocate and initialize the pins and configs arrays. */ 755 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins, 756 GFP_KERNEL); 757 if (unlikely(!pmx->configs)) 758 return -ENOMEM; 759 760 for (i = 0; i < pfc->info->nr_pins; ++i) { 761 struct sh_pfc_pin_config *cfg = &pmx->configs[i]; 762 cfg->type = PINMUX_TYPE_NONE; 763 } 764 765 return 0; 766 } 767 768 769 static int sh_pfc_pinctrl_probe(struct udevice *dev) 770 { 771 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 772 enum sh_pfc_model model = dev_get_driver_data(dev); 773 fdt_addr_t base; 774 775 base = devfdt_get_addr(dev); 776 if (base == FDT_ADDR_T_NONE) 777 return -EINVAL; 778 779 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K); 780 if (!priv->pfc.regs) 781 return -ENOMEM; 782 783 #ifdef CONFIG_PINCTRL_PFC_R8A7790 784 if (model == SH_PFC_R8A7790) 785 priv->pfc.info = &r8a7790_pinmux_info; 786 #endif 787 #ifdef CONFIG_PINCTRL_PFC_R8A7791 788 if (model == SH_PFC_R8A7791) 789 priv->pfc.info = &r8a7791_pinmux_info; 790 #endif 791 #ifdef CONFIG_PINCTRL_PFC_R8A7792 792 if (model == SH_PFC_R8A7792) 793 priv->pfc.info = &r8a7792_pinmux_info; 794 #endif 795 #ifdef CONFIG_PINCTRL_PFC_R8A7793 796 if (model == SH_PFC_R8A7793) 797 priv->pfc.info = &r8a7793_pinmux_info; 798 #endif 799 #ifdef CONFIG_PINCTRL_PFC_R8A7794 800 if (model == SH_PFC_R8A7794) 801 priv->pfc.info = &r8a7794_pinmux_info; 802 #endif 803 #ifdef CONFIG_PINCTRL_PFC_R8A7795 804 if (model == SH_PFC_R8A7795) 805 priv->pfc.info = &r8a7795_pinmux_info; 806 #endif 807 #ifdef CONFIG_PINCTRL_PFC_R8A7796 808 if (model == SH_PFC_R8A7796) 809 priv->pfc.info = &r8a7796_pinmux_info; 810 #endif 811 #ifdef CONFIG_PINCTRL_PFC_R8A77970 812 if (model == SH_PFC_R8A77970) 813 priv->pfc.info = &r8a77970_pinmux_info; 814 #endif 815 #ifdef CONFIG_PINCTRL_PFC_R8A77990 816 if (model == SH_PFC_R8A77990) 817 priv->pfc.info = &r8a77990_pinmux_info; 818 #endif 819 #ifdef CONFIG_PINCTRL_PFC_R8A77995 820 if (model == SH_PFC_R8A77995) 821 priv->pfc.info = &r8a77995_pinmux_info; 822 #endif 823 824 priv->pmx.pfc = &priv->pfc; 825 sh_pfc_init_ranges(&priv->pfc); 826 sh_pfc_map_pins(&priv->pfc, &priv->pmx); 827 828 return 0; 829 } 830 831 static const struct udevice_id sh_pfc_pinctrl_ids[] = { 832 #ifdef CONFIG_PINCTRL_PFC_R8A7790 833 { 834 .compatible = "renesas,pfc-r8a7790", 835 .data = SH_PFC_R8A7790, 836 }, 837 #endif 838 #ifdef CONFIG_PINCTRL_PFC_R8A7791 839 { 840 .compatible = "renesas,pfc-r8a7791", 841 .data = SH_PFC_R8A7791, 842 }, 843 #endif 844 #ifdef CONFIG_PINCTRL_PFC_R8A7792 845 { 846 .compatible = "renesas,pfc-r8a7792", 847 .data = SH_PFC_R8A7792, 848 }, 849 #endif 850 #ifdef CONFIG_PINCTRL_PFC_R8A7793 851 { 852 .compatible = "renesas,pfc-r8a7793", 853 .data = SH_PFC_R8A7793, 854 }, 855 #endif 856 #ifdef CONFIG_PINCTRL_PFC_R8A7794 857 { 858 .compatible = "renesas,pfc-r8a7794", 859 .data = SH_PFC_R8A7794, 860 }, 861 #endif 862 #ifdef CONFIG_PINCTRL_PFC_R8A7795 863 { 864 .compatible = "renesas,pfc-r8a7795", 865 .data = SH_PFC_R8A7795, 866 }, 867 #endif 868 #ifdef CONFIG_PINCTRL_PFC_R8A7796 869 { 870 .compatible = "renesas,pfc-r8a7796", 871 .data = SH_PFC_R8A7796, 872 }, { 873 .compatible = "renesas,pfc-r8a77965", 874 .data = SH_PFC_R8A7796, 875 }, 876 #endif 877 #ifdef CONFIG_PINCTRL_PFC_R8A77970 878 { 879 .compatible = "renesas,pfc-r8a77970", 880 .data = SH_PFC_R8A77970, 881 }, 882 #endif 883 #ifdef CONFIG_PINCTRL_PFC_R8A77990 884 { 885 .compatible = "renesas,pfc-r8a77990", 886 .data = SH_PFC_R8A77990, 887 }, 888 #endif 889 #ifdef CONFIG_PINCTRL_PFC_R8A77995 890 { 891 .compatible = "renesas,pfc-r8a77995", 892 .data = SH_PFC_R8A77995, 893 }, 894 #endif 895 { }, 896 }; 897 898 U_BOOT_DRIVER(pinctrl_sh_pfc) = { 899 .name = "sh_pfc_pinctrl", 900 .id = UCLASS_PINCTRL, 901 .of_match = sh_pfc_pinctrl_ids, 902 .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv), 903 .ops = &sh_pfc_pinctrl_ops, 904 .probe = sh_pfc_pinctrl_probe, 905 }; 906