1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pin Control driver for SuperH Pin Function Controller. 4 * 5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart 6 * 7 * Copyright (C) 2008 Magnus Damm 8 * Copyright (C) 2009 - 2012 Paul Mundt 9 * Copyright (C) 2017 Marek Vasut 10 */ 11 12 #define DRV_NAME "sh-pfc" 13 14 #include <common.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <dm/pinctrl.h> 18 #include <linux/io.h> 19 #include <linux/sizes.h> 20 21 #include "sh_pfc.h" 22 23 enum sh_pfc_model { 24 SH_PFC_R8A7790 = 0, 25 SH_PFC_R8A7791, 26 SH_PFC_R8A7792, 27 SH_PFC_R8A7793, 28 SH_PFC_R8A7794, 29 SH_PFC_R8A7795, 30 SH_PFC_R8A7796, 31 SH_PFC_R8A77970, 32 SH_PFC_R8A77995, 33 }; 34 35 struct sh_pfc_pin_config { 36 u32 type; 37 }; 38 39 struct sh_pfc_pinctrl { 40 struct sh_pfc *pfc; 41 42 struct sh_pfc_pin_config *configs; 43 44 const char *func_prop_name; 45 const char *groups_prop_name; 46 const char *pins_prop_name; 47 }; 48 49 struct sh_pfc_pin_range { 50 u16 start; 51 u16 end; 52 }; 53 54 struct sh_pfc_pinctrl_priv { 55 struct sh_pfc pfc; 56 struct sh_pfc_pinctrl pmx; 57 }; 58 59 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) 60 { 61 unsigned int offset; 62 unsigned int i; 63 64 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { 65 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; 66 67 if (pin <= range->end) 68 return pin >= range->start 69 ? offset + pin - range->start : -1; 70 71 offset += range->end - range->start + 1; 72 } 73 74 return -EINVAL; 75 } 76 77 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) 78 { 79 if (enum_id < r->begin) 80 return 0; 81 82 if (enum_id > r->end) 83 return 0; 84 85 return 1; 86 } 87 88 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) 89 { 90 switch (reg_width) { 91 case 8: 92 return readb(mapped_reg); 93 case 16: 94 return readw(mapped_reg); 95 case 32: 96 return readl(mapped_reg); 97 } 98 99 BUG(); 100 return 0; 101 } 102 103 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 104 u32 data) 105 { 106 switch (reg_width) { 107 case 8: 108 writeb(data, mapped_reg); 109 return; 110 case 16: 111 writew(data, mapped_reg); 112 return; 113 case 32: 114 writel(data, mapped_reg); 115 return; 116 } 117 118 BUG(); 119 } 120 121 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width) 122 { 123 return sh_pfc_read_raw_reg(pfc->regs + reg, width); 124 } 125 126 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) 127 { 128 void __iomem *unlock_reg = 129 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 130 131 if (pfc->info->unlock_reg) 132 sh_pfc_write_raw_reg(unlock_reg, 32, ~data); 133 134 sh_pfc_write_raw_reg(pfc->regs + reg, width, data); 135 } 136 137 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 138 const struct pinmux_cfg_reg *crp, 139 unsigned int in_pos, 140 void __iomem **mapped_regp, u32 *maskp, 141 unsigned int *posp) 142 { 143 unsigned int k; 144 145 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg; 146 147 if (crp->field_width) { 148 *maskp = (1 << crp->field_width) - 1; 149 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); 150 } else { 151 *maskp = (1 << crp->var_field_width[in_pos]) - 1; 152 *posp = crp->reg_width; 153 for (k = 0; k <= in_pos; k++) 154 *posp -= crp->var_field_width[k]; 155 } 156 } 157 158 static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 159 const struct pinmux_cfg_reg *crp, 160 unsigned int field, u32 value) 161 { 162 void __iomem *mapped_reg; 163 void __iomem *unlock_reg = 164 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 165 unsigned int pos; 166 u32 mask, data; 167 168 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 169 170 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " 171 "r_width = %u, f_width = %u\n", 172 crp->reg, value, field, crp->reg_width, crp->field_width); 173 174 mask = ~(mask << pos); 175 value = value << pos; 176 177 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); 178 data &= mask; 179 data |= value; 180 181 if (pfc->info->unlock_reg) 182 sh_pfc_write_raw_reg(unlock_reg, 32, ~data); 183 184 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); 185 } 186 187 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, 188 const struct pinmux_cfg_reg **crp, 189 unsigned int *fieldp, u32 *valuep) 190 { 191 unsigned int k = 0; 192 193 while (1) { 194 const struct pinmux_cfg_reg *config_reg = 195 pfc->info->cfg_regs + k; 196 unsigned int r_width = config_reg->reg_width; 197 unsigned int f_width = config_reg->field_width; 198 unsigned int curr_width; 199 unsigned int bit_pos; 200 unsigned int pos = 0; 201 unsigned int m = 0; 202 203 if (!r_width) 204 break; 205 206 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { 207 u32 ncomb; 208 u32 n; 209 210 if (f_width) 211 curr_width = f_width; 212 else 213 curr_width = config_reg->var_field_width[m]; 214 215 ncomb = 1 << curr_width; 216 for (n = 0; n < ncomb; n++) { 217 if (config_reg->enum_ids[pos + n] == enum_id) { 218 *crp = config_reg; 219 *fieldp = m; 220 *valuep = n; 221 return 0; 222 } 223 } 224 pos += ncomb; 225 m++; 226 } 227 k++; 228 } 229 230 return -EINVAL; 231 } 232 233 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, 234 u16 *enum_idp) 235 { 236 const u16 *data = pfc->info->pinmux_data; 237 unsigned int k; 238 239 if (pos) { 240 *enum_idp = data[pos + 1]; 241 return pos + 1; 242 } 243 244 for (k = 0; k < pfc->info->pinmux_data_size; k++) { 245 if (data[k] == mark) { 246 *enum_idp = data[k + 1]; 247 return k + 1; 248 } 249 } 250 251 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", 252 mark); 253 return -EINVAL; 254 } 255 256 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 257 { 258 const struct pinmux_range *range; 259 int pos = 0; 260 261 switch (pinmux_type) { 262 case PINMUX_TYPE_GPIO: 263 case PINMUX_TYPE_FUNCTION: 264 range = NULL; 265 break; 266 267 case PINMUX_TYPE_OUTPUT: 268 range = &pfc->info->output; 269 break; 270 271 case PINMUX_TYPE_INPUT: 272 range = &pfc->info->input; 273 break; 274 275 default: 276 return -EINVAL; 277 } 278 279 /* Iterate over all the configuration fields we need to update. */ 280 while (1) { 281 const struct pinmux_cfg_reg *cr; 282 unsigned int field; 283 u16 enum_id; 284 u32 value; 285 int in_range; 286 int ret; 287 288 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); 289 if (pos < 0) 290 return pos; 291 292 if (!enum_id) 293 break; 294 295 /* Check if the configuration field selects a function. If it 296 * doesn't, skip the field if it's not applicable to the 297 * requested pinmux type. 298 */ 299 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); 300 if (!in_range) { 301 if (pinmux_type == PINMUX_TYPE_FUNCTION) { 302 /* Functions are allowed to modify all 303 * fields. 304 */ 305 in_range = 1; 306 } else if (pinmux_type != PINMUX_TYPE_GPIO) { 307 /* Input/output types can only modify fields 308 * that correspond to their respective ranges. 309 */ 310 in_range = sh_pfc_enum_in_range(enum_id, range); 311 312 /* 313 * special case pass through for fixed 314 * input-only or output-only pins without 315 * function enum register association. 316 */ 317 if (in_range && enum_id == range->force) 318 continue; 319 } 320 /* GPIOs are only allowed to modify function fields. */ 321 } 322 323 if (!in_range) 324 continue; 325 326 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); 327 if (ret < 0) 328 return ret; 329 330 sh_pfc_write_config_reg(pfc, cr, field, value); 331 } 332 333 return 0; 334 } 335 336 const struct sh_pfc_bias_info * 337 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, 338 unsigned int num, unsigned int pin) 339 { 340 unsigned int i; 341 342 for (i = 0; i < num; i++) 343 if (info[i].pin == pin) 344 return &info[i]; 345 346 printf("Pin %u is not in bias info list\n", pin); 347 348 return NULL; 349 } 350 351 static int sh_pfc_init_ranges(struct sh_pfc *pfc) 352 { 353 struct sh_pfc_pin_range *range; 354 unsigned int nr_ranges; 355 unsigned int i; 356 357 if (pfc->info->pins[0].pin == (u16)-1) { 358 /* Pin number -1 denotes that the SoC doesn't report pin numbers 359 * in its pin arrays yet. Consider the pin numbers range as 360 * continuous and allocate a single range. 361 */ 362 pfc->nr_ranges = 1; 363 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL); 364 if (pfc->ranges == NULL) 365 return -ENOMEM; 366 367 pfc->ranges->start = 0; 368 pfc->ranges->end = pfc->info->nr_pins - 1; 369 pfc->nr_gpio_pins = pfc->info->nr_pins; 370 371 return 0; 372 } 373 374 /* Count, allocate and fill the ranges. The PFC SoC data pins array must 375 * be sorted by pin numbers, and pins without a GPIO port must come 376 * last. 377 */ 378 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { 379 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) 380 nr_ranges++; 381 } 382 383 pfc->nr_ranges = nr_ranges; 384 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL); 385 if (pfc->ranges == NULL) 386 return -ENOMEM; 387 388 range = pfc->ranges; 389 range->start = pfc->info->pins[0].pin; 390 391 for (i = 1; i < pfc->info->nr_pins; ++i) { 392 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) 393 continue; 394 395 range->end = pfc->info->pins[i-1].pin; 396 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 397 pfc->nr_gpio_pins = range->end + 1; 398 399 range++; 400 range->start = pfc->info->pins[i].pin; 401 } 402 403 range->end = pfc->info->pins[i-1].pin; 404 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 405 pfc->nr_gpio_pins = range->end + 1; 406 407 return 0; 408 } 409 410 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev) 411 { 412 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 413 414 return priv->pfc.info->nr_pins; 415 } 416 417 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev, 418 unsigned selector) 419 { 420 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 421 422 return priv->pfc.info->pins[selector].name; 423 } 424 425 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev) 426 { 427 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 428 429 return priv->pfc.info->nr_groups; 430 } 431 432 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev, 433 unsigned selector) 434 { 435 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 436 437 return priv->pfc.info->groups[selector].name; 438 } 439 440 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev) 441 { 442 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 443 444 return priv->pfc.info->nr_functions; 445 } 446 447 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, 448 unsigned selector) 449 { 450 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 451 452 return priv->pfc.info->functions[selector].name; 453 } 454 455 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector) 456 { 457 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 458 struct sh_pfc_pinctrl *pmx = &priv->pmx; 459 struct sh_pfc *pfc = &priv->pfc; 460 struct sh_pfc_pin_config *cfg; 461 const struct sh_pfc_pin *pin = NULL; 462 int i, idx; 463 464 for (i = 1; i < pfc->info->nr_pins; i++) { 465 if (priv->pfc.info->pins[i].pin != pin_selector) 466 continue; 467 468 pin = &priv->pfc.info->pins[i]; 469 break; 470 } 471 472 if (!pin) 473 return -EINVAL; 474 475 idx = sh_pfc_get_pin_index(pfc, pin->pin); 476 cfg = &pmx->configs[idx]; 477 478 if (cfg->type != PINMUX_TYPE_NONE) 479 return -EBUSY; 480 481 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); 482 } 483 484 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, 485 unsigned func_selector) 486 { 487 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 488 struct sh_pfc_pinctrl *pmx = &priv->pmx; 489 struct sh_pfc *pfc = &priv->pfc; 490 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector]; 491 int idx = sh_pfc_get_pin_index(pfc, pin->pin); 492 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 493 494 if (cfg->type != PINMUX_TYPE_NONE) 495 return -EBUSY; 496 497 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION); 498 } 499 500 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector, 501 unsigned func_selector) 502 { 503 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 504 struct sh_pfc_pinctrl *pmx = &priv->pmx; 505 struct sh_pfc *pfc = &priv->pfc; 506 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector]; 507 unsigned int i; 508 int ret = 0; 509 510 for (i = 0; i < grp->nr_pins; ++i) { 511 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 512 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 513 514 if (cfg->type != PINMUX_TYPE_NONE) { 515 ret = -EBUSY; 516 goto done; 517 } 518 } 519 520 for (i = 0; i < grp->nr_pins; ++i) { 521 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); 522 if (ret < 0) 523 break; 524 } 525 526 done: 527 return ret; 528 } 529 #if CONFIG_IS_ENABLED(PINCONF) 530 static const struct pinconf_param sh_pfc_pinconf_params[] = { 531 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 532 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 533 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 534 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 535 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 }, 536 }; 537 538 static void __iomem * 539 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin, 540 unsigned int *offset, unsigned int *size) 541 { 542 const struct pinmux_drive_reg_field *field; 543 const struct pinmux_drive_reg *reg; 544 unsigned int i; 545 546 for (reg = pfc->info->drive_regs; reg->reg; ++reg) { 547 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { 548 field = ®->fields[i]; 549 550 if (field->size && field->pin == pin) { 551 *offset = field->offset; 552 *size = field->size; 553 554 return (void __iomem *)(uintptr_t)reg->reg; 555 } 556 } 557 } 558 559 return NULL; 560 } 561 562 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, 563 unsigned int pin, u16 strength) 564 { 565 unsigned int offset; 566 unsigned int size; 567 unsigned int step; 568 void __iomem *reg; 569 void __iomem *unlock_reg = 570 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 571 u32 val; 572 573 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 574 if (!reg) 575 return -EINVAL; 576 577 step = size == 2 ? 6 : 3; 578 579 if (strength < step || strength > 24) 580 return -EINVAL; 581 582 /* Convert the value from mA based on a full drive strength value of 583 * 24mA. We can make the full value configurable later if needed. 584 */ 585 strength = strength / step - 1; 586 587 val = sh_pfc_read_raw_reg(reg, 32); 588 val &= ~GENMASK(offset + size - 1, offset); 589 val |= strength << offset; 590 591 if (unlock_reg) 592 sh_pfc_write_raw_reg(unlock_reg, 32, ~val); 593 594 sh_pfc_write_raw_reg(reg, 32, val); 595 596 return 0; 597 } 598 599 /* Check whether the requested parameter is supported for a pin. */ 600 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, 601 unsigned int param) 602 { 603 int idx = sh_pfc_get_pin_index(pfc, _pin); 604 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 605 606 switch (param) { 607 case PIN_CONFIG_BIAS_DISABLE: 608 return pin->configs & 609 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN); 610 611 case PIN_CONFIG_BIAS_PULL_UP: 612 return pin->configs & SH_PFC_PIN_CFG_PULL_UP; 613 614 case PIN_CONFIG_BIAS_PULL_DOWN: 615 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; 616 617 case PIN_CONFIG_DRIVE_STRENGTH: 618 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; 619 620 case PIN_CONFIG_POWER_SOURCE: 621 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; 622 623 default: 624 return false; 625 } 626 } 627 628 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, 629 unsigned int param, unsigned int arg) 630 { 631 struct sh_pfc *pfc = pmx->pfc; 632 void __iomem *pocctrl; 633 void __iomem *unlock_reg = 634 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 635 u32 addr, val; 636 int bit, ret; 637 638 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 639 return -ENOTSUPP; 640 641 switch (param) { 642 case PIN_CONFIG_BIAS_PULL_UP: 643 case PIN_CONFIG_BIAS_PULL_DOWN: 644 case PIN_CONFIG_BIAS_DISABLE: 645 if (!pfc->info->ops || !pfc->info->ops->set_bias) 646 return -ENOTSUPP; 647 648 pfc->info->ops->set_bias(pfc, _pin, param); 649 650 break; 651 652 case PIN_CONFIG_DRIVE_STRENGTH: 653 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); 654 if (ret < 0) 655 return ret; 656 657 break; 658 659 case PIN_CONFIG_POWER_SOURCE: 660 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 661 return -ENOTSUPP; 662 663 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr); 664 if (bit < 0) { 665 printf("invalid pin %#x", _pin); 666 return bit; 667 } 668 669 if (arg != 1800 && arg != 3300) 670 return -EINVAL; 671 672 pocctrl = (void __iomem *)(uintptr_t)addr; 673 674 val = sh_pfc_read_raw_reg(pocctrl, 32); 675 if (arg == 3300) 676 val |= BIT(bit); 677 else 678 val &= ~BIT(bit); 679 680 if (unlock_reg) 681 sh_pfc_write_raw_reg(unlock_reg, 32, ~val); 682 683 sh_pfc_write_raw_reg(pocctrl, 32, val); 684 685 break; 686 687 default: 688 return -ENOTSUPP; 689 } 690 691 return 0; 692 } 693 694 static int sh_pfc_pinconf_pin_set(struct udevice *dev, 695 unsigned int pin_selector, 696 unsigned int param, unsigned int arg) 697 { 698 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 699 struct sh_pfc_pinctrl *pmx = &priv->pmx; 700 struct sh_pfc *pfc = &priv->pfc; 701 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector]; 702 703 sh_pfc_pinconf_set(pmx, pin->pin, param, arg); 704 705 return 0; 706 } 707 708 static int sh_pfc_pinconf_group_set(struct udevice *dev, 709 unsigned int group_selector, 710 unsigned int param, unsigned int arg) 711 { 712 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 713 struct sh_pfc_pinctrl *pmx = &priv->pmx; 714 struct sh_pfc *pfc = &priv->pfc; 715 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector]; 716 unsigned int i; 717 718 for (i = 0; i < grp->nr_pins; i++) 719 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg); 720 721 return 0; 722 } 723 #endif 724 725 static struct pinctrl_ops sh_pfc_pinctrl_ops = { 726 .get_pins_count = sh_pfc_pinctrl_get_pins_count, 727 .get_pin_name = sh_pfc_pinctrl_get_pin_name, 728 .get_groups_count = sh_pfc_pinctrl_get_groups_count, 729 .get_group_name = sh_pfc_pinctrl_get_group_name, 730 .get_functions_count = sh_pfc_pinctrl_get_functions_count, 731 .get_function_name = sh_pfc_pinctrl_get_function_name, 732 733 #if CONFIG_IS_ENABLED(PINCONF) 734 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params), 735 .pinconf_params = sh_pfc_pinconf_params, 736 .pinconf_set = sh_pfc_pinconf_pin_set, 737 .pinconf_group_set = sh_pfc_pinconf_group_set, 738 #endif 739 .pinmux_set = sh_pfc_pinctrl_pin_set, 740 .pinmux_group_set = sh_pfc_pinctrl_group_set, 741 .set_state = pinctrl_generic_set_state, 742 }; 743 744 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 745 { 746 unsigned int i; 747 748 /* Allocate and initialize the pins and configs arrays. */ 749 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins, 750 GFP_KERNEL); 751 if (unlikely(!pmx->configs)) 752 return -ENOMEM; 753 754 for (i = 0; i < pfc->info->nr_pins; ++i) { 755 struct sh_pfc_pin_config *cfg = &pmx->configs[i]; 756 cfg->type = PINMUX_TYPE_NONE; 757 } 758 759 return 0; 760 } 761 762 763 static int sh_pfc_pinctrl_probe(struct udevice *dev) 764 { 765 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 766 enum sh_pfc_model model = dev_get_driver_data(dev); 767 fdt_addr_t base; 768 769 base = devfdt_get_addr(dev); 770 if (base == FDT_ADDR_T_NONE) 771 return -EINVAL; 772 773 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K); 774 if (!priv->pfc.regs) 775 return -ENOMEM; 776 777 #ifdef CONFIG_PINCTRL_PFC_R8A7790 778 if (model == SH_PFC_R8A7790) 779 priv->pfc.info = &r8a7790_pinmux_info; 780 #endif 781 #ifdef CONFIG_PINCTRL_PFC_R8A7791 782 if (model == SH_PFC_R8A7791) 783 priv->pfc.info = &r8a7791_pinmux_info; 784 #endif 785 #ifdef CONFIG_PINCTRL_PFC_R8A7792 786 if (model == SH_PFC_R8A7792) 787 priv->pfc.info = &r8a7792_pinmux_info; 788 #endif 789 #ifdef CONFIG_PINCTRL_PFC_R8A7793 790 if (model == SH_PFC_R8A7793) 791 priv->pfc.info = &r8a7793_pinmux_info; 792 #endif 793 #ifdef CONFIG_PINCTRL_PFC_R8A7794 794 if (model == SH_PFC_R8A7794) 795 priv->pfc.info = &r8a7794_pinmux_info; 796 #endif 797 #ifdef CONFIG_PINCTRL_PFC_R8A7795 798 if (model == SH_PFC_R8A7795) 799 priv->pfc.info = &r8a7795_pinmux_info; 800 #endif 801 #ifdef CONFIG_PINCTRL_PFC_R8A7796 802 if (model == SH_PFC_R8A7796) 803 priv->pfc.info = &r8a7796_pinmux_info; 804 #endif 805 #ifdef CONFIG_PINCTRL_PFC_R8A77970 806 if (model == SH_PFC_R8A77970) 807 priv->pfc.info = &r8a77970_pinmux_info; 808 #endif 809 #ifdef CONFIG_PINCTRL_PFC_R8A77995 810 if (model == SH_PFC_R8A77995) 811 priv->pfc.info = &r8a77995_pinmux_info; 812 #endif 813 814 priv->pmx.pfc = &priv->pfc; 815 sh_pfc_init_ranges(&priv->pfc); 816 sh_pfc_map_pins(&priv->pfc, &priv->pmx); 817 818 return 0; 819 } 820 821 static const struct udevice_id sh_pfc_pinctrl_ids[] = { 822 #ifdef CONFIG_PINCTRL_PFC_R8A7790 823 { 824 .compatible = "renesas,pfc-r8a7790", 825 .data = SH_PFC_R8A7790, 826 }, 827 #endif 828 #ifdef CONFIG_PINCTRL_PFC_R8A7791 829 { 830 .compatible = "renesas,pfc-r8a7791", 831 .data = SH_PFC_R8A7791, 832 }, 833 #endif 834 #ifdef CONFIG_PINCTRL_PFC_R8A7792 835 { 836 .compatible = "renesas,pfc-r8a7792", 837 .data = SH_PFC_R8A7792, 838 }, 839 #endif 840 #ifdef CONFIG_PINCTRL_PFC_R8A7793 841 { 842 .compatible = "renesas,pfc-r8a7793", 843 .data = SH_PFC_R8A7793, 844 }, 845 #endif 846 #ifdef CONFIG_PINCTRL_PFC_R8A7794 847 { 848 .compatible = "renesas,pfc-r8a7794", 849 .data = SH_PFC_R8A7794, 850 }, 851 #endif 852 #ifdef CONFIG_PINCTRL_PFC_R8A7795 853 { 854 .compatible = "renesas,pfc-r8a7795", 855 .data = SH_PFC_R8A7795, 856 }, 857 #endif 858 #ifdef CONFIG_PINCTRL_PFC_R8A7796 859 { 860 .compatible = "renesas,pfc-r8a7796", 861 .data = SH_PFC_R8A7796, 862 }, { 863 .compatible = "renesas,pfc-r8a77965", 864 .data = SH_PFC_R8A7796, 865 }, 866 #endif 867 #ifdef CONFIG_PINCTRL_PFC_R8A77970 868 { 869 .compatible = "renesas,pfc-r8a77970", 870 .data = SH_PFC_R8A77970, 871 }, 872 #endif 873 #ifdef CONFIG_PINCTRL_PFC_R8A77995 874 { 875 .compatible = "renesas,pfc-r8a77995", 876 .data = SH_PFC_R8A77995, 877 }, 878 #endif 879 { }, 880 }; 881 882 U_BOOT_DRIVER(pinctrl_sh_pfc) = { 883 .name = "sh_pfc_pinctrl", 884 .id = UCLASS_PINCTRL, 885 .of_match = sh_pfc_pinctrl_ids, 886 .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv), 887 .ops = &sh_pfc_pinctrl_ops, 888 .probe = sh_pfc_pinctrl_probe, 889 }; 890