1 /* 2 * Pin Control driver for SuperH Pin Function Controller. 3 * 4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart 5 * 6 * Copyright (C) 2008 Magnus Damm 7 * Copyright (C) 2009 - 2012 Paul Mundt 8 * Copyright (C) 2017 Marek Vasut 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #define DRV_NAME "sh-pfc" 14 15 #include <common.h> 16 #include <dm.h> 17 #include <errno.h> 18 #include <dm/pinctrl.h> 19 #include <linux/io.h> 20 #include <linux/sizes.h> 21 22 #include "sh_pfc.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 enum sh_pfc_model { 27 SH_PFC_R8A7795 = 0, 28 SH_PFC_R8A7796, 29 SH_PFC_R8A77970, 30 SH_PFC_R8A77995, 31 }; 32 33 struct sh_pfc_pin_config { 34 u32 type; 35 }; 36 37 struct sh_pfc_pinctrl { 38 struct sh_pfc *pfc; 39 40 struct sh_pfc_pin_config *configs; 41 42 const char *func_prop_name; 43 const char *groups_prop_name; 44 const char *pins_prop_name; 45 }; 46 47 struct sh_pfc_pin_range { 48 u16 start; 49 u16 end; 50 }; 51 52 struct sh_pfc_pinctrl_priv { 53 struct sh_pfc pfc; 54 struct sh_pfc_pinctrl pmx; 55 }; 56 57 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) 58 { 59 unsigned int offset; 60 unsigned int i; 61 62 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { 63 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; 64 65 if (pin <= range->end) 66 return pin >= range->start 67 ? offset + pin - range->start : -1; 68 69 offset += range->end - range->start + 1; 70 } 71 72 return -EINVAL; 73 } 74 75 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) 76 { 77 if (enum_id < r->begin) 78 return 0; 79 80 if (enum_id > r->end) 81 return 0; 82 83 return 1; 84 } 85 86 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) 87 { 88 switch (reg_width) { 89 case 8: 90 return readb(mapped_reg); 91 case 16: 92 return readw(mapped_reg); 93 case 32: 94 return readl(mapped_reg); 95 } 96 97 BUG(); 98 return 0; 99 } 100 101 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 102 u32 data) 103 { 104 switch (reg_width) { 105 case 8: 106 writeb(data, mapped_reg); 107 return; 108 case 16: 109 writew(data, mapped_reg); 110 return; 111 case 32: 112 writel(data, mapped_reg); 113 return; 114 } 115 116 BUG(); 117 } 118 119 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width) 120 { 121 return sh_pfc_read_raw_reg(pfc->regs + reg, width); 122 } 123 124 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) 125 { 126 void __iomem *unlock_reg = 127 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 128 129 if (pfc->info->unlock_reg) 130 sh_pfc_write_raw_reg(unlock_reg, 32, ~data); 131 132 sh_pfc_write_raw_reg(pfc->regs + reg, width, data); 133 } 134 135 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 136 const struct pinmux_cfg_reg *crp, 137 unsigned int in_pos, 138 void __iomem **mapped_regp, u32 *maskp, 139 unsigned int *posp) 140 { 141 unsigned int k; 142 143 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg; 144 145 if (crp->field_width) { 146 *maskp = (1 << crp->field_width) - 1; 147 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); 148 } else { 149 *maskp = (1 << crp->var_field_width[in_pos]) - 1; 150 *posp = crp->reg_width; 151 for (k = 0; k <= in_pos; k++) 152 *posp -= crp->var_field_width[k]; 153 } 154 } 155 156 static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 157 const struct pinmux_cfg_reg *crp, 158 unsigned int field, u32 value) 159 { 160 void __iomem *mapped_reg; 161 void __iomem *unlock_reg = 162 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 163 unsigned int pos; 164 u32 mask, data; 165 166 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 167 168 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " 169 "r_width = %u, f_width = %u\n", 170 crp->reg, value, field, crp->reg_width, crp->field_width); 171 172 mask = ~(mask << pos); 173 value = value << pos; 174 175 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); 176 data &= mask; 177 data |= value; 178 179 if (pfc->info->unlock_reg) 180 sh_pfc_write_raw_reg(unlock_reg, 32, ~data); 181 182 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); 183 } 184 185 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, 186 const struct pinmux_cfg_reg **crp, 187 unsigned int *fieldp, u32 *valuep) 188 { 189 unsigned int k = 0; 190 191 while (1) { 192 const struct pinmux_cfg_reg *config_reg = 193 pfc->info->cfg_regs + k; 194 unsigned int r_width = config_reg->reg_width; 195 unsigned int f_width = config_reg->field_width; 196 unsigned int curr_width; 197 unsigned int bit_pos; 198 unsigned int pos = 0; 199 unsigned int m = 0; 200 201 if (!r_width) 202 break; 203 204 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { 205 u32 ncomb; 206 u32 n; 207 208 if (f_width) 209 curr_width = f_width; 210 else 211 curr_width = config_reg->var_field_width[m]; 212 213 ncomb = 1 << curr_width; 214 for (n = 0; n < ncomb; n++) { 215 if (config_reg->enum_ids[pos + n] == enum_id) { 216 *crp = config_reg; 217 *fieldp = m; 218 *valuep = n; 219 return 0; 220 } 221 } 222 pos += ncomb; 223 m++; 224 } 225 k++; 226 } 227 228 return -EINVAL; 229 } 230 231 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, 232 u16 *enum_idp) 233 { 234 const u16 *data = pfc->info->pinmux_data; 235 unsigned int k; 236 237 if (pos) { 238 *enum_idp = data[pos + 1]; 239 return pos + 1; 240 } 241 242 for (k = 0; k < pfc->info->pinmux_data_size; k++) { 243 if (data[k] == mark) { 244 *enum_idp = data[k + 1]; 245 return k + 1; 246 } 247 } 248 249 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", 250 mark); 251 return -EINVAL; 252 } 253 254 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 255 { 256 const struct pinmux_range *range; 257 int pos = 0; 258 259 switch (pinmux_type) { 260 case PINMUX_TYPE_GPIO: 261 case PINMUX_TYPE_FUNCTION: 262 range = NULL; 263 break; 264 265 case PINMUX_TYPE_OUTPUT: 266 range = &pfc->info->output; 267 break; 268 269 case PINMUX_TYPE_INPUT: 270 range = &pfc->info->input; 271 break; 272 273 default: 274 return -EINVAL; 275 } 276 277 /* Iterate over all the configuration fields we need to update. */ 278 while (1) { 279 const struct pinmux_cfg_reg *cr; 280 unsigned int field; 281 u16 enum_id; 282 u32 value; 283 int in_range; 284 int ret; 285 286 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); 287 if (pos < 0) 288 return pos; 289 290 if (!enum_id) 291 break; 292 293 /* Check if the configuration field selects a function. If it 294 * doesn't, skip the field if it's not applicable to the 295 * requested pinmux type. 296 */ 297 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); 298 if (!in_range) { 299 if (pinmux_type == PINMUX_TYPE_FUNCTION) { 300 /* Functions are allowed to modify all 301 * fields. 302 */ 303 in_range = 1; 304 } else if (pinmux_type != PINMUX_TYPE_GPIO) { 305 /* Input/output types can only modify fields 306 * that correspond to their respective ranges. 307 */ 308 in_range = sh_pfc_enum_in_range(enum_id, range); 309 310 /* 311 * special case pass through for fixed 312 * input-only or output-only pins without 313 * function enum register association. 314 */ 315 if (in_range && enum_id == range->force) 316 continue; 317 } 318 /* GPIOs are only allowed to modify function fields. */ 319 } 320 321 if (!in_range) 322 continue; 323 324 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); 325 if (ret < 0) 326 return ret; 327 328 sh_pfc_write_config_reg(pfc, cr, field, value); 329 } 330 331 return 0; 332 } 333 334 const struct sh_pfc_bias_info * 335 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, 336 unsigned int num, unsigned int pin) 337 { 338 unsigned int i; 339 340 for (i = 0; i < num; i++) 341 if (info[i].pin == pin) 342 return &info[i]; 343 344 printf("Pin %u is not in bias info list\n", pin); 345 346 return NULL; 347 } 348 349 static int sh_pfc_init_ranges(struct sh_pfc *pfc) 350 { 351 struct sh_pfc_pin_range *range; 352 unsigned int nr_ranges; 353 unsigned int i; 354 355 if (pfc->info->pins[0].pin == (u16)-1) { 356 /* Pin number -1 denotes that the SoC doesn't report pin numbers 357 * in its pin arrays yet. Consider the pin numbers range as 358 * continuous and allocate a single range. 359 */ 360 pfc->nr_ranges = 1; 361 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL); 362 if (pfc->ranges == NULL) 363 return -ENOMEM; 364 365 pfc->ranges->start = 0; 366 pfc->ranges->end = pfc->info->nr_pins - 1; 367 pfc->nr_gpio_pins = pfc->info->nr_pins; 368 369 return 0; 370 } 371 372 /* Count, allocate and fill the ranges. The PFC SoC data pins array must 373 * be sorted by pin numbers, and pins without a GPIO port must come 374 * last. 375 */ 376 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { 377 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) 378 nr_ranges++; 379 } 380 381 pfc->nr_ranges = nr_ranges; 382 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL); 383 if (pfc->ranges == NULL) 384 return -ENOMEM; 385 386 range = pfc->ranges; 387 range->start = pfc->info->pins[0].pin; 388 389 for (i = 1; i < pfc->info->nr_pins; ++i) { 390 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) 391 continue; 392 393 range->end = pfc->info->pins[i-1].pin; 394 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 395 pfc->nr_gpio_pins = range->end + 1; 396 397 range++; 398 range->start = pfc->info->pins[i].pin; 399 } 400 401 range->end = pfc->info->pins[i-1].pin; 402 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 403 pfc->nr_gpio_pins = range->end + 1; 404 405 return 0; 406 } 407 408 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev) 409 { 410 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 411 412 return priv->pfc.info->nr_pins; 413 } 414 415 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev, 416 unsigned selector) 417 { 418 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 419 420 return priv->pfc.info->pins[selector].name; 421 } 422 423 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev) 424 { 425 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 426 427 return priv->pfc.info->nr_groups; 428 } 429 430 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev, 431 unsigned selector) 432 { 433 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 434 435 return priv->pfc.info->groups[selector].name; 436 } 437 438 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev) 439 { 440 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 441 442 return priv->pfc.info->nr_functions; 443 } 444 445 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, 446 unsigned selector) 447 { 448 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 449 450 return priv->pfc.info->functions[selector].name; 451 } 452 453 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector) 454 { 455 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 456 struct sh_pfc_pinctrl *pmx = &priv->pmx; 457 struct sh_pfc *pfc = &priv->pfc; 458 struct sh_pfc_pin_config *cfg; 459 const struct sh_pfc_pin *pin = NULL; 460 int i, idx; 461 462 for (i = 1; i < pfc->info->nr_pins; i++) { 463 if (priv->pfc.info->pins[i].pin != pin_selector) 464 continue; 465 466 pin = &priv->pfc.info->pins[i]; 467 break; 468 } 469 470 if (!pin) 471 return -EINVAL; 472 473 idx = sh_pfc_get_pin_index(pfc, pin->pin); 474 cfg = &pmx->configs[idx]; 475 476 if (cfg->type != PINMUX_TYPE_NONE) 477 return -EBUSY; 478 479 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); 480 } 481 482 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, 483 unsigned func_selector) 484 { 485 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 486 struct sh_pfc_pinctrl *pmx = &priv->pmx; 487 struct sh_pfc *pfc = &priv->pfc; 488 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector]; 489 int idx = sh_pfc_get_pin_index(pfc, pin->pin); 490 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 491 492 if (cfg->type != PINMUX_TYPE_NONE) 493 return -EBUSY; 494 495 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION); 496 } 497 498 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector, 499 unsigned func_selector) 500 { 501 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 502 struct sh_pfc_pinctrl *pmx = &priv->pmx; 503 struct sh_pfc *pfc = &priv->pfc; 504 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector]; 505 unsigned int i; 506 int ret = 0; 507 508 for (i = 0; i < grp->nr_pins; ++i) { 509 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 510 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 511 512 if (cfg->type != PINMUX_TYPE_NONE) { 513 ret = -EBUSY; 514 goto done; 515 } 516 } 517 518 for (i = 0; i < grp->nr_pins; ++i) { 519 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); 520 if (ret < 0) 521 break; 522 } 523 524 done: 525 return ret; 526 } 527 #if CONFIG_IS_ENABLED(PINCONF) 528 static const struct pinconf_param sh_pfc_pinconf_params[] = { 529 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 530 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 531 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 532 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 533 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 }, 534 }; 535 536 static void __iomem * 537 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin, 538 unsigned int *offset, unsigned int *size) 539 { 540 const struct pinmux_drive_reg_field *field; 541 const struct pinmux_drive_reg *reg; 542 unsigned int i; 543 544 for (reg = pfc->info->drive_regs; reg->reg; ++reg) { 545 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { 546 field = ®->fields[i]; 547 548 if (field->size && field->pin == pin) { 549 *offset = field->offset; 550 *size = field->size; 551 552 return (void __iomem *)(uintptr_t)reg->reg; 553 } 554 } 555 } 556 557 return NULL; 558 } 559 560 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, 561 unsigned int pin, u16 strength) 562 { 563 unsigned int offset; 564 unsigned int size; 565 unsigned int step; 566 void __iomem *reg; 567 void __iomem *unlock_reg = 568 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 569 u32 val; 570 571 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 572 if (!reg) 573 return -EINVAL; 574 575 step = size == 2 ? 6 : 3; 576 577 if (strength < step || strength > 24) 578 return -EINVAL; 579 580 /* Convert the value from mA based on a full drive strength value of 581 * 24mA. We can make the full value configurable later if needed. 582 */ 583 strength = strength / step - 1; 584 585 val = sh_pfc_read_raw_reg(reg, 32); 586 val &= ~GENMASK(offset + size - 1, offset); 587 val |= strength << offset; 588 589 if (unlock_reg) 590 sh_pfc_write_raw_reg(unlock_reg, 32, ~val); 591 592 sh_pfc_write_raw_reg(reg, 32, val); 593 594 return 0; 595 } 596 597 /* Check whether the requested parameter is supported for a pin. */ 598 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, 599 unsigned int param) 600 { 601 int idx = sh_pfc_get_pin_index(pfc, _pin); 602 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 603 604 switch (param) { 605 case PIN_CONFIG_BIAS_DISABLE: 606 return pin->configs & 607 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN); 608 609 case PIN_CONFIG_BIAS_PULL_UP: 610 return pin->configs & SH_PFC_PIN_CFG_PULL_UP; 611 612 case PIN_CONFIG_BIAS_PULL_DOWN: 613 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; 614 615 case PIN_CONFIG_DRIVE_STRENGTH: 616 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; 617 618 case PIN_CONFIG_POWER_SOURCE: 619 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; 620 621 default: 622 return false; 623 } 624 } 625 626 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, 627 unsigned int param, unsigned int arg) 628 { 629 struct sh_pfc *pfc = pmx->pfc; 630 void __iomem *pocctrl; 631 void __iomem *unlock_reg = 632 (void __iomem *)(uintptr_t)pfc->info->unlock_reg; 633 u32 addr, val; 634 int bit, ret; 635 636 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 637 return -ENOTSUPP; 638 639 switch (param) { 640 case PIN_CONFIG_BIAS_PULL_UP: 641 case PIN_CONFIG_BIAS_PULL_DOWN: 642 case PIN_CONFIG_BIAS_DISABLE: 643 if (!pfc->info->ops || !pfc->info->ops->set_bias) 644 return -ENOTSUPP; 645 646 pfc->info->ops->set_bias(pfc, _pin, param); 647 648 break; 649 650 case PIN_CONFIG_DRIVE_STRENGTH: 651 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); 652 if (ret < 0) 653 return ret; 654 655 break; 656 657 case PIN_CONFIG_POWER_SOURCE: 658 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 659 return -ENOTSUPP; 660 661 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr); 662 if (bit < 0) { 663 printf("invalid pin %#x", _pin); 664 return bit; 665 } 666 667 if (arg != 1800 && arg != 3300) 668 return -EINVAL; 669 670 pocctrl = (void __iomem *)(uintptr_t)addr; 671 672 val = sh_pfc_read_raw_reg(pocctrl, 32); 673 if (arg == 3300) 674 val |= BIT(bit); 675 else 676 val &= ~BIT(bit); 677 678 if (unlock_reg) 679 sh_pfc_write_raw_reg(unlock_reg, 32, ~val); 680 681 sh_pfc_write_raw_reg(pocctrl, 32, val); 682 683 break; 684 685 default: 686 return -ENOTSUPP; 687 } 688 689 return 0; 690 } 691 692 static int sh_pfc_pinconf_pin_set(struct udevice *dev, 693 unsigned int pin_selector, 694 unsigned int param, unsigned int arg) 695 { 696 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 697 struct sh_pfc_pinctrl *pmx = &priv->pmx; 698 struct sh_pfc *pfc = &priv->pfc; 699 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector]; 700 701 sh_pfc_pinconf_set(pmx, pin->pin, param, arg); 702 703 return 0; 704 } 705 706 static int sh_pfc_pinconf_group_set(struct udevice *dev, 707 unsigned int group_selector, 708 unsigned int param, unsigned int arg) 709 { 710 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 711 struct sh_pfc_pinctrl *pmx = &priv->pmx; 712 struct sh_pfc *pfc = &priv->pfc; 713 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector]; 714 unsigned int i; 715 716 for (i = 0; i < grp->nr_pins; i++) 717 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg); 718 719 return 0; 720 } 721 #endif 722 723 static struct pinctrl_ops sh_pfc_pinctrl_ops = { 724 .get_pins_count = sh_pfc_pinctrl_get_pins_count, 725 .get_pin_name = sh_pfc_pinctrl_get_pin_name, 726 .get_groups_count = sh_pfc_pinctrl_get_groups_count, 727 .get_group_name = sh_pfc_pinctrl_get_group_name, 728 .get_functions_count = sh_pfc_pinctrl_get_functions_count, 729 .get_function_name = sh_pfc_pinctrl_get_function_name, 730 731 #if CONFIG_IS_ENABLED(PINCONF) 732 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params), 733 .pinconf_params = sh_pfc_pinconf_params, 734 .pinconf_set = sh_pfc_pinconf_pin_set, 735 .pinconf_group_set = sh_pfc_pinconf_group_set, 736 #endif 737 .pinmux_set = sh_pfc_pinctrl_pin_set, 738 .pinmux_group_set = sh_pfc_pinctrl_group_set, 739 .set_state = pinctrl_generic_set_state, 740 }; 741 742 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 743 { 744 unsigned int i; 745 746 /* Allocate and initialize the pins and configs arrays. */ 747 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins, 748 GFP_KERNEL); 749 if (unlikely(!pmx->configs)) 750 return -ENOMEM; 751 752 for (i = 0; i < pfc->info->nr_pins; ++i) { 753 struct sh_pfc_pin_config *cfg = &pmx->configs[i]; 754 cfg->type = PINMUX_TYPE_NONE; 755 } 756 757 return 0; 758 } 759 760 761 static int sh_pfc_pinctrl_probe(struct udevice *dev) 762 { 763 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); 764 enum sh_pfc_model model = dev_get_driver_data(dev); 765 fdt_addr_t base; 766 767 base = devfdt_get_addr(dev); 768 if (base == FDT_ADDR_T_NONE) 769 return -EINVAL; 770 771 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K); 772 if (!priv->pfc.regs) 773 return -ENOMEM; 774 775 #ifdef CONFIG_PINCTRL_PFC_R8A7795 776 if (model == SH_PFC_R8A7795) 777 priv->pfc.info = &r8a7795_pinmux_info; 778 #endif 779 #ifdef CONFIG_PINCTRL_PFC_R8A7796 780 if (model == SH_PFC_R8A7796) 781 priv->pfc.info = &r8a7796_pinmux_info; 782 #endif 783 #ifdef CONFIG_PINCTRL_PFC_R8A77970 784 if (model == SH_PFC_R8A77970) 785 priv->pfc.info = &r8a77970_pinmux_info; 786 #endif 787 #ifdef CONFIG_PINCTRL_PFC_R8A77995 788 if (model == SH_PFC_R8A77995) 789 priv->pfc.info = &r8a77995_pinmux_info; 790 #endif 791 792 priv->pmx.pfc = &priv->pfc; 793 sh_pfc_init_ranges(&priv->pfc); 794 sh_pfc_map_pins(&priv->pfc, &priv->pmx); 795 796 return 0; 797 } 798 799 static const struct udevice_id sh_pfc_pinctrl_ids[] = { 800 #ifdef CONFIG_PINCTRL_PFC_R8A7795 801 { 802 .compatible = "renesas,pfc-r8a7795", 803 .data = SH_PFC_R8A7795, 804 }, 805 #endif 806 #ifdef CONFIG_PINCTRL_PFC_R8A7796 807 { 808 .compatible = "renesas,pfc-r8a7796", 809 .data = SH_PFC_R8A7796, 810 }, 811 #endif 812 #ifdef CONFIG_PINCTRL_PFC_R8A77970 813 { 814 .compatible = "renesas,pfc-r8a77970", 815 .data = SH_PFC_R8A77970, 816 }, 817 #endif 818 #ifdef CONFIG_PINCTRL_PFC_R8A77995 819 { 820 .compatible = "renesas,pfc-r8a77995", 821 .data = SH_PFC_R8A77995, 822 }, 823 #endif 824 { }, 825 }; 826 827 U_BOOT_DRIVER(pinctrl_sh_pfc) = { 828 .name = "sh_pfc_pinctrl", 829 .id = UCLASS_PINCTRL, 830 .of_match = sh_pfc_pinctrl_ids, 831 .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv), 832 .ops = &sh_pfc_pinctrl_ops, 833 .probe = sh_pfc_pinctrl_probe, 834 }; 835