1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77995 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2017 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c 8 * 9 * R-Car Gen3 processor support - PFC hardware block. 10 * 11 * Copyright (C) 2015 Renesas Electronics Corporation 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <dm/pinctrl.h> 18 #include <linux/kernel.h> 19 20 #include "sh_pfc.h" 21 22 #define CPU_ALL_PORT(fn, sfx) \ 23 PORT_GP_9(0, fn, sfx), \ 24 PORT_GP_32(1, fn, sfx), \ 25 PORT_GP_32(2, fn, sfx), \ 26 PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 27 PORT_GP_32(4, fn, sfx), \ 28 PORT_GP_21(5, fn, sfx), \ 29 PORT_GP_14(6, fn, sfx) 30 31 /* 32 * F_() : just information 33 * FM() : macro for FN_xxx / xxx_MARK 34 */ 35 36 /* GPSR0 */ 37 #define GPSR0_8 F_(MLB_SIG, IP0_27_24) 38 #define GPSR0_7 F_(MLB_DAT, IP0_23_20) 39 #define GPSR0_6 F_(MLB_CLK, IP0_19_16) 40 #define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12) 41 #define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8) 42 #define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4) 43 #define GPSR0_2 F_(IRQ0_A, IP0_3_0) 44 #define GPSR0_1 FM(USB0_OVC) 45 #define GPSR0_0 FM(USB0_PWEN) 46 47 /* GPSR1 */ 48 #define GPSR1_31 F_(QPOLB, IP4_27_24) 49 #define GPSR1_30 F_(QPOLA, IP4_23_20) 50 #define GPSR1_29 F_(DU_CDE, IP4_19_16) 51 #define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12) 52 #define GPSR1_27 F_(DU_DISP, IP4_11_8) 53 #define GPSR1_26 F_(DU_VSYNC, IP4_7_4) 54 #define GPSR1_25 F_(DU_HSYNC, IP4_3_0) 55 #define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28) 56 #define GPSR1_23 F_(DU_DR7, IP3_27_24) 57 #define GPSR1_22 F_(DU_DR6, IP3_23_20) 58 #define GPSR1_21 F_(DU_DR5, IP3_19_16) 59 #define GPSR1_20 F_(DU_DR4, IP3_15_12) 60 #define GPSR1_19 F_(DU_DR3, IP3_11_8) 61 #define GPSR1_18 F_(DU_DR2, IP3_7_4) 62 #define GPSR1_17 F_(DU_DR1, IP3_3_0) 63 #define GPSR1_16 F_(DU_DR0, IP2_31_28) 64 #define GPSR1_15 F_(DU_DG7, IP2_27_24) 65 #define GPSR1_14 F_(DU_DG6, IP2_23_20) 66 #define GPSR1_13 F_(DU_DG5, IP2_19_16) 67 #define GPSR1_12 F_(DU_DG4, IP2_15_12) 68 #define GPSR1_11 F_(DU_DG3, IP2_11_8) 69 #define GPSR1_10 F_(DU_DG2, IP2_7_4) 70 #define GPSR1_9 F_(DU_DG1, IP2_3_0) 71 #define GPSR1_8 F_(DU_DG0, IP1_31_28) 72 #define GPSR1_7 F_(DU_DB7, IP1_27_24) 73 #define GPSR1_6 F_(DU_DB6, IP1_23_20) 74 #define GPSR1_5 F_(DU_DB5, IP1_19_16) 75 #define GPSR1_4 F_(DU_DB4, IP1_15_12) 76 #define GPSR1_3 F_(DU_DB3, IP1_11_8) 77 #define GPSR1_2 F_(DU_DB2, IP1_7_4) 78 #define GPSR1_1 F_(DU_DB1, IP1_3_0) 79 #define GPSR1_0 F_(DU_DB0, IP0_31_28) 80 81 /* GPSR2 */ 82 #define GPSR2_31 F_(NFCE_N, IP8_19_16) 83 #define GPSR2_30 F_(NFCLE, IP8_15_12) 84 #define GPSR2_29 F_(NFALE, IP8_11_8) 85 #define GPSR2_28 F_(VI4_CLKENB, IP8_7_4) 86 #define GPSR2_27 F_(VI4_FIELD, IP8_3_0) 87 #define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28) 88 #define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24) 89 #define GPSR2_24 F_(VI4_DATA23, IP7_23_20) 90 #define GPSR2_23 F_(VI4_DATA22, IP7_19_16) 91 #define GPSR2_22 F_(VI4_DATA21, IP7_15_12) 92 #define GPSR2_21 F_(VI4_DATA20, IP7_11_8) 93 #define GPSR2_20 F_(VI4_DATA19, IP7_7_4) 94 #define GPSR2_19 F_(VI4_DATA18, IP7_3_0) 95 #define GPSR2_18 F_(VI4_DATA17, IP6_31_28) 96 #define GPSR2_17 F_(VI4_DATA16, IP6_27_24) 97 #define GPSR2_16 F_(VI4_DATA15, IP6_23_20) 98 #define GPSR2_15 F_(VI4_DATA14, IP6_19_16) 99 #define GPSR2_14 F_(VI4_DATA13, IP6_15_12) 100 #define GPSR2_13 F_(VI4_DATA12, IP6_11_8) 101 #define GPSR2_12 F_(VI4_DATA11, IP6_7_4) 102 #define GPSR2_11 F_(VI4_DATA10, IP6_3_0) 103 #define GPSR2_10 F_(VI4_DATA9, IP5_31_28) 104 #define GPSR2_9 F_(VI4_DATA8, IP5_27_24) 105 #define GPSR2_8 F_(VI4_DATA7, IP5_23_20) 106 #define GPSR2_7 F_(VI4_DATA6, IP5_19_16) 107 #define GPSR2_6 F_(VI4_DATA5, IP5_15_12) 108 #define GPSR2_5 FM(VI4_DATA4) 109 #define GPSR2_4 F_(VI4_DATA3, IP5_11_8) 110 #define GPSR2_3 F_(VI4_DATA2, IP5_7_4) 111 #define GPSR2_2 F_(VI4_DATA1, IP5_3_0) 112 #define GPSR2_1 F_(VI4_DATA0, IP4_31_28) 113 #define GPSR2_0 FM(VI4_CLK) 114 115 /* GPSR3 */ 116 #define GPSR3_9 F_(NFDATA7, IP9_31_28) 117 #define GPSR3_8 F_(NFDATA6, IP9_27_24) 118 #define GPSR3_7 F_(NFDATA5, IP9_23_20) 119 #define GPSR3_6 F_(NFDATA4, IP9_19_16) 120 #define GPSR3_5 F_(NFDATA3, IP9_15_12) 121 #define GPSR3_4 F_(NFDATA2, IP9_11_8) 122 #define GPSR3_3 F_(NFDATA1, IP9_7_4) 123 #define GPSR3_2 F_(NFDATA0, IP9_3_0) 124 #define GPSR3_1 F_(NFWE_N, IP8_31_28) 125 #define GPSR3_0 F_(NFRE_N, IP8_27_24) 126 127 /* GPSR4 */ 128 #define GPSR4_31 F_(CAN0_RX_A, IP12_27_24) 129 #define GPSR4_30 F_(CAN1_TX_A, IP13_7_4) 130 #define GPSR4_29 F_(CAN1_RX_A, IP13_3_0) 131 #define GPSR4_28 F_(CAN0_TX_A, IP12_31_28) 132 #define GPSR4_27 FM(TX2) 133 #define GPSR4_26 FM(RX2) 134 #define GPSR4_25 F_(SCK2, IP12_11_8) 135 #define GPSR4_24 F_(TX1_A, IP12_7_4) 136 #define GPSR4_23 F_(RX1_A, IP12_3_0) 137 #define GPSR4_22 F_(SCK1_A, IP11_31_28) 138 #define GPSR4_21 F_(TX0_A, IP11_27_24) 139 #define GPSR4_20 F_(RX0_A, IP11_23_20) 140 #define GPSR4_19 F_(SCK0_A, IP11_19_16) 141 #define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12) 142 #define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8) 143 #define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4) 144 #define GPSR4_15 FM(MSIOF0_RXD) 145 #define GPSR4_14 FM(MSIOF0_TXD) 146 #define GPSR4_13 FM(MSIOF0_SYNC) 147 #define GPSR4_12 FM(MSIOF0_SCK) 148 #define GPSR4_11 F_(SDA1, IP11_3_0) 149 #define GPSR4_10 F_(SCL1, IP10_31_28) 150 #define GPSR4_9 FM(SDA0) 151 #define GPSR4_8 FM(SCL0) 152 #define GPSR4_7 F_(SSI_WS4_A, IP10_27_24) 153 #define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20) 154 #define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16) 155 #define GPSR4_4 F_(SSI_WS34, IP10_15_12) 156 #define GPSR4_3 F_(SSI_SDATA3, IP10_11_8) 157 #define GPSR4_2 F_(SSI_SCK34, IP10_7_4) 158 #define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0) 159 #define GPSR4_0 F_(NFRB_N, IP8_23_20) 160 161 /* GPSR5 */ 162 #define GPSR5_20 FM(AVB0_LINK) 163 #define GPSR5_19 FM(AVB0_PHY_INT) 164 #define GPSR5_18 FM(AVB0_MAGIC) 165 #define GPSR5_17 FM(AVB0_MDC) 166 #define GPSR5_16 FM(AVB0_MDIO) 167 #define GPSR5_15 FM(AVB0_TXCREFCLK) 168 #define GPSR5_14 FM(AVB0_TD3) 169 #define GPSR5_13 FM(AVB0_TD2) 170 #define GPSR5_12 FM(AVB0_TD1) 171 #define GPSR5_11 FM(AVB0_TD0) 172 #define GPSR5_10 FM(AVB0_TXC) 173 #define GPSR5_9 FM(AVB0_TX_CTL) 174 #define GPSR5_8 FM(AVB0_RD3) 175 #define GPSR5_7 FM(AVB0_RD2) 176 #define GPSR5_6 FM(AVB0_RD1) 177 #define GPSR5_5 FM(AVB0_RD0) 178 #define GPSR5_4 FM(AVB0_RXC) 179 #define GPSR5_3 FM(AVB0_RX_CTL) 180 #define GPSR5_2 F_(CAN_CLK, IP12_23_20) 181 #define GPSR5_1 F_(TPU0TO1_A, IP12_19_16) 182 #define GPSR5_0 F_(TPU0TO0_A, IP12_15_12) 183 184 /* GPSR6 */ 185 #define GPSR6_13 FM(RPC_INT_N) 186 #define GPSR6_12 FM(RPC_RESET_N) 187 #define GPSR6_11 FM(QSPI1_SSL) 188 #define GPSR6_10 FM(QSPI1_IO3) 189 #define GPSR6_9 FM(QSPI1_IO2) 190 #define GPSR6_8 FM(QSPI1_MISO_IO1) 191 #define GPSR6_7 FM(QSPI1_MOSI_IO0) 192 #define GPSR6_6 FM(QSPI1_SPCLK) 193 #define GPSR6_5 FM(QSPI0_SSL) 194 #define GPSR6_4 FM(QSPI0_IO3) 195 #define GPSR6_3 FM(QSPI0_IO2) 196 #define GPSR6_2 FM(QSPI0_MISO_IO1) 197 #define GPSR6_1 FM(QSPI0_MOSI_IO0) 198 #define GPSR6_0 FM(QSPI0_SPCLK) 199 200 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 201 #define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 202 #define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 203 #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 204 #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205 #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 206 #define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 207 #define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 208 #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 209 #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 210 #define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211 #define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212 #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213 #define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214 #define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 #define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225 #define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226 #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227 #define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228 #define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229 #define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230 #define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 231 #define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 232 #define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233 234 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 235 #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236 #define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237 #define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238 #define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239 #define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240 #define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241 #define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242 #define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243 #define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244 #define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245 #define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246 #define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 247 #define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248 #define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249 #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250 #define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251 #define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252 #define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253 #define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254 #define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255 #define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 268 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 269 #define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 #define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 #define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 302 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 303 #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 314 #define PINMUX_GPSR \ 315 \ 316 GPSR1_31 GPSR2_31 GPSR4_31 \ 317 GPSR1_30 GPSR2_30 GPSR4_30 \ 318 GPSR1_29 GPSR2_29 GPSR4_29 \ 319 GPSR1_28 GPSR2_28 GPSR4_28 \ 320 GPSR1_27 GPSR2_27 GPSR4_27 \ 321 GPSR1_26 GPSR2_26 GPSR4_26 \ 322 GPSR1_25 GPSR2_25 GPSR4_25 \ 323 GPSR1_24 GPSR2_24 GPSR4_24 \ 324 GPSR1_23 GPSR2_23 GPSR4_23 \ 325 GPSR1_22 GPSR2_22 GPSR4_22 \ 326 GPSR1_21 GPSR2_21 GPSR4_21 \ 327 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \ 328 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \ 329 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \ 330 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \ 331 GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \ 332 GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \ 333 GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \ 334 GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 335 GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 336 GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 337 GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 338 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 339 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 340 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 341 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 342 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 343 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 344 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ 345 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ 346 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ 347 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 348 349 #define PINMUX_IPSR \ 350 \ 351 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 352 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 353 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 354 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 355 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 356 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 357 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 358 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 359 \ 360 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 361 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 362 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 363 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 364 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 365 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 366 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 367 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 368 \ 369 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 370 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 371 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 372 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 373 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 374 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 375 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 376 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 377 \ 378 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \ 379 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \ 380 FM(IP12_11_8) IP12_11_8 \ 381 FM(IP12_15_12) IP12_15_12 \ 382 FM(IP12_19_16) IP12_19_16 \ 383 FM(IP12_23_20) IP12_23_20 \ 384 FM(IP12_27_24) IP12_27_24 \ 385 FM(IP12_31_28) IP12_31_28 \ 386 387 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 388 #define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) 389 #define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1) 390 #define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 391 #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) 392 #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) 393 #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) 394 #define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3) 395 #define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3) 396 #define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3) 397 #define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3) 398 #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1) 399 #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1) 400 #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1) 401 #define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1) 402 #define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1) 403 #define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1) 404 #define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1) 405 #define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1) 406 #define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 407 #define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 408 #define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1) 409 #define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1) 410 411 #define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1) 412 #define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1) 413 #define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 414 #define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 415 #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) 416 #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1) 417 418 419 #define PINMUX_MOD_SELS \ 420 \ 421 MOD_SEL1_31 \ 422 MOD_SEL0_30 MOD_SEL1_30 \ 423 MOD_SEL0_29 MOD_SEL1_29 \ 424 MOD_SEL0_28 MOD_SEL1_28 \ 425 MOD_SEL0_27 MOD_SEL1_27 \ 426 MOD_SEL0_26 MOD_SEL1_26 \ 427 MOD_SEL0_25 \ 428 MOD_SEL0_24_23 \ 429 MOD_SEL0_22_21 \ 430 MOD_SEL0_20_19 \ 431 MOD_SEL0_18_17 \ 432 MOD_SEL0_15 \ 433 MOD_SEL0_14 \ 434 MOD_SEL0_13 \ 435 MOD_SEL0_12 \ 436 MOD_SEL0_11 \ 437 MOD_SEL0_10 \ 438 MOD_SEL0_5 \ 439 MOD_SEL0_4 \ 440 MOD_SEL0_3 \ 441 MOD_SEL0_2 \ 442 MOD_SEL0_1 \ 443 MOD_SEL0_0 444 445 enum { 446 PINMUX_RESERVED = 0, 447 448 PINMUX_DATA_BEGIN, 449 GP_ALL(DATA), 450 PINMUX_DATA_END, 451 452 #define F_(x, y) 453 #define FM(x) FN_##x, 454 PINMUX_FUNCTION_BEGIN, 455 GP_ALL(FN), 456 PINMUX_GPSR 457 PINMUX_IPSR 458 PINMUX_MOD_SELS 459 PINMUX_FUNCTION_END, 460 #undef F_ 461 #undef FM 462 463 #define F_(x, y) 464 #define FM(x) x##_MARK, 465 PINMUX_MARK_BEGIN, 466 PINMUX_GPSR 467 PINMUX_IPSR 468 PINMUX_MOD_SELS 469 PINMUX_MARK_END, 470 #undef F_ 471 #undef FM 472 }; 473 474 #define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \ 475 PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr) 476 477 #define PINMUX_IPSR_PHYS(ipsr, fn, msel) \ 478 PINMUX_DATA(fn##_MARK, FN_##msel) 479 480 static const u16 pinmux_data[] = { 481 PINMUX_DATA_GP_ALL(), 482 483 PINMUX_SINGLE(USB0_OVC), 484 PINMUX_SINGLE(USB0_PWEN), 485 PINMUX_SINGLE(VI4_DATA4), 486 PINMUX_SINGLE(VI4_CLK), 487 PINMUX_SINGLE(TX2), 488 PINMUX_SINGLE(RX2), 489 PINMUX_SINGLE(AVB0_LINK), 490 PINMUX_SINGLE(AVB0_PHY_INT), 491 PINMUX_SINGLE(AVB0_MAGIC), 492 PINMUX_SINGLE(AVB0_MDC), 493 PINMUX_SINGLE(AVB0_MDIO), 494 PINMUX_SINGLE(AVB0_TXCREFCLK), 495 PINMUX_SINGLE(AVB0_TD3), 496 PINMUX_SINGLE(AVB0_TD2), 497 PINMUX_SINGLE(AVB0_TD1), 498 PINMUX_SINGLE(AVB0_TD0), 499 PINMUX_SINGLE(AVB0_TXC), 500 PINMUX_SINGLE(AVB0_TX_CTL), 501 PINMUX_SINGLE(AVB0_RD3), 502 PINMUX_SINGLE(AVB0_RD2), 503 PINMUX_SINGLE(AVB0_RD1), 504 PINMUX_SINGLE(AVB0_RD0), 505 PINMUX_SINGLE(AVB0_RXC), 506 PINMUX_SINGLE(AVB0_RX_CTL), 507 PINMUX_SINGLE(RPC_INT_N), 508 PINMUX_SINGLE(RPC_RESET_N), 509 PINMUX_SINGLE(QSPI1_SSL), 510 PINMUX_SINGLE(QSPI1_IO3), 511 PINMUX_SINGLE(QSPI1_IO2), 512 PINMUX_SINGLE(QSPI1_MISO_IO1), 513 PINMUX_SINGLE(QSPI1_MOSI_IO0), 514 PINMUX_SINGLE(QSPI1_SPCLK), 515 PINMUX_SINGLE(QSPI0_SSL), 516 PINMUX_SINGLE(QSPI0_IO3), 517 PINMUX_SINGLE(QSPI0_IO2), 518 PINMUX_SINGLE(QSPI0_MISO_IO1), 519 PINMUX_SINGLE(QSPI0_MOSI_IO0), 520 PINMUX_SINGLE(QSPI0_SPCLK), 521 522 /* IPSR0 */ 523 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), 524 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 525 PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN), 526 527 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK), 528 PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU), 529 530 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD), 531 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0), 532 533 PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD), 534 PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0), 535 536 PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK), 537 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0), 538 PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0), 539 540 PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT), 541 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1), 542 PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0), 543 PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1), 544 545 PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG), 546 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2), 547 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0), 548 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1), 549 550 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0), 551 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0), 552 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1), 553 554 /* IPSR1 */ 555 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1), 556 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1), 557 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1), 558 559 PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2), 560 PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2), 561 PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1), 562 563 PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3), 564 PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3), 565 PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1), 566 567 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4), 568 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4), 569 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1), 570 571 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5), 572 PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5), 573 PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1), 574 575 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6), 576 PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6), 577 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1), 578 579 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7), 580 PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7), 581 PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1), 582 583 PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0), 584 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8), 585 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1), 586 587 /* IPSR2 */ 588 PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1), 589 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9), 590 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1), 591 592 PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2), 593 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10), 594 595 PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3), 596 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11), 597 PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0), 598 599 PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4), 600 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12), 601 PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1), 602 603 PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5), 604 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13), 605 PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1), 606 607 PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6), 608 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14), 609 PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1), 610 611 PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7), 612 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15), 613 PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1), 614 615 PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0), 616 PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16), 617 PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1), 618 619 /* IPSR3 */ 620 PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1), 621 PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17), 622 PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1), 623 624 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2), 625 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18), 626 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2), 627 628 PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3), 629 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19), 630 PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2), 631 632 PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4), 633 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20), 634 PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1), 635 636 PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5), 637 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21), 638 PINMUX_IPSR_GPSR(IP3_19_16, NMI), 639 640 PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6), 641 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22), 642 PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2), 643 644 PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7), 645 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23), 646 PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1), 647 648 PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0), 649 PINMUX_IPSR_GPSR(IP3_31_28, QCLK), 650 651 /* IPSR4 */ 652 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC), 653 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS), 654 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0), 655 656 PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC), 657 PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS), 658 PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0), 659 660 PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP), 661 PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE), 662 PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2), 663 664 PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE), 665 PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE), 666 PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1), 667 PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1), 668 669 PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE), 670 PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE), 671 PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1), 672 673 PINMUX_IPSR_GPSR(IP4_23_20, QPOLA), 674 PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1), 675 676 PINMUX_IPSR_GPSR(IP4_27_24, QPOLB), 677 PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1), 678 679 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0), 680 PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0), 681 682 /* IPSR5 */ 683 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1), 684 PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0), 685 686 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2), 687 PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0), 688 689 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3), 690 PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0), 691 692 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5), 693 PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0), 694 695 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6), 696 PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0), 697 698 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7), 699 PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0), 700 701 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8), 702 703 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9), 704 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0), 705 PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1), 706 707 /* IPSR6 */ 708 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10), 709 PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0), 710 711 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11), 712 PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0), 713 714 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12), 715 PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0), 716 717 PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13), 718 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0), 719 PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N), 720 721 PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14), 722 PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1), 723 PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N), 724 725 PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15), 726 PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1), 727 728 PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16), 729 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0), 730 731 PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17), 732 PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0), 733 734 /* IPSR7 */ 735 PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18), 736 PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0), 737 738 PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19), 739 PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1), 740 PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15), 741 742 PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20), 743 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0), 744 PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14), 745 746 PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21), 747 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0), 748 749 PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13), 750 PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22), 751 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0), 752 753 PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12), 754 PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23), 755 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), 756 757 PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11), 758 759 PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N), 760 PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1), 761 PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10), 762 763 PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N), 764 PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1), 765 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9), 766 767 /* IPSR8 */ 768 PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD), 769 PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB), 770 PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0), 771 PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK), 772 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8), 773 774 PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB), 775 PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1), 776 PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N), 777 PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0), 778 779 PINMUX_IPSR_GPSR(IP8_11_8, NFALE), 780 PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1), 781 PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1), 782 PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1), 783 784 PINMUX_IPSR_GPSR(IP8_15_12, NFCLE), 785 PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1), 786 PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0), 787 PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1), 788 789 PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N), 790 PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0), 791 PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1), 792 793 PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N), 794 PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0), 795 PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1), 796 797 PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N), 798 PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD), 799 800 PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N), 801 PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK), 802 803 /* IPSR9 */ 804 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0), 805 PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0), 806 807 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1), 808 PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1), 809 810 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2), 811 PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2), 812 813 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3), 814 PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3), 815 816 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4), 817 PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4), 818 819 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5), 820 PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5), 821 822 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6), 823 PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6), 824 825 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7), 826 PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7), 827 828 /* IPSR10 */ 829 PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA), 830 PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1), 831 832 PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34), 833 PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0), 834 835 PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3), 836 PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0), 837 838 PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34), 839 PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0), 840 841 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0), 842 PINMUX_IPSR_GPSR(IP10_19_16, HSCK0), 843 PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT), 844 PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1), 845 PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1), 846 847 PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0), 848 PINMUX_IPSR_GPSR(IP10_23_20, HTX0), 849 PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0), 850 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1), 851 852 PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0), 853 PINMUX_IPSR_GPSR(IP10_27_24, HRX0), 854 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), 855 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1), 856 857 PINMUX_IPSR_GPSR(IP10_31_28, SCL1), 858 PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N), 859 860 /* IPSR11 */ 861 PINMUX_IPSR_GPSR(IP11_3_0, SDA1), 862 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS), 863 864 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), 865 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), 866 867 PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD), 868 PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 869 870 PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD), 871 PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1), 872 873 PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0), 874 PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC), 875 PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1), 876 877 PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0), 878 PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1), 879 PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1), 880 881 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0), 882 PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2), 883 PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1), 884 885 PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0), 886 PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2), 887 PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B), 888 PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1), 889 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1), 890 891 /* IPSR12 */ 892 PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0), 893 PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N), 894 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), 895 896 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), 897 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS), 898 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), 899 900 PINMUX_IPSR_GPSR(IP12_11_8, SCK2), 901 PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1), 902 PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B), 903 904 PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A), 905 PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0), 906 PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N), 907 908 PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A), 909 PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0), 910 PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N), 911 912 PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK), 913 PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0), 914 PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1), 915 PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1), 916 917 PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0), 918 PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX), 919 PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1), 920 921 PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0), 922 PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX), 923 PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1), 924 925 /* IPSR13 */ 926 PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0), 927 PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX), 928 PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A), 929 930 PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0), 931 PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX), 932 PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A), 933 }; 934 935 static const struct sh_pfc_pin pinmux_pins[] = { 936 PINMUX_GPIO_GP_ALL(), 937 }; 938 939 /* - I2C -------------------------------------------------------------------- */ 940 static const unsigned int i2c0_pins[] = { 941 /* SCL, SDA */ 942 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 943 }; 944 static const unsigned int i2c0_mux[] = { 945 SCL0_MARK, SDA0_MARK, 946 }; 947 static const unsigned int i2c1_pins[] = { 948 /* SCL, SDA */ 949 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 950 }; 951 static const unsigned int i2c1_mux[] = { 952 SCL1_MARK, SDA1_MARK, 953 }; 954 static const unsigned int i2c2_a_pins[] = { 955 /* SCL, SDA */ 956 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 957 }; 958 static const unsigned int i2c2_a_mux[] = { 959 SCL2_A_MARK, SDA2_A_MARK, 960 }; 961 static const unsigned int i2c2_b_pins[] = { 962 /* SCL, SDA */ 963 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30), 964 }; 965 static const unsigned int i2c2_b_mux[] = { 966 SCL2_B_MARK, SDA2_B_MARK, 967 }; 968 static const unsigned int i2c3_a_pins[] = { 969 /* SCL, SDA */ 970 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 971 }; 972 static const unsigned int i2c3_a_mux[] = { 973 SCL3_A_MARK, SDA3_A_MARK, 974 }; 975 static const unsigned int i2c3_b_pins[] = { 976 /* SCL, SDA */ 977 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), 978 }; 979 static const unsigned int i2c3_b_mux[] = { 980 SCL3_B_MARK, SDA3_B_MARK, 981 }; 982 983 /* - MMC ------------------------------------------------------------------- */ 984 static const unsigned int mmc_data1_pins[] = { 985 /* D0 */ 986 RCAR_GP_PIN(3, 2), 987 }; 988 static const unsigned int mmc_data1_mux[] = { 989 MMC_D0_MARK, 990 }; 991 static const unsigned int mmc_data4_pins[] = { 992 /* D[0:3] */ 993 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 994 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 995 }; 996 static const unsigned int mmc_data4_mux[] = { 997 MMC_D0_MARK, MMC_D1_MARK, 998 MMC_D2_MARK, MMC_D3_MARK, 999 }; 1000 static const unsigned int mmc_data8_pins[] = { 1001 /* D[0:7] */ 1002 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 1003 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 1004 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1005 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1006 }; 1007 static const unsigned int mmc_data8_mux[] = { 1008 MMC_D0_MARK, MMC_D1_MARK, 1009 MMC_D2_MARK, MMC_D3_MARK, 1010 MMC_D4_MARK, MMC_D5_MARK, 1011 MMC_D6_MARK, MMC_D7_MARK, 1012 }; 1013 static const unsigned int mmc_ctrl_pins[] = { 1014 /* CLK, CMD */ 1015 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 1016 }; 1017 static const unsigned int mmc_ctrl_mux[] = { 1018 MMC_CLK_MARK, MMC_CMD_MARK, 1019 }; 1020 1021 /* - SCIF0 ------------------------------------------------------------------ */ 1022 static const unsigned int scif0_data_a_pins[] = { 1023 /* RX, TX */ 1024 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 1025 }; 1026 static const unsigned int scif0_data_a_mux[] = { 1027 RX0_A_MARK, TX0_A_MARK, 1028 }; 1029 static const unsigned int scif0_clk_a_pins[] = { 1030 /* SCK */ 1031 RCAR_GP_PIN(4, 19), 1032 }; 1033 static const unsigned int scif0_clk_a_mux[] = { 1034 SCK0_A_MARK, 1035 }; 1036 static const unsigned int scif0_data_b_pins[] = { 1037 /* RX, TX */ 1038 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28), 1039 }; 1040 static const unsigned int scif0_data_b_mux[] = { 1041 RX0_B_MARK, TX0_B_MARK, 1042 }; 1043 static const unsigned int scif0_clk_b_pins[] = { 1044 /* SCK */ 1045 RCAR_GP_PIN(5, 2), 1046 }; 1047 static const unsigned int scif0_clk_b_mux[] = { 1048 SCK0_B_MARK, 1049 }; 1050 static const unsigned int scif0_ctrl_pins[] = { 1051 /* RTS, CTS */ 1052 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), 1053 }; 1054 static const unsigned int scif0_ctrl_mux[] = { 1055 RTS0_N_TANS_MARK, CTS0_N_MARK, 1056 }; 1057 /* - SCIF1 ------------------------------------------------------------------ */ 1058 static const unsigned int scif1_data_a_pins[] = { 1059 /* RX, TX */ 1060 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 1061 }; 1062 static const unsigned int scif1_data_a_mux[] = { 1063 RX1_A_MARK, TX1_A_MARK, 1064 }; 1065 static const unsigned int scif1_clk_a_pins[] = { 1066 /* SCK */ 1067 RCAR_GP_PIN(4, 22), 1068 }; 1069 static const unsigned int scif1_clk_a_mux[] = { 1070 SCK1_A_MARK, 1071 }; 1072 static const unsigned int scif1_data_b_pins[] = { 1073 /* RX, TX */ 1074 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28), 1075 }; 1076 static const unsigned int scif1_data_b_mux[] = { 1077 RX1_B_MARK, TX1_B_MARK, 1078 }; 1079 static const unsigned int scif1_clk_b_pins[] = { 1080 /* SCK */ 1081 RCAR_GP_PIN(2, 25), 1082 }; 1083 static const unsigned int scif1_clk_b_mux[] = { 1084 SCK1_B_MARK, 1085 }; 1086 static const unsigned int scif1_ctrl_pins[] = { 1087 /* RTS, CTS */ 1088 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), 1089 }; 1090 static const unsigned int scif1_ctrl_mux[] = { 1091 RTS1_N_TANS_MARK, CTS1_N_MARK, 1092 }; 1093 1094 /* - SCIF2 ------------------------------------------------------------------ */ 1095 static const unsigned int scif2_data_pins[] = { 1096 /* RX, TX */ 1097 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), 1098 }; 1099 static const unsigned int scif2_data_mux[] = { 1100 RX2_MARK, TX2_MARK, 1101 }; 1102 static const unsigned int scif2_clk_pins[] = { 1103 /* SCK */ 1104 RCAR_GP_PIN(4, 25), 1105 }; 1106 static const unsigned int scif2_clk_mux[] = { 1107 SCK2_MARK, 1108 }; 1109 /* - SCIF3 ------------------------------------------------------------------ */ 1110 static const unsigned int scif3_data_a_pins[] = { 1111 /* RX, TX */ 1112 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00), 1113 }; 1114 static const unsigned int scif3_data_a_mux[] = { 1115 RX3_A_MARK, TX3_A_MARK, 1116 }; 1117 static const unsigned int scif3_clk_a_pins[] = { 1118 /* SCK */ 1119 RCAR_GP_PIN(2, 30), 1120 }; 1121 static const unsigned int scif3_clk_a_mux[] = { 1122 SCK3_A_MARK, 1123 }; 1124 static const unsigned int scif3_data_b_pins[] = { 1125 /* RX, TX */ 1126 RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31), 1127 }; 1128 static const unsigned int scif3_data_b_mux[] = { 1129 RX3_B_MARK, TX3_B_MARK, 1130 }; 1131 static const unsigned int scif3_clk_b_pins[] = { 1132 /* SCK */ 1133 RCAR_GP_PIN(1, 29), 1134 }; 1135 static const unsigned int scif3_clk_b_mux[] = { 1136 SCK3_B_MARK, 1137 }; 1138 /* - SCIF4 ------------------------------------------------------------------ */ 1139 static const unsigned int scif4_data_a_pins[] = { 1140 /* RX, TX */ 1141 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 1142 }; 1143 static const unsigned int scif4_data_a_mux[] = { 1144 RX4_A_MARK, TX4_A_MARK, 1145 }; 1146 static const unsigned int scif4_clk_a_pins[] = { 1147 /* SCK */ 1148 RCAR_GP_PIN(2, 6), 1149 }; 1150 static const unsigned int scif4_clk_a_mux[] = { 1151 SCK4_A_MARK, 1152 }; 1153 static const unsigned int scif4_data_b_pins[] = { 1154 /* RX, TX */ 1155 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 1156 }; 1157 static const unsigned int scif4_data_b_mux[] = { 1158 RX4_B_MARK, TX4_B_MARK, 1159 }; 1160 static const unsigned int scif4_clk_b_pins[] = { 1161 /* SCK */ 1162 RCAR_GP_PIN(1, 15), 1163 }; 1164 static const unsigned int scif4_clk_b_mux[] = { 1165 SCK4_B_MARK, 1166 }; 1167 /* - SCIF5 ------------------------------------------------------------------ */ 1168 static const unsigned int scif5_data_a_pins[] = { 1169 /* RX, TX */ 1170 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), 1171 }; 1172 static const unsigned int scif5_data_a_mux[] = { 1173 RX5_A_MARK, TX5_A_MARK, 1174 }; 1175 static const unsigned int scif5_clk_a_pins[] = { 1176 /* SCK */ 1177 RCAR_GP_PIN(0, 6), 1178 }; 1179 static const unsigned int scif5_clk_a_mux[] = { 1180 SCK5_A_MARK, 1181 }; 1182 static const unsigned int scif5_data_b_pins[] = { 1183 /* RX, TX */ 1184 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 1185 }; 1186 static const unsigned int scif5_data_b_mux[] = { 1187 RX5_B_MARK, TX5_B_MARK, 1188 }; 1189 static const unsigned int scif5_clk_b_pins[] = { 1190 /* SCK */ 1191 RCAR_GP_PIN(1, 3), 1192 }; 1193 static const unsigned int scif5_clk_b_mux[] = { 1194 SCK5_B_MARK, 1195 }; 1196 /* - SCIF Clock ------------------------------------------------------------- */ 1197 static const unsigned int scif_clk_pins[] = { 1198 /* SCIF_CLK */ 1199 RCAR_GP_PIN(2, 27), 1200 }; 1201 static const unsigned int scif_clk_mux[] = { 1202 SCIF_CLK_MARK, 1203 }; 1204 1205 static const struct sh_pfc_pin_group pinmux_groups[] = { 1206 SH_PFC_PIN_GROUP(i2c0), 1207 SH_PFC_PIN_GROUP(i2c1), 1208 SH_PFC_PIN_GROUP(i2c2_a), 1209 SH_PFC_PIN_GROUP(i2c2_b), 1210 SH_PFC_PIN_GROUP(i2c3_a), 1211 SH_PFC_PIN_GROUP(i2c3_b), 1212 SH_PFC_PIN_GROUP(mmc_data1), 1213 SH_PFC_PIN_GROUP(mmc_data4), 1214 SH_PFC_PIN_GROUP(mmc_data8), 1215 SH_PFC_PIN_GROUP(mmc_ctrl), 1216 SH_PFC_PIN_GROUP(scif0_data_a), 1217 SH_PFC_PIN_GROUP(scif0_clk_a), 1218 SH_PFC_PIN_GROUP(scif0_data_b), 1219 SH_PFC_PIN_GROUP(scif0_clk_b), 1220 SH_PFC_PIN_GROUP(scif0_ctrl), 1221 SH_PFC_PIN_GROUP(scif1_data_a), 1222 SH_PFC_PIN_GROUP(scif1_clk_a), 1223 SH_PFC_PIN_GROUP(scif1_data_b), 1224 SH_PFC_PIN_GROUP(scif1_clk_b), 1225 SH_PFC_PIN_GROUP(scif1_ctrl), 1226 SH_PFC_PIN_GROUP(scif2_data), 1227 SH_PFC_PIN_GROUP(scif2_clk), 1228 SH_PFC_PIN_GROUP(scif3_data_a), 1229 SH_PFC_PIN_GROUP(scif3_clk_a), 1230 SH_PFC_PIN_GROUP(scif3_data_b), 1231 SH_PFC_PIN_GROUP(scif3_clk_b), 1232 SH_PFC_PIN_GROUP(scif4_data_a), 1233 SH_PFC_PIN_GROUP(scif4_clk_a), 1234 SH_PFC_PIN_GROUP(scif4_data_b), 1235 SH_PFC_PIN_GROUP(scif4_clk_b), 1236 SH_PFC_PIN_GROUP(scif5_data_a), 1237 SH_PFC_PIN_GROUP(scif5_clk_a), 1238 SH_PFC_PIN_GROUP(scif5_data_b), 1239 SH_PFC_PIN_GROUP(scif5_clk_b), 1240 SH_PFC_PIN_GROUP(scif_clk), 1241 }; 1242 1243 static const char * const i2c0_groups[] = { 1244 "i2c0", 1245 }; 1246 static const char * const i2c1_groups[] = { 1247 "i2c1", 1248 }; 1249 1250 static const char * const i2c2_groups[] = { 1251 "i2c2_a", 1252 "i2c2_b", 1253 }; 1254 1255 static const char * const i2c3_groups[] = { 1256 "i2c3_a", 1257 "i2c3_b", 1258 }; 1259 1260 static const char * const mmc_groups[] = { 1261 "mmc_data1", 1262 "mmc_data4", 1263 "mmc_data8", 1264 "mmc_ctrl", 1265 }; 1266 1267 static const char * const scif0_groups[] = { 1268 "scif0_data_a", 1269 "scif0_clk_a", 1270 "scif0_data_b", 1271 "scif0_clk_b", 1272 "scif0_ctrl", 1273 }; 1274 1275 static const char * const scif1_groups[] = { 1276 "scif1_data_a", 1277 "scif1_clk_a", 1278 "scif1_data_b", 1279 "scif1_clk_b", 1280 "scif1_ctrl", 1281 }; 1282 1283 static const char * const scif2_groups[] = { 1284 "scif2_data", 1285 "scif2_clk", 1286 }; 1287 1288 static const char * const scif3_groups[] = { 1289 "scif3_data_a", 1290 "scif3_clk_a", 1291 "scif3_data_b", 1292 "scif3_clk_b", 1293 }; 1294 1295 static const char * const scif4_groups[] = { 1296 "scif4_data_a", 1297 "scif4_clk_a", 1298 "scif4_data_b", 1299 "scif4_clk_b", 1300 }; 1301 1302 static const char * const scif5_groups[] = { 1303 "scif5_data_a", 1304 "scif5_clk_a", 1305 "scif5_data_b", 1306 "scif5_clk_b", 1307 }; 1308 1309 static const char * const scif_clk_groups[] = { 1310 "scif_clk", 1311 }; 1312 1313 static const struct sh_pfc_function pinmux_functions[] = { 1314 SH_PFC_FUNCTION(i2c0), 1315 SH_PFC_FUNCTION(i2c1), 1316 SH_PFC_FUNCTION(i2c2), 1317 SH_PFC_FUNCTION(i2c3), 1318 SH_PFC_FUNCTION(mmc), 1319 SH_PFC_FUNCTION(scif0), 1320 SH_PFC_FUNCTION(scif1), 1321 SH_PFC_FUNCTION(scif2), 1322 SH_PFC_FUNCTION(scif3), 1323 SH_PFC_FUNCTION(scif4), 1324 SH_PFC_FUNCTION(scif5), 1325 SH_PFC_FUNCTION(scif_clk), 1326 }; 1327 1328 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1329 #define F_(x, y) FN_##y 1330 #define FM(x) FN_##x 1331 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 1332 0, 0, 1333 0, 0, 1334 0, 0, 1335 0, 0, 1336 0, 0, 1337 0, 0, 1338 0, 0, 1339 0, 0, 1340 0, 0, 1341 0, 0, 1342 0, 0, 1343 0, 0, 1344 0, 0, 1345 0, 0, 1346 0, 0, 1347 0, 0, 1348 0, 0, 1349 0, 0, 1350 0, 0, 1351 0, 0, 1352 0, 0, 1353 0, 0, 1354 0, 0, 1355 GP_0_8_FN, GPSR0_8, 1356 GP_0_7_FN, GPSR0_7, 1357 GP_0_6_FN, GPSR0_6, 1358 GP_0_5_FN, GPSR0_5, 1359 GP_0_4_FN, GPSR0_4, 1360 GP_0_3_FN, GPSR0_3, 1361 GP_0_2_FN, GPSR0_2, 1362 GP_0_1_FN, GPSR0_1, 1363 GP_0_0_FN, GPSR0_0, } 1364 }, 1365 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 1366 GP_1_31_FN, GPSR1_31, 1367 GP_1_30_FN, GPSR1_30, 1368 GP_1_29_FN, GPSR1_29, 1369 GP_1_28_FN, GPSR1_28, 1370 GP_1_27_FN, GPSR1_27, 1371 GP_1_26_FN, GPSR1_26, 1372 GP_1_25_FN, GPSR1_25, 1373 GP_1_24_FN, GPSR1_24, 1374 GP_1_23_FN, GPSR1_23, 1375 GP_1_22_FN, GPSR1_22, 1376 GP_1_21_FN, GPSR1_21, 1377 GP_1_20_FN, GPSR1_20, 1378 GP_1_19_FN, GPSR1_19, 1379 GP_1_18_FN, GPSR1_18, 1380 GP_1_17_FN, GPSR1_17, 1381 GP_1_16_FN, GPSR1_16, 1382 GP_1_15_FN, GPSR1_15, 1383 GP_1_14_FN, GPSR1_14, 1384 GP_1_13_FN, GPSR1_13, 1385 GP_1_12_FN, GPSR1_12, 1386 GP_1_11_FN, GPSR1_11, 1387 GP_1_10_FN, GPSR1_10, 1388 GP_1_9_FN, GPSR1_9, 1389 GP_1_8_FN, GPSR1_8, 1390 GP_1_7_FN, GPSR1_7, 1391 GP_1_6_FN, GPSR1_6, 1392 GP_1_5_FN, GPSR1_5, 1393 GP_1_4_FN, GPSR1_4, 1394 GP_1_3_FN, GPSR1_3, 1395 GP_1_2_FN, GPSR1_2, 1396 GP_1_1_FN, GPSR1_1, 1397 GP_1_0_FN, GPSR1_0, } 1398 }, 1399 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 1400 GP_2_31_FN, GPSR2_31, 1401 GP_2_30_FN, GPSR2_30, 1402 GP_2_29_FN, GPSR2_29, 1403 GP_2_28_FN, GPSR2_28, 1404 GP_2_27_FN, GPSR2_27, 1405 GP_2_26_FN, GPSR2_26, 1406 GP_2_25_FN, GPSR2_25, 1407 GP_2_24_FN, GPSR2_24, 1408 GP_2_23_FN, GPSR2_23, 1409 GP_2_22_FN, GPSR2_22, 1410 GP_2_21_FN, GPSR2_21, 1411 GP_2_20_FN, GPSR2_20, 1412 GP_2_19_FN, GPSR2_19, 1413 GP_2_18_FN, GPSR2_18, 1414 GP_2_17_FN, GPSR2_17, 1415 GP_2_16_FN, GPSR2_16, 1416 GP_2_15_FN, GPSR2_15, 1417 GP_2_14_FN, GPSR2_14, 1418 GP_2_13_FN, GPSR2_13, 1419 GP_2_12_FN, GPSR2_12, 1420 GP_2_11_FN, GPSR2_11, 1421 GP_2_10_FN, GPSR2_10, 1422 GP_2_9_FN, GPSR2_9, 1423 GP_2_8_FN, GPSR2_8, 1424 GP_2_7_FN, GPSR2_7, 1425 GP_2_6_FN, GPSR2_6, 1426 GP_2_5_FN, GPSR2_5, 1427 GP_2_4_FN, GPSR2_4, 1428 GP_2_3_FN, GPSR2_3, 1429 GP_2_2_FN, GPSR2_2, 1430 GP_2_1_FN, GPSR2_1, 1431 GP_2_0_FN, GPSR2_0, } 1432 }, 1433 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 1434 0, 0, 1435 0, 0, 1436 0, 0, 1437 0, 0, 1438 0, 0, 1439 0, 0, 1440 0, 0, 1441 0, 0, 1442 0, 0, 1443 0, 0, 1444 0, 0, 1445 0, 0, 1446 0, 0, 1447 0, 0, 1448 0, 0, 1449 0, 0, 1450 0, 0, 1451 0, 0, 1452 0, 0, 1453 0, 0, 1454 0, 0, 1455 0, 0, 1456 GP_3_9_FN, GPSR3_9, 1457 GP_3_8_FN, GPSR3_8, 1458 GP_3_7_FN, GPSR3_7, 1459 GP_3_6_FN, GPSR3_6, 1460 GP_3_5_FN, GPSR3_5, 1461 GP_3_4_FN, GPSR3_4, 1462 GP_3_3_FN, GPSR3_3, 1463 GP_3_2_FN, GPSR3_2, 1464 GP_3_1_FN, GPSR3_1, 1465 GP_3_0_FN, GPSR3_0, } 1466 }, 1467 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 1468 GP_4_31_FN, GPSR4_31, 1469 GP_4_30_FN, GPSR4_30, 1470 GP_4_29_FN, GPSR4_29, 1471 GP_4_28_FN, GPSR4_28, 1472 GP_4_27_FN, GPSR4_27, 1473 GP_4_26_FN, GPSR4_26, 1474 GP_4_25_FN, GPSR4_25, 1475 GP_4_24_FN, GPSR4_24, 1476 GP_4_23_FN, GPSR4_23, 1477 GP_4_22_FN, GPSR4_22, 1478 GP_4_21_FN, GPSR4_21, 1479 GP_4_20_FN, GPSR4_20, 1480 GP_4_19_FN, GPSR4_19, 1481 GP_4_18_FN, GPSR4_18, 1482 GP_4_17_FN, GPSR4_17, 1483 GP_4_16_FN, GPSR4_16, 1484 GP_4_15_FN, GPSR4_15, 1485 GP_4_14_FN, GPSR4_14, 1486 GP_4_13_FN, GPSR4_13, 1487 GP_4_12_FN, GPSR4_12, 1488 GP_4_11_FN, GPSR4_11, 1489 GP_4_10_FN, GPSR4_10, 1490 GP_4_9_FN, GPSR4_9, 1491 GP_4_8_FN, GPSR4_8, 1492 GP_4_7_FN, GPSR4_7, 1493 GP_4_6_FN, GPSR4_6, 1494 GP_4_5_FN, GPSR4_5, 1495 GP_4_4_FN, GPSR4_4, 1496 GP_4_3_FN, GPSR4_3, 1497 GP_4_2_FN, GPSR4_2, 1498 GP_4_1_FN, GPSR4_1, 1499 GP_4_0_FN, GPSR4_0, } 1500 }, 1501 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 1502 0, 0, 1503 0, 0, 1504 0, 0, 1505 0, 0, 1506 0, 0, 1507 0, 0, 1508 0, 0, 1509 0, 0, 1510 0, 0, 1511 0, 0, 1512 0, 0, 1513 GP_5_20_FN, GPSR5_20, 1514 GP_5_19_FN, GPSR5_19, 1515 GP_5_18_FN, GPSR5_18, 1516 GP_5_17_FN, GPSR5_17, 1517 GP_5_16_FN, GPSR5_16, 1518 GP_5_15_FN, GPSR5_15, 1519 GP_5_14_FN, GPSR5_14, 1520 GP_5_13_FN, GPSR5_13, 1521 GP_5_12_FN, GPSR5_12, 1522 GP_5_11_FN, GPSR5_11, 1523 GP_5_10_FN, GPSR5_10, 1524 GP_5_9_FN, GPSR5_9, 1525 GP_5_8_FN, GPSR5_8, 1526 GP_5_7_FN, GPSR5_7, 1527 GP_5_6_FN, GPSR5_6, 1528 GP_5_5_FN, GPSR5_5, 1529 GP_5_4_FN, GPSR5_4, 1530 GP_5_3_FN, GPSR5_3, 1531 GP_5_2_FN, GPSR5_2, 1532 GP_5_1_FN, GPSR5_1, 1533 GP_5_0_FN, GPSR5_0, } 1534 }, 1535 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { 1536 0, 0, 1537 0, 0, 1538 0, 0, 1539 0, 0, 1540 0, 0, 1541 0, 0, 1542 0, 0, 1543 0, 0, 1544 0, 0, 1545 0, 0, 1546 0, 0, 1547 0, 0, 1548 0, 0, 1549 0, 0, 1550 0, 0, 1551 0, 0, 1552 0, 0, 1553 0, 0, 1554 GP_6_13_FN, GPSR6_13, 1555 GP_6_12_FN, GPSR6_12, 1556 GP_6_11_FN, GPSR6_11, 1557 GP_6_10_FN, GPSR6_10, 1558 GP_6_9_FN, GPSR6_9, 1559 GP_6_8_FN, GPSR6_8, 1560 GP_6_7_FN, GPSR6_7, 1561 GP_6_6_FN, GPSR6_6, 1562 GP_6_5_FN, GPSR6_5, 1563 GP_6_4_FN, GPSR6_4, 1564 GP_6_3_FN, GPSR6_3, 1565 GP_6_2_FN, GPSR6_2, 1566 GP_6_1_FN, GPSR6_1, 1567 GP_6_0_FN, GPSR6_0, } 1568 }, 1569 #undef F_ 1570 #undef FM 1571 1572 #define F_(x, y) x, 1573 #define FM(x) FN_##x, 1574 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 1575 IP0_31_28 1576 IP0_27_24 1577 IP0_23_20 1578 IP0_19_16 1579 IP0_15_12 1580 IP0_11_8 1581 IP0_7_4 1582 IP0_3_0 } 1583 }, 1584 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 1585 IP1_31_28 1586 IP1_27_24 1587 IP1_23_20 1588 IP1_19_16 1589 IP1_15_12 1590 IP1_11_8 1591 IP1_7_4 1592 IP1_3_0 } 1593 }, 1594 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 1595 IP2_31_28 1596 IP2_27_24 1597 IP2_23_20 1598 IP2_19_16 1599 IP2_15_12 1600 IP2_11_8 1601 IP2_7_4 1602 IP2_3_0 } 1603 }, 1604 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 1605 IP3_31_28 1606 IP3_27_24 1607 IP3_23_20 1608 IP3_19_16 1609 IP3_15_12 1610 IP3_11_8 1611 IP3_7_4 1612 IP3_3_0 } 1613 }, 1614 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 1615 IP4_31_28 1616 IP4_27_24 1617 IP4_23_20 1618 IP4_19_16 1619 IP4_15_12 1620 IP4_11_8 1621 IP4_7_4 1622 IP4_3_0 } 1623 }, 1624 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 1625 IP5_31_28 1626 IP5_27_24 1627 IP5_23_20 1628 IP5_19_16 1629 IP5_15_12 1630 IP5_11_8 1631 IP5_7_4 1632 IP5_3_0 } 1633 }, 1634 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 1635 IP6_31_28 1636 IP6_27_24 1637 IP6_23_20 1638 IP6_19_16 1639 IP6_15_12 1640 IP6_11_8 1641 IP6_7_4 1642 IP6_3_0 } 1643 }, 1644 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 1645 IP7_31_28 1646 IP7_27_24 1647 IP7_23_20 1648 IP7_19_16 1649 IP7_15_12 1650 IP7_11_8 1651 IP7_7_4 1652 IP7_3_0 } 1653 }, 1654 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 1655 IP8_31_28 1656 IP8_27_24 1657 IP8_23_20 1658 IP8_19_16 1659 IP8_15_12 1660 IP8_11_8 1661 IP8_7_4 1662 IP8_3_0 } 1663 }, 1664 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { 1665 IP9_31_28 1666 IP9_27_24 1667 IP9_23_20 1668 IP9_19_16 1669 IP9_15_12 1670 IP9_11_8 1671 IP9_7_4 1672 IP9_3_0 } 1673 }, 1674 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { 1675 IP10_31_28 1676 IP10_27_24 1677 IP10_23_20 1678 IP10_19_16 1679 IP10_15_12 1680 IP10_11_8 1681 IP10_7_4 1682 IP10_3_0 } 1683 }, 1684 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { 1685 IP11_31_28 1686 IP11_27_24 1687 IP11_23_20 1688 IP11_19_16 1689 IP11_15_12 1690 IP11_11_8 1691 IP11_7_4 1692 IP11_3_0 } 1693 }, 1694 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { 1695 IP12_31_28 1696 IP12_27_24 1697 IP12_23_20 1698 IP12_19_16 1699 IP12_15_12 1700 IP12_11_8 1701 IP12_7_4 1702 IP12_3_0 } 1703 }, 1704 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { 1705 /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1706 /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1707 /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1708 /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1709 /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1710 /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1711 IP13_7_4 1712 IP13_3_0 } 1713 }, 1714 #undef F_ 1715 #undef FM 1716 1717 #define F_(x, y) x, 1718 #define FM(x) FN_##x, 1719 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 1720 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, 1721 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) { 1722 /* RESERVED 31 */ 1723 0, 0, 1724 MOD_SEL0_30 1725 MOD_SEL0_29 1726 MOD_SEL0_28 1727 MOD_SEL0_27 1728 MOD_SEL0_26 1729 MOD_SEL0_25 1730 MOD_SEL0_24_23 1731 MOD_SEL0_22_21 1732 MOD_SEL0_20_19 1733 MOD_SEL0_18_17 1734 /* RESERVED 16 */ 1735 0, 0, 1736 MOD_SEL0_15 1737 MOD_SEL0_14 1738 MOD_SEL0_13 1739 MOD_SEL0_12 1740 MOD_SEL0_11 1741 MOD_SEL0_10 1742 /* RESERVED 9, 8, 7, 6 */ 1743 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1744 MOD_SEL0_5 1745 MOD_SEL0_4 1746 MOD_SEL0_3 1747 MOD_SEL0_2 1748 MOD_SEL0_1 1749 MOD_SEL0_0 } 1750 }, 1751 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 1752 1, 1, 1, 1, 1, 1, 2, 4, 4, 1753 4, 4, 4, 4) { 1754 MOD_SEL1_31 1755 MOD_SEL1_30 1756 MOD_SEL1_29 1757 MOD_SEL1_28 1758 MOD_SEL1_27 1759 MOD_SEL1_26 1760 /* RESERVED 25, 24 */ 1761 0, 0, 0, 0, 1762 /* RESERVED 23, 22, 21, 20 */ 1763 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1764 /* RESERVED 19, 18, 17, 16 */ 1765 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1766 /* RESERVED 15, 14, 13, 12 */ 1767 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1768 /* RESERVED 11, 10, 9, 8 */ 1769 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1770 /* RESERVED 7, 6, 5, 4 */ 1771 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1772 /* RESERVED 3, 2, 1, 0 */ 1773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1774 }, 1775 { }, 1776 }; 1777 1778 static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 1779 { 1780 int bit = -EINVAL; 1781 1782 *pocctrl = 0xe6060380; 1783 1784 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9)) 1785 bit = 29 - (pin - RCAR_GP_PIN(3, 0)); 1786 1787 return bit; 1788 } 1789 1790 static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { 1791 .pin_to_pocctrl = r8a77995_pin_to_pocctrl, 1792 }; 1793 1794 const struct sh_pfc_soc_info r8a77995_pinmux_info = { 1795 .name = "r8a77995_pfc", 1796 .ops = &r8a77995_pinmux_ops, 1797 .unlock_reg = 0xe6060000, /* PMMR */ 1798 1799 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1800 1801 .pins = pinmux_pins, 1802 .nr_pins = ARRAY_SIZE(pinmux_pins), 1803 .groups = pinmux_groups, 1804 .nr_groups = ARRAY_SIZE(pinmux_groups), 1805 .functions = pinmux_functions, 1806 .nr_functions = ARRAY_SIZE(pinmux_functions), 1807 1808 .cfg_regs = pinmux_config_regs, 1809 1810 .pinmux_data = pinmux_data, 1811 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 1812 }; 1813