1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A7795 ES2.0+ processor support - PFC hardware block. 4 * 5 * Copyright (C) 2015-2016 Renesas Electronics Corporation 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <dm/pinctrl.h> 12 #include <linux/kernel.h> 13 14 #include "sh_pfc.h" 15 16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ 17 SH_PFC_PIN_CFG_PULL_UP | \ 18 SH_PFC_PIN_CFG_PULL_DOWN) 19 20 #define CPU_ALL_PORT(fn, sfx) \ 21 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 22 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 25 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 30 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 33 /* 34 * F_() : just information 35 * FM() : macro for FN_xxx / xxx_MARK 36 */ 37 38 /* GPSR0 */ 39 #define GPSR0_15 F_(D15, IP7_11_8) 40 #define GPSR0_14 F_(D14, IP7_7_4) 41 #define GPSR0_13 F_(D13, IP7_3_0) 42 #define GPSR0_12 F_(D12, IP6_31_28) 43 #define GPSR0_11 F_(D11, IP6_27_24) 44 #define GPSR0_10 F_(D10, IP6_23_20) 45 #define GPSR0_9 F_(D9, IP6_19_16) 46 #define GPSR0_8 F_(D8, IP6_15_12) 47 #define GPSR0_7 F_(D7, IP6_11_8) 48 #define GPSR0_6 F_(D6, IP6_7_4) 49 #define GPSR0_5 F_(D5, IP6_3_0) 50 #define GPSR0_4 F_(D4, IP5_31_28) 51 #define GPSR0_3 F_(D3, IP5_27_24) 52 #define GPSR0_2 F_(D2, IP5_23_20) 53 #define GPSR0_1 F_(D1, IP5_19_16) 54 #define GPSR0_0 F_(D0, IP5_15_12) 55 56 /* GPSR1 */ 57 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 58 #define GPSR1_26 F_(WE1_N, IP5_7_4) 59 #define GPSR1_25 F_(WE0_N, IP5_3_0) 60 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 61 #define GPSR1_23 F_(RD_N, IP4_27_24) 62 #define GPSR1_22 F_(BS_N, IP4_23_20) 63 #define GPSR1_21 F_(CS1_N, IP4_19_16) 64 #define GPSR1_20 F_(CS0_N, IP4_15_12) 65 #define GPSR1_19 F_(A19, IP4_11_8) 66 #define GPSR1_18 F_(A18, IP4_7_4) 67 #define GPSR1_17 F_(A17, IP4_3_0) 68 #define GPSR1_16 F_(A16, IP3_31_28) 69 #define GPSR1_15 F_(A15, IP3_27_24) 70 #define GPSR1_14 F_(A14, IP3_23_20) 71 #define GPSR1_13 F_(A13, IP3_19_16) 72 #define GPSR1_12 F_(A12, IP3_15_12) 73 #define GPSR1_11 F_(A11, IP3_11_8) 74 #define GPSR1_10 F_(A10, IP3_7_4) 75 #define GPSR1_9 F_(A9, IP3_3_0) 76 #define GPSR1_8 F_(A8, IP2_31_28) 77 #define GPSR1_7 F_(A7, IP2_27_24) 78 #define GPSR1_6 F_(A6, IP2_23_20) 79 #define GPSR1_5 F_(A5, IP2_19_16) 80 #define GPSR1_4 F_(A4, IP2_15_12) 81 #define GPSR1_3 F_(A3, IP2_11_8) 82 #define GPSR1_2 F_(A2, IP2_7_4) 83 #define GPSR1_1 F_(A1, IP2_3_0) 84 #define GPSR1_0 F_(A0, IP1_31_28) 85 86 /* GPSR2 */ 87 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 88 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 89 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 90 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 91 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 92 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 93 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 94 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 95 #define GPSR2_6 F_(PWM0, IP1_19_16) 96 #define GPSR2_5 F_(IRQ5, IP1_15_12) 97 #define GPSR2_4 F_(IRQ4, IP1_11_8) 98 #define GPSR2_3 F_(IRQ3, IP1_7_4) 99 #define GPSR2_2 F_(IRQ2, IP1_3_0) 100 #define GPSR2_1 F_(IRQ1, IP0_31_28) 101 #define GPSR2_0 F_(IRQ0, IP0_27_24) 102 103 /* GPSR3 */ 104 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 105 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 106 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 107 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 108 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 109 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 110 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 111 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 112 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 113 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 114 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 115 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 116 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 117 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 118 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 119 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 120 121 /* GPSR4 */ 122 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 123 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 124 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 125 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 126 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 127 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 128 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 129 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 130 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 131 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 132 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 133 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 134 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 135 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 136 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 137 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 138 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 139 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 140 141 /* GPSR5 */ 142 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 143 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 144 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 145 #define GPSR5_22 FM(MSIOF0_RXD) 146 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 147 #define GPSR5_20 FM(MSIOF0_TXD) 148 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 149 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 150 #define GPSR5_17 FM(MSIOF0_SCK) 151 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 152 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 153 #define GPSR5_14 F_(HTX0, IP13_19_16) 154 #define GPSR5_13 F_(HRX0, IP13_15_12) 155 #define GPSR5_12 F_(HSCK0, IP13_11_8) 156 #define GPSR5_11 F_(RX2_A, IP13_7_4) 157 #define GPSR5_10 F_(TX2_A, IP13_3_0) 158 #define GPSR5_9 F_(SCK2, IP12_31_28) 159 #define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24) 160 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 161 #define GPSR5_6 F_(TX1_A, IP12_19_16) 162 #define GPSR5_5 F_(RX1_A, IP12_15_12) 163 #define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8) 164 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 165 #define GPSR5_2 F_(TX0, IP12_3_0) 166 #define GPSR5_1 F_(RX0, IP11_31_28) 167 #define GPSR5_0 F_(SCK0, IP11_27_24) 168 169 /* GPSR6 */ 170 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4) 171 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0) 172 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 173 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 174 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 175 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 176 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 177 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 178 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 179 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 180 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 181 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 182 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 183 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 184 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 185 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 186 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 187 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 188 #define GPSR6_13 FM(SSI_SDATA5) 189 #define GPSR6_12 FM(SSI_WS5) 190 #define GPSR6_11 FM(SSI_SCK5) 191 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 192 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 193 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 194 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 195 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 196 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 197 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 198 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 199 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 200 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 201 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 202 203 /* GPSR7 */ 204 #define GPSR7_3 FM(HDMI1_CEC) 205 #define GPSR7_2 FM(HDMI0_CEC) 206 #define GPSR7_1 FM(AVS2) 207 #define GPSR7_0 FM(AVS1) 208 209 210 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 211 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230 231 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 232 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 247 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 274 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 275 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 306 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 307 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 #define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 328 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 336 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 337 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 357 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 358 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 359 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 360 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 361 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 363 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 364 365 #define PINMUX_GPSR \ 366 \ 367 GPSR6_31 \ 368 GPSR6_30 \ 369 GPSR6_29 \ 370 GPSR6_28 \ 371 GPSR1_27 GPSR6_27 \ 372 GPSR1_26 GPSR6_26 \ 373 GPSR1_25 GPSR5_25 GPSR6_25 \ 374 GPSR1_24 GPSR5_24 GPSR6_24 \ 375 GPSR1_23 GPSR5_23 GPSR6_23 \ 376 GPSR1_22 GPSR5_22 GPSR6_22 \ 377 GPSR1_21 GPSR5_21 GPSR6_21 \ 378 GPSR1_20 GPSR5_20 GPSR6_20 \ 379 GPSR1_19 GPSR5_19 GPSR6_19 \ 380 GPSR1_18 GPSR5_18 GPSR6_18 \ 381 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 382 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 383 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 384 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 385 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 386 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 387 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 388 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 389 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 390 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 391 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 392 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 393 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 394 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 395 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 396 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 397 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 398 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 399 400 #define PINMUX_IPSR \ 401 \ 402 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 403 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 404 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 405 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 406 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 407 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 408 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 409 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 410 \ 411 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 412 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 413 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 414 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 415 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 416 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 417 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 418 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 419 \ 420 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 421 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 422 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 423 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 424 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 425 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 426 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 427 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 428 \ 429 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 430 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 431 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 432 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 433 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 434 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 435 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 436 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 437 \ 438 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 439 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 440 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 441 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 442 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 443 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 444 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 445 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 446 447 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 448 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 449 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 450 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 451 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 452 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 453 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 454 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 455 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 456 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 457 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 458 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 459 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 460 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 461 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 462 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 463 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 464 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 465 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) 466 467 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 468 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 469 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 470 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1) 471 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 472 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 473 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) 474 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 475 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 476 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 477 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 478 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 479 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 480 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 481 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 482 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 483 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 484 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 485 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 486 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 487 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 488 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 489 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 490 491 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 492 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 493 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 494 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 495 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 496 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 497 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 498 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 499 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 500 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 501 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) 502 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) 503 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 504 505 #define PINMUX_MOD_SELS \ 506 \ 507 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 508 MOD_SEL2_30 \ 509 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 510 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 511 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 512 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 513 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 514 MOD_SEL0_22 \ 515 MOD_SEL0_21 MOD_SEL2_21 \ 516 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 517 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 518 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 519 MOD_SEL2_17 \ 520 MOD_SEL0_16 MOD_SEL1_16 \ 521 MOD_SEL1_15_14 \ 522 MOD_SEL0_14_13 \ 523 MOD_SEL1_13 \ 524 MOD_SEL0_12 MOD_SEL1_12 \ 525 MOD_SEL0_11 MOD_SEL1_11 \ 526 MOD_SEL0_10 MOD_SEL1_10 \ 527 MOD_SEL0_9_8 MOD_SEL1_9 \ 528 MOD_SEL0_7_6 \ 529 MOD_SEL1_6 \ 530 MOD_SEL0_5 MOD_SEL1_5 \ 531 MOD_SEL0_4_3 MOD_SEL1_4 \ 532 MOD_SEL1_3 \ 533 MOD_SEL1_2 \ 534 MOD_SEL1_1 \ 535 MOD_SEL1_0 MOD_SEL2_0 536 537 /* 538 * These pins are not able to be muxed but have other properties 539 * that can be set, such as drive-strength or pull-up/pull-down enable. 540 */ 541 #define PINMUX_STATIC \ 542 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 543 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 544 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 545 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 546 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 547 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 548 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 549 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 550 FM(CLKOUT) FM(PRESETOUT) \ 551 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ 552 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 553 554 enum { 555 PINMUX_RESERVED = 0, 556 557 PINMUX_DATA_BEGIN, 558 GP_ALL(DATA), 559 PINMUX_DATA_END, 560 561 #define F_(x, y) 562 #define FM(x) FN_##x, 563 PINMUX_FUNCTION_BEGIN, 564 GP_ALL(FN), 565 PINMUX_GPSR 566 PINMUX_IPSR 567 PINMUX_MOD_SELS 568 PINMUX_FUNCTION_END, 569 #undef F_ 570 #undef FM 571 572 #define F_(x, y) 573 #define FM(x) x##_MARK, 574 PINMUX_MARK_BEGIN, 575 PINMUX_GPSR 576 PINMUX_IPSR 577 PINMUX_MOD_SELS 578 PINMUX_STATIC 579 PINMUX_MARK_END, 580 #undef F_ 581 #undef FM 582 }; 583 584 static const u16 pinmux_data[] = { 585 PINMUX_DATA_GP_ALL(), 586 587 PINMUX_SINGLE(AVS1), 588 PINMUX_SINGLE(AVS2), 589 PINMUX_SINGLE(HDMI0_CEC), 590 PINMUX_SINGLE(HDMI1_CEC), 591 PINMUX_SINGLE(I2C_SEL_0_1), 592 PINMUX_SINGLE(I2C_SEL_3_1), 593 PINMUX_SINGLE(I2C_SEL_5_1), 594 PINMUX_SINGLE(MSIOF0_RXD), 595 PINMUX_SINGLE(MSIOF0_SCK), 596 PINMUX_SINGLE(MSIOF0_TXD), 597 PINMUX_SINGLE(SSI_SCK5), 598 PINMUX_SINGLE(SSI_SDATA5), 599 PINMUX_SINGLE(SSI_WS5), 600 601 /* IPSR0 */ 602 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 603 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 604 605 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 606 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 607 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 608 609 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 610 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 611 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 612 613 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 614 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 615 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 616 617 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), 618 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), 619 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), 620 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), 621 622 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), 623 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), 624 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), 625 626 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 627 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 628 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 629 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 630 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 631 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 632 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 633 634 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 635 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 636 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 637 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 638 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 639 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 640 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 641 642 /* IPSR1 */ 643 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 644 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 645 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 646 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 647 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 648 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 649 650 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 651 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 652 PINMUX_IPSR_GPSR(IP1_7_4, A25), 653 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 654 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 655 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 656 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 657 658 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 659 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 660 PINMUX_IPSR_GPSR(IP1_11_8, A24), 661 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 662 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 663 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 664 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 665 666 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 667 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 668 PINMUX_IPSR_GPSR(IP1_15_12, A23), 669 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 670 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 671 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 672 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 673 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 674 675 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 676 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 677 PINMUX_IPSR_GPSR(IP1_19_16, A22), 678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 680 681 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), 682 PINMUX_IPSR_GPSR(IP1_23_20, A21), 683 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), 684 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), 685 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), 686 687 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), 688 PINMUX_IPSR_GPSR(IP1_27_24, A20), 689 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), 690 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), 691 692 PINMUX_IPSR_GPSR(IP1_31_28, A0), 693 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 694 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 695 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 696 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 697 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 698 699 /* IPSR2 */ 700 PINMUX_IPSR_GPSR(IP2_3_0, A1), 701 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 702 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 703 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 704 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 705 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 706 707 PINMUX_IPSR_GPSR(IP2_7_4, A2), 708 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 709 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 710 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 711 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 712 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 713 714 PINMUX_IPSR_GPSR(IP2_11_8, A3), 715 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 716 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 717 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 718 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 719 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 720 721 PINMUX_IPSR_GPSR(IP2_15_12, A4), 722 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 723 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 724 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 725 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 726 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 727 728 PINMUX_IPSR_GPSR(IP2_19_16, A5), 729 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 730 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 731 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 732 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 733 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 734 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 735 736 PINMUX_IPSR_GPSR(IP2_23_20, A6), 737 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 738 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 739 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 740 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 741 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 742 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 743 744 PINMUX_IPSR_GPSR(IP2_27_24, A7), 745 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 746 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 747 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 748 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 749 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 750 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 751 752 PINMUX_IPSR_GPSR(IP2_31_28, A8), 753 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 754 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 755 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 756 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 757 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 758 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 759 760 /* IPSR3 */ 761 PINMUX_IPSR_GPSR(IP3_3_0, A9), 762 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 763 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 764 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 765 766 PINMUX_IPSR_GPSR(IP3_7_4, A10), 767 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 768 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), 769 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 770 771 PINMUX_IPSR_GPSR(IP3_11_8, A11), 772 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 773 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 774 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 775 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 776 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 777 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 778 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 779 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 780 781 PINMUX_IPSR_GPSR(IP3_15_12, A12), 782 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 783 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 784 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 785 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 786 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 787 788 PINMUX_IPSR_GPSR(IP3_19_16, A13), 789 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 790 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 791 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 792 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 793 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 794 795 PINMUX_IPSR_GPSR(IP3_23_20, A14), 796 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 797 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 798 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 799 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 800 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 801 802 PINMUX_IPSR_GPSR(IP3_27_24, A15), 803 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 804 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 805 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 806 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 807 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 808 809 PINMUX_IPSR_GPSR(IP3_31_28, A16), 810 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 811 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 812 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 813 814 /* IPSR4 */ 815 PINMUX_IPSR_GPSR(IP4_3_0, A17), 816 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 817 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 818 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 819 820 PINMUX_IPSR_GPSR(IP4_7_4, A18), 821 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 822 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 823 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 824 825 PINMUX_IPSR_GPSR(IP4_11_8, A19), 826 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 827 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 828 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 829 830 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 831 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 832 833 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 834 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 835 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 836 837 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 838 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 839 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 840 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 841 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 842 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 843 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 844 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 845 846 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 847 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 848 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 849 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 850 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 851 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 852 853 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 854 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 855 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 856 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 857 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 858 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 859 860 /* IPSR5 */ 861 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 862 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 863 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 864 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 865 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 866 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 867 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 868 869 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 870 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 871 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), 872 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 873 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 874 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 875 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 876 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 877 878 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 879 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 880 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 881 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 882 883 PINMUX_IPSR_GPSR(IP5_15_12, D0), 884 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 886 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 887 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 888 889 PINMUX_IPSR_GPSR(IP5_19_16, D1), 890 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 892 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 893 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 894 895 PINMUX_IPSR_GPSR(IP5_23_20, D2), 896 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 897 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 898 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 899 900 PINMUX_IPSR_GPSR(IP5_27_24, D3), 901 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 902 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 903 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 904 905 PINMUX_IPSR_GPSR(IP5_31_28, D4), 906 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 907 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 908 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 909 910 /* IPSR6 */ 911 PINMUX_IPSR_GPSR(IP6_3_0, D5), 912 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 913 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 914 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 915 916 PINMUX_IPSR_GPSR(IP6_7_4, D6), 917 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 918 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 919 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 920 921 PINMUX_IPSR_GPSR(IP6_11_8, D7), 922 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 923 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 924 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 925 926 PINMUX_IPSR_GPSR(IP6_15_12, D8), 927 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 928 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 929 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 930 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 931 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 932 933 PINMUX_IPSR_GPSR(IP6_19_16, D9), 934 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 935 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 936 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 937 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 938 939 PINMUX_IPSR_GPSR(IP6_23_20, D10), 940 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 941 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 942 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 943 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 944 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 945 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 946 947 PINMUX_IPSR_GPSR(IP6_27_24, D11), 948 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 949 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 950 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 951 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 952 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), 953 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 954 955 PINMUX_IPSR_GPSR(IP6_31_28, D12), 956 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 957 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 958 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 959 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 960 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 961 962 /* IPSR7 */ 963 PINMUX_IPSR_GPSR(IP7_3_0, D13), 964 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 965 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 966 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 967 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 968 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 969 970 PINMUX_IPSR_GPSR(IP7_7_4, D14), 971 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 972 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 973 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 974 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 975 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 976 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 977 978 PINMUX_IPSR_GPSR(IP7_11_8, D15), 979 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 980 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 981 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 982 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 983 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 984 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 985 986 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 987 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 988 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 989 990 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 991 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 992 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 993 994 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 995 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 996 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 997 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 998 999 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1000 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1001 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1002 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1003 1004 /* IPSR8 */ 1005 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1006 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1007 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1008 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1009 1010 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1011 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1012 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1013 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1014 1015 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1016 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1017 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1018 1019 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1020 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1021 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B), 1022 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1023 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1024 1025 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1026 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1027 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1028 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B), 1029 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1030 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1031 1032 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1033 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1034 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1035 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B), 1036 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1037 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1038 1039 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1040 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1041 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1042 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B), 1043 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1044 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1045 1046 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1047 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1048 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1049 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B), 1050 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1051 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1052 1053 /* IPSR9 */ 1054 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1055 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1056 1057 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1058 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1059 1060 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1061 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1062 1063 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1064 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1065 1066 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1067 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1068 1069 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1070 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1071 1072 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1073 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1074 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1075 1076 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1077 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1078 1079 /* IPSR10 */ 1080 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1081 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1082 1083 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1084 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1085 1086 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1087 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1088 1089 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1090 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1091 1092 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1093 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1094 1095 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1096 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1097 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1098 1099 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1100 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1101 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1102 1103 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1105 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1106 1107 /* IPSR11 */ 1108 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1110 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1111 1112 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1113 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1114 1115 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1116 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1117 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1118 1119 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1120 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1121 1122 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), 1123 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), 1124 1125 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), 1126 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), 1127 1128 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1129 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1130 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1131 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), 1132 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1133 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1134 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1135 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1136 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1137 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1138 1139 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1140 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1141 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1142 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1143 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1144 1145 /* IPSR12 */ 1146 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1147 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1148 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1149 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1150 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1151 1152 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1153 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1154 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1155 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1156 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1157 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1158 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1159 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1160 1161 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS), 1162 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1163 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1164 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), 1165 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1166 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1167 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1168 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1169 1170 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1171 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1172 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1173 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1174 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1175 1176 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1177 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1178 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1179 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1180 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1181 1182 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1183 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1184 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1185 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1186 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1187 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1188 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1189 1190 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS), 1191 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1192 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1193 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1194 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1195 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1196 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1197 1198 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1199 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1200 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1201 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1202 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1203 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1204 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1205 1206 /* IPSR13 */ 1207 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1208 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1209 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1210 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1211 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1212 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1213 1214 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1215 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1216 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1217 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1218 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1219 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1220 1221 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1222 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1223 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), 1224 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1), 1225 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1226 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1227 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1228 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1229 1230 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1231 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1232 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1), 1233 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1234 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1235 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1236 1237 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1238 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1239 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1), 1240 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1241 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1242 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1243 1244 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1245 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1246 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1247 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0), 1248 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1249 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1250 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1251 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1252 1253 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1254 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1255 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1256 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0), 1257 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1258 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1259 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1260 1261 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1262 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1263 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1264 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1265 1266 /* IPSR14 */ 1267 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1268 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1269 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), 1270 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), 1271 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), 1272 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1273 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1274 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1), 1275 1276 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1277 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1278 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1279 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), 1280 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0), 1281 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1282 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1283 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1284 1285 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1286 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1287 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1288 1289 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1290 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1291 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1292 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1293 1294 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1295 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1296 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1297 1298 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1299 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1300 1301 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1302 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1303 1304 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1305 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1306 1307 /* IPSR15 */ 1308 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0), 1309 1310 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0), 1311 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1), 1312 1313 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1314 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1315 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1316 1317 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1318 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1319 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1320 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1321 1322 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1323 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1324 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1325 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1326 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1327 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1328 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1329 1330 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1331 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1332 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1333 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1334 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1335 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1336 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1337 1338 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1339 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1340 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1341 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1342 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1343 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1345 1346 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1347 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1348 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1349 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1350 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1351 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1352 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1353 1354 /* IPSR16 */ 1355 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1356 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN), 1357 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1358 1359 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1360 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC), 1361 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1362 1363 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1364 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1365 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1366 1367 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1368 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1369 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1370 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1371 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1372 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1374 1375 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1376 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1377 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1378 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1379 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1380 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1382 1383 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1384 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1385 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1386 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1387 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1388 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1390 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1391 1392 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1393 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1394 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1395 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1396 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1397 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1399 1400 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0), 1401 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1402 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1403 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1404 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), 1405 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1406 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1407 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1408 1409 /* IPSR17 */ 1410 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), 1411 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), 1412 1413 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), 1414 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1415 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1416 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1417 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0), 1418 1419 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1420 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1421 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1422 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1423 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1424 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1425 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1426 1427 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1428 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1429 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1430 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1431 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1432 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1433 1434 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1435 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1436 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0), 1437 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1438 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1439 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1440 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1441 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1442 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1443 1444 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1445 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1446 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0), 1447 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1448 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1449 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1450 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1451 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1452 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1453 1454 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1455 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1456 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), 1457 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1458 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1460 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1461 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1462 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1463 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1464 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1465 1466 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1467 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1468 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1), 1469 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1470 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1472 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1473 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1474 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1475 1476 /* IPSR18 */ 1477 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN), 1478 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1479 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), 1480 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1481 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1482 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1483 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1484 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1486 1487 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC), 1488 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1489 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), 1490 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1491 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1492 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1493 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1494 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1496 1497 /* 1498 * Static pins can not be muxed between different functions but 1499 * still needs a mark entry in the pinmux list. Add each static 1500 * pin to the list without an associated function. The sh-pfc 1501 * core will do the right thing and skip trying to mux then pin 1502 * while still applying configuration to it 1503 */ 1504 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1505 PINMUX_STATIC 1506 #undef FM 1507 }; 1508 1509 /* 1510 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. 1511 * Physical layout rows: A - AW, cols: 1 - 39. 1512 */ 1513 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) 1514 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) 1515 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) 1516 1517 static const struct sh_pfc_pin pinmux_pins[] = { 1518 PINMUX_GPIO_GP_ALL(), 1519 1520 /* 1521 * Pins not associated with a GPIO port. 1522 * 1523 * The pin positions are different between different r8a7795 1524 * packages, all that is needed for the pfc driver is a unique 1525 * number for each pin. To this end use the pin layout from 1526 * R-Car H3SiP to calculate a unique number for each pin. 1527 */ 1528 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), 1529 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), 1530 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), 1531 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), 1532 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), 1533 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), 1534 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), 1535 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), 1536 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), 1537 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), 1538 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), 1539 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), 1540 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), 1541 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), 1542 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), 1543 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS), 1544 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), 1545 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), 1546 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), 1547 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), 1548 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), 1549 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), 1550 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), 1551 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), 1552 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), 1553 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), 1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), 1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), 1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), 1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), 1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), 1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), 1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), 1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), 1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), 1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), 1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), 1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), 1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), 1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), 1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), 1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), 1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), 1572 }; 1573 1574 /* - EtherAVB --------------------------------------------------------------- */ 1575 static const unsigned int avb_link_pins[] = { 1576 /* AVB_LINK */ 1577 RCAR_GP_PIN(2, 12), 1578 }; 1579 static const unsigned int avb_link_mux[] = { 1580 AVB_LINK_MARK, 1581 }; 1582 static const unsigned int avb_magic_pins[] = { 1583 /* AVB_MAGIC_ */ 1584 RCAR_GP_PIN(2, 10), 1585 }; 1586 static const unsigned int avb_magic_mux[] = { 1587 AVB_MAGIC_MARK, 1588 }; 1589 static const unsigned int avb_phy_int_pins[] = { 1590 /* AVB_PHY_INT */ 1591 RCAR_GP_PIN(2, 11), 1592 }; 1593 static const unsigned int avb_phy_int_mux[] = { 1594 AVB_PHY_INT_MARK, 1595 }; 1596 static const unsigned int avb_mdc_pins[] = { 1597 /* AVB_MDC, AVB_MDIO */ 1598 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), 1599 }; 1600 static const unsigned int avb_mdc_mux[] = { 1601 AVB_MDC_MARK, AVB_MDIO_MARK, 1602 }; 1603 static const unsigned int avb_mii_pins[] = { 1604 /* 1605 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1606 * AVB_TD1, AVB_TD2, AVB_TD3, 1607 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1608 * AVB_RD1, AVB_RD2, AVB_RD3, 1609 * AVB_TXCREFCLK 1610 */ 1611 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), 1612 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), 1613 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), 1614 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), 1615 PIN_NUMBER('A', 12), 1616 1617 }; 1618 static const unsigned int avb_mii_mux[] = { 1619 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1620 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1621 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1622 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1623 AVB_TXCREFCLK_MARK, 1624 }; 1625 static const unsigned int avb_avtp_pps_pins[] = { 1626 /* AVB_AVTP_PPS */ 1627 RCAR_GP_PIN(2, 6), 1628 }; 1629 static const unsigned int avb_avtp_pps_mux[] = { 1630 AVB_AVTP_PPS_MARK, 1631 }; 1632 static const unsigned int avb_avtp_match_a_pins[] = { 1633 /* AVB_AVTP_MATCH_A */ 1634 RCAR_GP_PIN(2, 13), 1635 }; 1636 static const unsigned int avb_avtp_match_a_mux[] = { 1637 AVB_AVTP_MATCH_A_MARK, 1638 }; 1639 static const unsigned int avb_avtp_capture_a_pins[] = { 1640 /* AVB_AVTP_CAPTURE_A */ 1641 RCAR_GP_PIN(2, 14), 1642 }; 1643 static const unsigned int avb_avtp_capture_a_mux[] = { 1644 AVB_AVTP_CAPTURE_A_MARK, 1645 }; 1646 static const unsigned int avb_avtp_match_b_pins[] = { 1647 /* AVB_AVTP_MATCH_B */ 1648 RCAR_GP_PIN(1, 8), 1649 }; 1650 static const unsigned int avb_avtp_match_b_mux[] = { 1651 AVB_AVTP_MATCH_B_MARK, 1652 }; 1653 static const unsigned int avb_avtp_capture_b_pins[] = { 1654 /* AVB_AVTP_CAPTURE_B */ 1655 RCAR_GP_PIN(1, 11), 1656 }; 1657 static const unsigned int avb_avtp_capture_b_mux[] = { 1658 AVB_AVTP_CAPTURE_B_MARK, 1659 }; 1660 1661 /* - DRIF0 --------------------------------------------------------------- */ 1662 static const unsigned int drif0_ctrl_a_pins[] = { 1663 /* CLK, SYNC */ 1664 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1665 }; 1666 static const unsigned int drif0_ctrl_a_mux[] = { 1667 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1668 }; 1669 static const unsigned int drif0_data0_a_pins[] = { 1670 /* D0 */ 1671 RCAR_GP_PIN(6, 10), 1672 }; 1673 static const unsigned int drif0_data0_a_mux[] = { 1674 RIF0_D0_A_MARK, 1675 }; 1676 static const unsigned int drif0_data1_a_pins[] = { 1677 /* D1 */ 1678 RCAR_GP_PIN(6, 7), 1679 }; 1680 static const unsigned int drif0_data1_a_mux[] = { 1681 RIF0_D1_A_MARK, 1682 }; 1683 static const unsigned int drif0_ctrl_b_pins[] = { 1684 /* CLK, SYNC */ 1685 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1686 }; 1687 static const unsigned int drif0_ctrl_b_mux[] = { 1688 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1689 }; 1690 static const unsigned int drif0_data0_b_pins[] = { 1691 /* D0 */ 1692 RCAR_GP_PIN(5, 1), 1693 }; 1694 static const unsigned int drif0_data0_b_mux[] = { 1695 RIF0_D0_B_MARK, 1696 }; 1697 static const unsigned int drif0_data1_b_pins[] = { 1698 /* D1 */ 1699 RCAR_GP_PIN(5, 2), 1700 }; 1701 static const unsigned int drif0_data1_b_mux[] = { 1702 RIF0_D1_B_MARK, 1703 }; 1704 static const unsigned int drif0_ctrl_c_pins[] = { 1705 /* CLK, SYNC */ 1706 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1707 }; 1708 static const unsigned int drif0_ctrl_c_mux[] = { 1709 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1710 }; 1711 static const unsigned int drif0_data0_c_pins[] = { 1712 /* D0 */ 1713 RCAR_GP_PIN(5, 13), 1714 }; 1715 static const unsigned int drif0_data0_c_mux[] = { 1716 RIF0_D0_C_MARK, 1717 }; 1718 static const unsigned int drif0_data1_c_pins[] = { 1719 /* D1 */ 1720 RCAR_GP_PIN(5, 14), 1721 }; 1722 static const unsigned int drif0_data1_c_mux[] = { 1723 RIF0_D1_C_MARK, 1724 }; 1725 /* - DRIF1 --------------------------------------------------------------- */ 1726 static const unsigned int drif1_ctrl_a_pins[] = { 1727 /* CLK, SYNC */ 1728 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1729 }; 1730 static const unsigned int drif1_ctrl_a_mux[] = { 1731 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1732 }; 1733 static const unsigned int drif1_data0_a_pins[] = { 1734 /* D0 */ 1735 RCAR_GP_PIN(6, 19), 1736 }; 1737 static const unsigned int drif1_data0_a_mux[] = { 1738 RIF1_D0_A_MARK, 1739 }; 1740 static const unsigned int drif1_data1_a_pins[] = { 1741 /* D1 */ 1742 RCAR_GP_PIN(6, 20), 1743 }; 1744 static const unsigned int drif1_data1_a_mux[] = { 1745 RIF1_D1_A_MARK, 1746 }; 1747 static const unsigned int drif1_ctrl_b_pins[] = { 1748 /* CLK, SYNC */ 1749 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1750 }; 1751 static const unsigned int drif1_ctrl_b_mux[] = { 1752 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1753 }; 1754 static const unsigned int drif1_data0_b_pins[] = { 1755 /* D0 */ 1756 RCAR_GP_PIN(5, 7), 1757 }; 1758 static const unsigned int drif1_data0_b_mux[] = { 1759 RIF1_D0_B_MARK, 1760 }; 1761 static const unsigned int drif1_data1_b_pins[] = { 1762 /* D1 */ 1763 RCAR_GP_PIN(5, 8), 1764 }; 1765 static const unsigned int drif1_data1_b_mux[] = { 1766 RIF1_D1_B_MARK, 1767 }; 1768 static const unsigned int drif1_ctrl_c_pins[] = { 1769 /* CLK, SYNC */ 1770 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1771 }; 1772 static const unsigned int drif1_ctrl_c_mux[] = { 1773 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1774 }; 1775 static const unsigned int drif1_data0_c_pins[] = { 1776 /* D0 */ 1777 RCAR_GP_PIN(5, 6), 1778 }; 1779 static const unsigned int drif1_data0_c_mux[] = { 1780 RIF1_D0_C_MARK, 1781 }; 1782 static const unsigned int drif1_data1_c_pins[] = { 1783 /* D1 */ 1784 RCAR_GP_PIN(5, 10), 1785 }; 1786 static const unsigned int drif1_data1_c_mux[] = { 1787 RIF1_D1_C_MARK, 1788 }; 1789 /* - DRIF2 --------------------------------------------------------------- */ 1790 static const unsigned int drif2_ctrl_a_pins[] = { 1791 /* CLK, SYNC */ 1792 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1793 }; 1794 static const unsigned int drif2_ctrl_a_mux[] = { 1795 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1796 }; 1797 static const unsigned int drif2_data0_a_pins[] = { 1798 /* D0 */ 1799 RCAR_GP_PIN(6, 7), 1800 }; 1801 static const unsigned int drif2_data0_a_mux[] = { 1802 RIF2_D0_A_MARK, 1803 }; 1804 static const unsigned int drif2_data1_a_pins[] = { 1805 /* D1 */ 1806 RCAR_GP_PIN(6, 10), 1807 }; 1808 static const unsigned int drif2_data1_a_mux[] = { 1809 RIF2_D1_A_MARK, 1810 }; 1811 static const unsigned int drif2_ctrl_b_pins[] = { 1812 /* CLK, SYNC */ 1813 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 1814 }; 1815 static const unsigned int drif2_ctrl_b_mux[] = { 1816 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1817 }; 1818 static const unsigned int drif2_data0_b_pins[] = { 1819 /* D0 */ 1820 RCAR_GP_PIN(6, 30), 1821 }; 1822 static const unsigned int drif2_data0_b_mux[] = { 1823 RIF2_D0_B_MARK, 1824 }; 1825 static const unsigned int drif2_data1_b_pins[] = { 1826 /* D1 */ 1827 RCAR_GP_PIN(6, 31), 1828 }; 1829 static const unsigned int drif2_data1_b_mux[] = { 1830 RIF2_D1_B_MARK, 1831 }; 1832 /* - DRIF3 --------------------------------------------------------------- */ 1833 static const unsigned int drif3_ctrl_a_pins[] = { 1834 /* CLK, SYNC */ 1835 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1836 }; 1837 static const unsigned int drif3_ctrl_a_mux[] = { 1838 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 1839 }; 1840 static const unsigned int drif3_data0_a_pins[] = { 1841 /* D0 */ 1842 RCAR_GP_PIN(6, 19), 1843 }; 1844 static const unsigned int drif3_data0_a_mux[] = { 1845 RIF3_D0_A_MARK, 1846 }; 1847 static const unsigned int drif3_data1_a_pins[] = { 1848 /* D1 */ 1849 RCAR_GP_PIN(6, 20), 1850 }; 1851 static const unsigned int drif3_data1_a_mux[] = { 1852 RIF3_D1_A_MARK, 1853 }; 1854 static const unsigned int drif3_ctrl_b_pins[] = { 1855 /* CLK, SYNC */ 1856 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 1857 }; 1858 static const unsigned int drif3_ctrl_b_mux[] = { 1859 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 1860 }; 1861 static const unsigned int drif3_data0_b_pins[] = { 1862 /* D0 */ 1863 RCAR_GP_PIN(6, 28), 1864 }; 1865 static const unsigned int drif3_data0_b_mux[] = { 1866 RIF3_D0_B_MARK, 1867 }; 1868 static const unsigned int drif3_data1_b_pins[] = { 1869 /* D1 */ 1870 RCAR_GP_PIN(6, 29), 1871 }; 1872 static const unsigned int drif3_data1_b_mux[] = { 1873 RIF3_D1_B_MARK, 1874 }; 1875 1876 /* - DU --------------------------------------------------------------------- */ 1877 static const unsigned int du_rgb666_pins[] = { 1878 /* R[7:2], G[7:2], B[7:2] */ 1879 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 1880 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 1881 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1882 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1883 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 1884 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 1885 }; 1886 static const unsigned int du_rgb666_mux[] = { 1887 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1888 DU_DR3_MARK, DU_DR2_MARK, 1889 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1890 DU_DG3_MARK, DU_DG2_MARK, 1891 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1892 DU_DB3_MARK, DU_DB2_MARK, 1893 }; 1894 static const unsigned int du_rgb888_pins[] = { 1895 /* R[7:0], G[7:0], B[7:0] */ 1896 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 1897 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 1898 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 1899 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1900 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1901 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 1902 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 1903 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 1904 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 1905 }; 1906 static const unsigned int du_rgb888_mux[] = { 1907 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1908 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 1909 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1910 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 1911 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1912 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 1913 }; 1914 static const unsigned int du_clk_out_0_pins[] = { 1915 /* CLKOUT */ 1916 RCAR_GP_PIN(1, 27), 1917 }; 1918 static const unsigned int du_clk_out_0_mux[] = { 1919 DU_DOTCLKOUT0_MARK 1920 }; 1921 static const unsigned int du_clk_out_1_pins[] = { 1922 /* CLKOUT */ 1923 RCAR_GP_PIN(2, 3), 1924 }; 1925 static const unsigned int du_clk_out_1_mux[] = { 1926 DU_DOTCLKOUT1_MARK 1927 }; 1928 static const unsigned int du_sync_pins[] = { 1929 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 1930 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 1931 }; 1932 static const unsigned int du_sync_mux[] = { 1933 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 1934 }; 1935 static const unsigned int du_oddf_pins[] = { 1936 /* EXDISP/EXODDF/EXCDE */ 1937 RCAR_GP_PIN(2, 2), 1938 }; 1939 static const unsigned int du_oddf_mux[] = { 1940 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 1941 }; 1942 static const unsigned int du_cde_pins[] = { 1943 /* CDE */ 1944 RCAR_GP_PIN(2, 0), 1945 }; 1946 static const unsigned int du_cde_mux[] = { 1947 DU_CDE_MARK, 1948 }; 1949 static const unsigned int du_disp_pins[] = { 1950 /* DISP */ 1951 RCAR_GP_PIN(2, 1), 1952 }; 1953 static const unsigned int du_disp_mux[] = { 1954 DU_DISP_MARK, 1955 }; 1956 1957 /* - MSIOF0 ----------------------------------------------------------------- */ 1958 static const unsigned int msiof0_clk_pins[] = { 1959 /* SCK */ 1960 RCAR_GP_PIN(5, 17), 1961 }; 1962 static const unsigned int msiof0_clk_mux[] = { 1963 MSIOF0_SCK_MARK, 1964 }; 1965 static const unsigned int msiof0_sync_pins[] = { 1966 /* SYNC */ 1967 RCAR_GP_PIN(5, 18), 1968 }; 1969 static const unsigned int msiof0_sync_mux[] = { 1970 MSIOF0_SYNC_MARK, 1971 }; 1972 static const unsigned int msiof0_ss1_pins[] = { 1973 /* SS1 */ 1974 RCAR_GP_PIN(5, 19), 1975 }; 1976 static const unsigned int msiof0_ss1_mux[] = { 1977 MSIOF0_SS1_MARK, 1978 }; 1979 static const unsigned int msiof0_ss2_pins[] = { 1980 /* SS2 */ 1981 RCAR_GP_PIN(5, 21), 1982 }; 1983 static const unsigned int msiof0_ss2_mux[] = { 1984 MSIOF0_SS2_MARK, 1985 }; 1986 static const unsigned int msiof0_txd_pins[] = { 1987 /* TXD */ 1988 RCAR_GP_PIN(5, 20), 1989 }; 1990 static const unsigned int msiof0_txd_mux[] = { 1991 MSIOF0_TXD_MARK, 1992 }; 1993 static const unsigned int msiof0_rxd_pins[] = { 1994 /* RXD */ 1995 RCAR_GP_PIN(5, 22), 1996 }; 1997 static const unsigned int msiof0_rxd_mux[] = { 1998 MSIOF0_RXD_MARK, 1999 }; 2000 /* - MSIOF1 ----------------------------------------------------------------- */ 2001 static const unsigned int msiof1_clk_a_pins[] = { 2002 /* SCK */ 2003 RCAR_GP_PIN(6, 8), 2004 }; 2005 static const unsigned int msiof1_clk_a_mux[] = { 2006 MSIOF1_SCK_A_MARK, 2007 }; 2008 static const unsigned int msiof1_sync_a_pins[] = { 2009 /* SYNC */ 2010 RCAR_GP_PIN(6, 9), 2011 }; 2012 static const unsigned int msiof1_sync_a_mux[] = { 2013 MSIOF1_SYNC_A_MARK, 2014 }; 2015 static const unsigned int msiof1_ss1_a_pins[] = { 2016 /* SS1 */ 2017 RCAR_GP_PIN(6, 5), 2018 }; 2019 static const unsigned int msiof1_ss1_a_mux[] = { 2020 MSIOF1_SS1_A_MARK, 2021 }; 2022 static const unsigned int msiof1_ss2_a_pins[] = { 2023 /* SS2 */ 2024 RCAR_GP_PIN(6, 6), 2025 }; 2026 static const unsigned int msiof1_ss2_a_mux[] = { 2027 MSIOF1_SS2_A_MARK, 2028 }; 2029 static const unsigned int msiof1_txd_a_pins[] = { 2030 /* TXD */ 2031 RCAR_GP_PIN(6, 7), 2032 }; 2033 static const unsigned int msiof1_txd_a_mux[] = { 2034 MSIOF1_TXD_A_MARK, 2035 }; 2036 static const unsigned int msiof1_rxd_a_pins[] = { 2037 /* RXD */ 2038 RCAR_GP_PIN(6, 10), 2039 }; 2040 static const unsigned int msiof1_rxd_a_mux[] = { 2041 MSIOF1_RXD_A_MARK, 2042 }; 2043 static const unsigned int msiof1_clk_b_pins[] = { 2044 /* SCK */ 2045 RCAR_GP_PIN(5, 9), 2046 }; 2047 static const unsigned int msiof1_clk_b_mux[] = { 2048 MSIOF1_SCK_B_MARK, 2049 }; 2050 static const unsigned int msiof1_sync_b_pins[] = { 2051 /* SYNC */ 2052 RCAR_GP_PIN(5, 3), 2053 }; 2054 static const unsigned int msiof1_sync_b_mux[] = { 2055 MSIOF1_SYNC_B_MARK, 2056 }; 2057 static const unsigned int msiof1_ss1_b_pins[] = { 2058 /* SS1 */ 2059 RCAR_GP_PIN(5, 4), 2060 }; 2061 static const unsigned int msiof1_ss1_b_mux[] = { 2062 MSIOF1_SS1_B_MARK, 2063 }; 2064 static const unsigned int msiof1_ss2_b_pins[] = { 2065 /* SS2 */ 2066 RCAR_GP_PIN(5, 0), 2067 }; 2068 static const unsigned int msiof1_ss2_b_mux[] = { 2069 MSIOF1_SS2_B_MARK, 2070 }; 2071 static const unsigned int msiof1_txd_b_pins[] = { 2072 /* TXD */ 2073 RCAR_GP_PIN(5, 8), 2074 }; 2075 static const unsigned int msiof1_txd_b_mux[] = { 2076 MSIOF1_TXD_B_MARK, 2077 }; 2078 static const unsigned int msiof1_rxd_b_pins[] = { 2079 /* RXD */ 2080 RCAR_GP_PIN(5, 7), 2081 }; 2082 static const unsigned int msiof1_rxd_b_mux[] = { 2083 MSIOF1_RXD_B_MARK, 2084 }; 2085 static const unsigned int msiof1_clk_c_pins[] = { 2086 /* SCK */ 2087 RCAR_GP_PIN(6, 17), 2088 }; 2089 static const unsigned int msiof1_clk_c_mux[] = { 2090 MSIOF1_SCK_C_MARK, 2091 }; 2092 static const unsigned int msiof1_sync_c_pins[] = { 2093 /* SYNC */ 2094 RCAR_GP_PIN(6, 18), 2095 }; 2096 static const unsigned int msiof1_sync_c_mux[] = { 2097 MSIOF1_SYNC_C_MARK, 2098 }; 2099 static const unsigned int msiof1_ss1_c_pins[] = { 2100 /* SS1 */ 2101 RCAR_GP_PIN(6, 21), 2102 }; 2103 static const unsigned int msiof1_ss1_c_mux[] = { 2104 MSIOF1_SS1_C_MARK, 2105 }; 2106 static const unsigned int msiof1_ss2_c_pins[] = { 2107 /* SS2 */ 2108 RCAR_GP_PIN(6, 27), 2109 }; 2110 static const unsigned int msiof1_ss2_c_mux[] = { 2111 MSIOF1_SS2_C_MARK, 2112 }; 2113 static const unsigned int msiof1_txd_c_pins[] = { 2114 /* TXD */ 2115 RCAR_GP_PIN(6, 20), 2116 }; 2117 static const unsigned int msiof1_txd_c_mux[] = { 2118 MSIOF1_TXD_C_MARK, 2119 }; 2120 static const unsigned int msiof1_rxd_c_pins[] = { 2121 /* RXD */ 2122 RCAR_GP_PIN(6, 19), 2123 }; 2124 static const unsigned int msiof1_rxd_c_mux[] = { 2125 MSIOF1_RXD_C_MARK, 2126 }; 2127 static const unsigned int msiof1_clk_d_pins[] = { 2128 /* SCK */ 2129 RCAR_GP_PIN(5, 12), 2130 }; 2131 static const unsigned int msiof1_clk_d_mux[] = { 2132 MSIOF1_SCK_D_MARK, 2133 }; 2134 static const unsigned int msiof1_sync_d_pins[] = { 2135 /* SYNC */ 2136 RCAR_GP_PIN(5, 15), 2137 }; 2138 static const unsigned int msiof1_sync_d_mux[] = { 2139 MSIOF1_SYNC_D_MARK, 2140 }; 2141 static const unsigned int msiof1_ss1_d_pins[] = { 2142 /* SS1 */ 2143 RCAR_GP_PIN(5, 16), 2144 }; 2145 static const unsigned int msiof1_ss1_d_mux[] = { 2146 MSIOF1_SS1_D_MARK, 2147 }; 2148 static const unsigned int msiof1_ss2_d_pins[] = { 2149 /* SS2 */ 2150 RCAR_GP_PIN(5, 21), 2151 }; 2152 static const unsigned int msiof1_ss2_d_mux[] = { 2153 MSIOF1_SS2_D_MARK, 2154 }; 2155 static const unsigned int msiof1_txd_d_pins[] = { 2156 /* TXD */ 2157 RCAR_GP_PIN(5, 14), 2158 }; 2159 static const unsigned int msiof1_txd_d_mux[] = { 2160 MSIOF1_TXD_D_MARK, 2161 }; 2162 static const unsigned int msiof1_rxd_d_pins[] = { 2163 /* RXD */ 2164 RCAR_GP_PIN(5, 13), 2165 }; 2166 static const unsigned int msiof1_rxd_d_mux[] = { 2167 MSIOF1_RXD_D_MARK, 2168 }; 2169 static const unsigned int msiof1_clk_e_pins[] = { 2170 /* SCK */ 2171 RCAR_GP_PIN(3, 0), 2172 }; 2173 static const unsigned int msiof1_clk_e_mux[] = { 2174 MSIOF1_SCK_E_MARK, 2175 }; 2176 static const unsigned int msiof1_sync_e_pins[] = { 2177 /* SYNC */ 2178 RCAR_GP_PIN(3, 1), 2179 }; 2180 static const unsigned int msiof1_sync_e_mux[] = { 2181 MSIOF1_SYNC_E_MARK, 2182 }; 2183 static const unsigned int msiof1_ss1_e_pins[] = { 2184 /* SS1 */ 2185 RCAR_GP_PIN(3, 4), 2186 }; 2187 static const unsigned int msiof1_ss1_e_mux[] = { 2188 MSIOF1_SS1_E_MARK, 2189 }; 2190 static const unsigned int msiof1_ss2_e_pins[] = { 2191 /* SS2 */ 2192 RCAR_GP_PIN(3, 5), 2193 }; 2194 static const unsigned int msiof1_ss2_e_mux[] = { 2195 MSIOF1_SS2_E_MARK, 2196 }; 2197 static const unsigned int msiof1_txd_e_pins[] = { 2198 /* TXD */ 2199 RCAR_GP_PIN(3, 3), 2200 }; 2201 static const unsigned int msiof1_txd_e_mux[] = { 2202 MSIOF1_TXD_E_MARK, 2203 }; 2204 static const unsigned int msiof1_rxd_e_pins[] = { 2205 /* RXD */ 2206 RCAR_GP_PIN(3, 2), 2207 }; 2208 static const unsigned int msiof1_rxd_e_mux[] = { 2209 MSIOF1_RXD_E_MARK, 2210 }; 2211 static const unsigned int msiof1_clk_f_pins[] = { 2212 /* SCK */ 2213 RCAR_GP_PIN(5, 23), 2214 }; 2215 static const unsigned int msiof1_clk_f_mux[] = { 2216 MSIOF1_SCK_F_MARK, 2217 }; 2218 static const unsigned int msiof1_sync_f_pins[] = { 2219 /* SYNC */ 2220 RCAR_GP_PIN(5, 24), 2221 }; 2222 static const unsigned int msiof1_sync_f_mux[] = { 2223 MSIOF1_SYNC_F_MARK, 2224 }; 2225 static const unsigned int msiof1_ss1_f_pins[] = { 2226 /* SS1 */ 2227 RCAR_GP_PIN(6, 1), 2228 }; 2229 static const unsigned int msiof1_ss1_f_mux[] = { 2230 MSIOF1_SS1_F_MARK, 2231 }; 2232 static const unsigned int msiof1_ss2_f_pins[] = { 2233 /* SS2 */ 2234 RCAR_GP_PIN(6, 2), 2235 }; 2236 static const unsigned int msiof1_ss2_f_mux[] = { 2237 MSIOF1_SS2_F_MARK, 2238 }; 2239 static const unsigned int msiof1_txd_f_pins[] = { 2240 /* TXD */ 2241 RCAR_GP_PIN(6, 0), 2242 }; 2243 static const unsigned int msiof1_txd_f_mux[] = { 2244 MSIOF1_TXD_F_MARK, 2245 }; 2246 static const unsigned int msiof1_rxd_f_pins[] = { 2247 /* RXD */ 2248 RCAR_GP_PIN(5, 25), 2249 }; 2250 static const unsigned int msiof1_rxd_f_mux[] = { 2251 MSIOF1_RXD_F_MARK, 2252 }; 2253 static const unsigned int msiof1_clk_g_pins[] = { 2254 /* SCK */ 2255 RCAR_GP_PIN(3, 6), 2256 }; 2257 static const unsigned int msiof1_clk_g_mux[] = { 2258 MSIOF1_SCK_G_MARK, 2259 }; 2260 static const unsigned int msiof1_sync_g_pins[] = { 2261 /* SYNC */ 2262 RCAR_GP_PIN(3, 7), 2263 }; 2264 static const unsigned int msiof1_sync_g_mux[] = { 2265 MSIOF1_SYNC_G_MARK, 2266 }; 2267 static const unsigned int msiof1_ss1_g_pins[] = { 2268 /* SS1 */ 2269 RCAR_GP_PIN(3, 10), 2270 }; 2271 static const unsigned int msiof1_ss1_g_mux[] = { 2272 MSIOF1_SS1_G_MARK, 2273 }; 2274 static const unsigned int msiof1_ss2_g_pins[] = { 2275 /* SS2 */ 2276 RCAR_GP_PIN(3, 11), 2277 }; 2278 static const unsigned int msiof1_ss2_g_mux[] = { 2279 MSIOF1_SS2_G_MARK, 2280 }; 2281 static const unsigned int msiof1_txd_g_pins[] = { 2282 /* TXD */ 2283 RCAR_GP_PIN(3, 9), 2284 }; 2285 static const unsigned int msiof1_txd_g_mux[] = { 2286 MSIOF1_TXD_G_MARK, 2287 }; 2288 static const unsigned int msiof1_rxd_g_pins[] = { 2289 /* RXD */ 2290 RCAR_GP_PIN(3, 8), 2291 }; 2292 static const unsigned int msiof1_rxd_g_mux[] = { 2293 MSIOF1_RXD_G_MARK, 2294 }; 2295 /* - MSIOF2 ----------------------------------------------------------------- */ 2296 static const unsigned int msiof2_clk_a_pins[] = { 2297 /* SCK */ 2298 RCAR_GP_PIN(1, 9), 2299 }; 2300 static const unsigned int msiof2_clk_a_mux[] = { 2301 MSIOF2_SCK_A_MARK, 2302 }; 2303 static const unsigned int msiof2_sync_a_pins[] = { 2304 /* SYNC */ 2305 RCAR_GP_PIN(1, 8), 2306 }; 2307 static const unsigned int msiof2_sync_a_mux[] = { 2308 MSIOF2_SYNC_A_MARK, 2309 }; 2310 static const unsigned int msiof2_ss1_a_pins[] = { 2311 /* SS1 */ 2312 RCAR_GP_PIN(1, 6), 2313 }; 2314 static const unsigned int msiof2_ss1_a_mux[] = { 2315 MSIOF2_SS1_A_MARK, 2316 }; 2317 static const unsigned int msiof2_ss2_a_pins[] = { 2318 /* SS2 */ 2319 RCAR_GP_PIN(1, 7), 2320 }; 2321 static const unsigned int msiof2_ss2_a_mux[] = { 2322 MSIOF2_SS2_A_MARK, 2323 }; 2324 static const unsigned int msiof2_txd_a_pins[] = { 2325 /* TXD */ 2326 RCAR_GP_PIN(1, 11), 2327 }; 2328 static const unsigned int msiof2_txd_a_mux[] = { 2329 MSIOF2_TXD_A_MARK, 2330 }; 2331 static const unsigned int msiof2_rxd_a_pins[] = { 2332 /* RXD */ 2333 RCAR_GP_PIN(1, 10), 2334 }; 2335 static const unsigned int msiof2_rxd_a_mux[] = { 2336 MSIOF2_RXD_A_MARK, 2337 }; 2338 static const unsigned int msiof2_clk_b_pins[] = { 2339 /* SCK */ 2340 RCAR_GP_PIN(0, 4), 2341 }; 2342 static const unsigned int msiof2_clk_b_mux[] = { 2343 MSIOF2_SCK_B_MARK, 2344 }; 2345 static const unsigned int msiof2_sync_b_pins[] = { 2346 /* SYNC */ 2347 RCAR_GP_PIN(0, 5), 2348 }; 2349 static const unsigned int msiof2_sync_b_mux[] = { 2350 MSIOF2_SYNC_B_MARK, 2351 }; 2352 static const unsigned int msiof2_ss1_b_pins[] = { 2353 /* SS1 */ 2354 RCAR_GP_PIN(0, 0), 2355 }; 2356 static const unsigned int msiof2_ss1_b_mux[] = { 2357 MSIOF2_SS1_B_MARK, 2358 }; 2359 static const unsigned int msiof2_ss2_b_pins[] = { 2360 /* SS2 */ 2361 RCAR_GP_PIN(0, 1), 2362 }; 2363 static const unsigned int msiof2_ss2_b_mux[] = { 2364 MSIOF2_SS2_B_MARK, 2365 }; 2366 static const unsigned int msiof2_txd_b_pins[] = { 2367 /* TXD */ 2368 RCAR_GP_PIN(0, 7), 2369 }; 2370 static const unsigned int msiof2_txd_b_mux[] = { 2371 MSIOF2_TXD_B_MARK, 2372 }; 2373 static const unsigned int msiof2_rxd_b_pins[] = { 2374 /* RXD */ 2375 RCAR_GP_PIN(0, 6), 2376 }; 2377 static const unsigned int msiof2_rxd_b_mux[] = { 2378 MSIOF2_RXD_B_MARK, 2379 }; 2380 static const unsigned int msiof2_clk_c_pins[] = { 2381 /* SCK */ 2382 RCAR_GP_PIN(2, 12), 2383 }; 2384 static const unsigned int msiof2_clk_c_mux[] = { 2385 MSIOF2_SCK_C_MARK, 2386 }; 2387 static const unsigned int msiof2_sync_c_pins[] = { 2388 /* SYNC */ 2389 RCAR_GP_PIN(2, 11), 2390 }; 2391 static const unsigned int msiof2_sync_c_mux[] = { 2392 MSIOF2_SYNC_C_MARK, 2393 }; 2394 static const unsigned int msiof2_ss1_c_pins[] = { 2395 /* SS1 */ 2396 RCAR_GP_PIN(2, 10), 2397 }; 2398 static const unsigned int msiof2_ss1_c_mux[] = { 2399 MSIOF2_SS1_C_MARK, 2400 }; 2401 static const unsigned int msiof2_ss2_c_pins[] = { 2402 /* SS2 */ 2403 RCAR_GP_PIN(2, 9), 2404 }; 2405 static const unsigned int msiof2_ss2_c_mux[] = { 2406 MSIOF2_SS2_C_MARK, 2407 }; 2408 static const unsigned int msiof2_txd_c_pins[] = { 2409 /* TXD */ 2410 RCAR_GP_PIN(2, 14), 2411 }; 2412 static const unsigned int msiof2_txd_c_mux[] = { 2413 MSIOF2_TXD_C_MARK, 2414 }; 2415 static const unsigned int msiof2_rxd_c_pins[] = { 2416 /* RXD */ 2417 RCAR_GP_PIN(2, 13), 2418 }; 2419 static const unsigned int msiof2_rxd_c_mux[] = { 2420 MSIOF2_RXD_C_MARK, 2421 }; 2422 static const unsigned int msiof2_clk_d_pins[] = { 2423 /* SCK */ 2424 RCAR_GP_PIN(0, 8), 2425 }; 2426 static const unsigned int msiof2_clk_d_mux[] = { 2427 MSIOF2_SCK_D_MARK, 2428 }; 2429 static const unsigned int msiof2_sync_d_pins[] = { 2430 /* SYNC */ 2431 RCAR_GP_PIN(0, 9), 2432 }; 2433 static const unsigned int msiof2_sync_d_mux[] = { 2434 MSIOF2_SYNC_D_MARK, 2435 }; 2436 static const unsigned int msiof2_ss1_d_pins[] = { 2437 /* SS1 */ 2438 RCAR_GP_PIN(0, 12), 2439 }; 2440 static const unsigned int msiof2_ss1_d_mux[] = { 2441 MSIOF2_SS1_D_MARK, 2442 }; 2443 static const unsigned int msiof2_ss2_d_pins[] = { 2444 /* SS2 */ 2445 RCAR_GP_PIN(0, 13), 2446 }; 2447 static const unsigned int msiof2_ss2_d_mux[] = { 2448 MSIOF2_SS2_D_MARK, 2449 }; 2450 static const unsigned int msiof2_txd_d_pins[] = { 2451 /* TXD */ 2452 RCAR_GP_PIN(0, 11), 2453 }; 2454 static const unsigned int msiof2_txd_d_mux[] = { 2455 MSIOF2_TXD_D_MARK, 2456 }; 2457 static const unsigned int msiof2_rxd_d_pins[] = { 2458 /* RXD */ 2459 RCAR_GP_PIN(0, 10), 2460 }; 2461 static const unsigned int msiof2_rxd_d_mux[] = { 2462 MSIOF2_RXD_D_MARK, 2463 }; 2464 /* - MSIOF3 ----------------------------------------------------------------- */ 2465 static const unsigned int msiof3_clk_a_pins[] = { 2466 /* SCK */ 2467 RCAR_GP_PIN(0, 0), 2468 }; 2469 static const unsigned int msiof3_clk_a_mux[] = { 2470 MSIOF3_SCK_A_MARK, 2471 }; 2472 static const unsigned int msiof3_sync_a_pins[] = { 2473 /* SYNC */ 2474 RCAR_GP_PIN(0, 1), 2475 }; 2476 static const unsigned int msiof3_sync_a_mux[] = { 2477 MSIOF3_SYNC_A_MARK, 2478 }; 2479 static const unsigned int msiof3_ss1_a_pins[] = { 2480 /* SS1 */ 2481 RCAR_GP_PIN(0, 14), 2482 }; 2483 static const unsigned int msiof3_ss1_a_mux[] = { 2484 MSIOF3_SS1_A_MARK, 2485 }; 2486 static const unsigned int msiof3_ss2_a_pins[] = { 2487 /* SS2 */ 2488 RCAR_GP_PIN(0, 15), 2489 }; 2490 static const unsigned int msiof3_ss2_a_mux[] = { 2491 MSIOF3_SS2_A_MARK, 2492 }; 2493 static const unsigned int msiof3_txd_a_pins[] = { 2494 /* TXD */ 2495 RCAR_GP_PIN(0, 3), 2496 }; 2497 static const unsigned int msiof3_txd_a_mux[] = { 2498 MSIOF3_TXD_A_MARK, 2499 }; 2500 static const unsigned int msiof3_rxd_a_pins[] = { 2501 /* RXD */ 2502 RCAR_GP_PIN(0, 2), 2503 }; 2504 static const unsigned int msiof3_rxd_a_mux[] = { 2505 MSIOF3_RXD_A_MARK, 2506 }; 2507 static const unsigned int msiof3_clk_b_pins[] = { 2508 /* SCK */ 2509 RCAR_GP_PIN(1, 2), 2510 }; 2511 static const unsigned int msiof3_clk_b_mux[] = { 2512 MSIOF3_SCK_B_MARK, 2513 }; 2514 static const unsigned int msiof3_sync_b_pins[] = { 2515 /* SYNC */ 2516 RCAR_GP_PIN(1, 0), 2517 }; 2518 static const unsigned int msiof3_sync_b_mux[] = { 2519 MSIOF3_SYNC_B_MARK, 2520 }; 2521 static const unsigned int msiof3_ss1_b_pins[] = { 2522 /* SS1 */ 2523 RCAR_GP_PIN(1, 4), 2524 }; 2525 static const unsigned int msiof3_ss1_b_mux[] = { 2526 MSIOF3_SS1_B_MARK, 2527 }; 2528 static const unsigned int msiof3_ss2_b_pins[] = { 2529 /* SS2 */ 2530 RCAR_GP_PIN(1, 5), 2531 }; 2532 static const unsigned int msiof3_ss2_b_mux[] = { 2533 MSIOF3_SS2_B_MARK, 2534 }; 2535 static const unsigned int msiof3_txd_b_pins[] = { 2536 /* TXD */ 2537 RCAR_GP_PIN(1, 1), 2538 }; 2539 static const unsigned int msiof3_txd_b_mux[] = { 2540 MSIOF3_TXD_B_MARK, 2541 }; 2542 static const unsigned int msiof3_rxd_b_pins[] = { 2543 /* RXD */ 2544 RCAR_GP_PIN(1, 3), 2545 }; 2546 static const unsigned int msiof3_rxd_b_mux[] = { 2547 MSIOF3_RXD_B_MARK, 2548 }; 2549 static const unsigned int msiof3_clk_c_pins[] = { 2550 /* SCK */ 2551 RCAR_GP_PIN(1, 12), 2552 }; 2553 static const unsigned int msiof3_clk_c_mux[] = { 2554 MSIOF3_SCK_C_MARK, 2555 }; 2556 static const unsigned int msiof3_sync_c_pins[] = { 2557 /* SYNC */ 2558 RCAR_GP_PIN(1, 13), 2559 }; 2560 static const unsigned int msiof3_sync_c_mux[] = { 2561 MSIOF3_SYNC_C_MARK, 2562 }; 2563 static const unsigned int msiof3_txd_c_pins[] = { 2564 /* TXD */ 2565 RCAR_GP_PIN(1, 15), 2566 }; 2567 static const unsigned int msiof3_txd_c_mux[] = { 2568 MSIOF3_TXD_C_MARK, 2569 }; 2570 static const unsigned int msiof3_rxd_c_pins[] = { 2571 /* RXD */ 2572 RCAR_GP_PIN(1, 14), 2573 }; 2574 static const unsigned int msiof3_rxd_c_mux[] = { 2575 MSIOF3_RXD_C_MARK, 2576 }; 2577 static const unsigned int msiof3_clk_d_pins[] = { 2578 /* SCK */ 2579 RCAR_GP_PIN(1, 22), 2580 }; 2581 static const unsigned int msiof3_clk_d_mux[] = { 2582 MSIOF3_SCK_D_MARK, 2583 }; 2584 static const unsigned int msiof3_sync_d_pins[] = { 2585 /* SYNC */ 2586 RCAR_GP_PIN(1, 23), 2587 }; 2588 static const unsigned int msiof3_sync_d_mux[] = { 2589 MSIOF3_SYNC_D_MARK, 2590 }; 2591 static const unsigned int msiof3_ss1_d_pins[] = { 2592 /* SS1 */ 2593 RCAR_GP_PIN(1, 26), 2594 }; 2595 static const unsigned int msiof3_ss1_d_mux[] = { 2596 MSIOF3_SS1_D_MARK, 2597 }; 2598 static const unsigned int msiof3_txd_d_pins[] = { 2599 /* TXD */ 2600 RCAR_GP_PIN(1, 25), 2601 }; 2602 static const unsigned int msiof3_txd_d_mux[] = { 2603 MSIOF3_TXD_D_MARK, 2604 }; 2605 static const unsigned int msiof3_rxd_d_pins[] = { 2606 /* RXD */ 2607 RCAR_GP_PIN(1, 24), 2608 }; 2609 static const unsigned int msiof3_rxd_d_mux[] = { 2610 MSIOF3_RXD_D_MARK, 2611 }; 2612 static const unsigned int msiof3_clk_e_pins[] = { 2613 /* SCK */ 2614 RCAR_GP_PIN(2, 3), 2615 }; 2616 static const unsigned int msiof3_clk_e_mux[] = { 2617 MSIOF3_SCK_E_MARK, 2618 }; 2619 static const unsigned int msiof3_sync_e_pins[] = { 2620 /* SYNC */ 2621 RCAR_GP_PIN(2, 2), 2622 }; 2623 static const unsigned int msiof3_sync_e_mux[] = { 2624 MSIOF3_SYNC_E_MARK, 2625 }; 2626 static const unsigned int msiof3_ss1_e_pins[] = { 2627 /* SS1 */ 2628 RCAR_GP_PIN(2, 1), 2629 }; 2630 static const unsigned int msiof3_ss1_e_mux[] = { 2631 MSIOF3_SS1_E_MARK, 2632 }; 2633 static const unsigned int msiof3_ss2_e_pins[] = { 2634 /* SS1 */ 2635 RCAR_GP_PIN(2, 0), 2636 }; 2637 static const unsigned int msiof3_ss2_e_mux[] = { 2638 MSIOF3_SS2_E_MARK, 2639 }; 2640 static const unsigned int msiof3_txd_e_pins[] = { 2641 /* TXD */ 2642 RCAR_GP_PIN(2, 5), 2643 }; 2644 static const unsigned int msiof3_txd_e_mux[] = { 2645 MSIOF3_TXD_E_MARK, 2646 }; 2647 static const unsigned int msiof3_rxd_e_pins[] = { 2648 /* RXD */ 2649 RCAR_GP_PIN(2, 4), 2650 }; 2651 static const unsigned int msiof3_rxd_e_mux[] = { 2652 MSIOF3_RXD_E_MARK, 2653 }; 2654 2655 /* - PWM0 --------------------------------------------------------------------*/ 2656 static const unsigned int pwm0_pins[] = { 2657 /* PWM */ 2658 RCAR_GP_PIN(2, 6), 2659 }; 2660 static const unsigned int pwm0_mux[] = { 2661 PWM0_MARK, 2662 }; 2663 /* - PWM1 --------------------------------------------------------------------*/ 2664 static const unsigned int pwm1_a_pins[] = { 2665 /* PWM */ 2666 RCAR_GP_PIN(2, 7), 2667 }; 2668 static const unsigned int pwm1_a_mux[] = { 2669 PWM1_A_MARK, 2670 }; 2671 static const unsigned int pwm1_b_pins[] = { 2672 /* PWM */ 2673 RCAR_GP_PIN(1, 8), 2674 }; 2675 static const unsigned int pwm1_b_mux[] = { 2676 PWM1_B_MARK, 2677 }; 2678 /* - PWM2 --------------------------------------------------------------------*/ 2679 static const unsigned int pwm2_a_pins[] = { 2680 /* PWM */ 2681 RCAR_GP_PIN(2, 8), 2682 }; 2683 static const unsigned int pwm2_a_mux[] = { 2684 PWM2_A_MARK, 2685 }; 2686 static const unsigned int pwm2_b_pins[] = { 2687 /* PWM */ 2688 RCAR_GP_PIN(1, 11), 2689 }; 2690 static const unsigned int pwm2_b_mux[] = { 2691 PWM2_B_MARK, 2692 }; 2693 /* - PWM3 --------------------------------------------------------------------*/ 2694 static const unsigned int pwm3_a_pins[] = { 2695 /* PWM */ 2696 RCAR_GP_PIN(1, 0), 2697 }; 2698 static const unsigned int pwm3_a_mux[] = { 2699 PWM3_A_MARK, 2700 }; 2701 static const unsigned int pwm3_b_pins[] = { 2702 /* PWM */ 2703 RCAR_GP_PIN(2, 2), 2704 }; 2705 static const unsigned int pwm3_b_mux[] = { 2706 PWM3_B_MARK, 2707 }; 2708 /* - PWM4 --------------------------------------------------------------------*/ 2709 static const unsigned int pwm4_a_pins[] = { 2710 /* PWM */ 2711 RCAR_GP_PIN(1, 1), 2712 }; 2713 static const unsigned int pwm4_a_mux[] = { 2714 PWM4_A_MARK, 2715 }; 2716 static const unsigned int pwm4_b_pins[] = { 2717 /* PWM */ 2718 RCAR_GP_PIN(2, 3), 2719 }; 2720 static const unsigned int pwm4_b_mux[] = { 2721 PWM4_B_MARK, 2722 }; 2723 /* - PWM5 --------------------------------------------------------------------*/ 2724 static const unsigned int pwm5_a_pins[] = { 2725 /* PWM */ 2726 RCAR_GP_PIN(1, 2), 2727 }; 2728 static const unsigned int pwm5_a_mux[] = { 2729 PWM5_A_MARK, 2730 }; 2731 static const unsigned int pwm5_b_pins[] = { 2732 /* PWM */ 2733 RCAR_GP_PIN(2, 4), 2734 }; 2735 static const unsigned int pwm5_b_mux[] = { 2736 PWM5_B_MARK, 2737 }; 2738 /* - PWM6 --------------------------------------------------------------------*/ 2739 static const unsigned int pwm6_a_pins[] = { 2740 /* PWM */ 2741 RCAR_GP_PIN(1, 3), 2742 }; 2743 static const unsigned int pwm6_a_mux[] = { 2744 PWM6_A_MARK, 2745 }; 2746 static const unsigned int pwm6_b_pins[] = { 2747 /* PWM */ 2748 RCAR_GP_PIN(2, 5), 2749 }; 2750 static const unsigned int pwm6_b_mux[] = { 2751 PWM6_B_MARK, 2752 }; 2753 2754 /* - SCIF0 ------------------------------------------------------------------ */ 2755 static const unsigned int scif0_data_pins[] = { 2756 /* RX, TX */ 2757 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2758 }; 2759 static const unsigned int scif0_data_mux[] = { 2760 RX0_MARK, TX0_MARK, 2761 }; 2762 static const unsigned int scif0_clk_pins[] = { 2763 /* SCK */ 2764 RCAR_GP_PIN(5, 0), 2765 }; 2766 static const unsigned int scif0_clk_mux[] = { 2767 SCK0_MARK, 2768 }; 2769 static const unsigned int scif0_ctrl_pins[] = { 2770 /* RTS, CTS */ 2771 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2772 }; 2773 static const unsigned int scif0_ctrl_mux[] = { 2774 RTS0_N_TANS_MARK, CTS0_N_MARK, 2775 }; 2776 /* - SCIF1 ------------------------------------------------------------------ */ 2777 static const unsigned int scif1_data_a_pins[] = { 2778 /* RX, TX */ 2779 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2780 }; 2781 static const unsigned int scif1_data_a_mux[] = { 2782 RX1_A_MARK, TX1_A_MARK, 2783 }; 2784 static const unsigned int scif1_clk_pins[] = { 2785 /* SCK */ 2786 RCAR_GP_PIN(6, 21), 2787 }; 2788 static const unsigned int scif1_clk_mux[] = { 2789 SCK1_MARK, 2790 }; 2791 static const unsigned int scif1_ctrl_pins[] = { 2792 /* RTS, CTS */ 2793 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2794 }; 2795 static const unsigned int scif1_ctrl_mux[] = { 2796 RTS1_N_TANS_MARK, CTS1_N_MARK, 2797 }; 2798 2799 static const unsigned int scif1_data_b_pins[] = { 2800 /* RX, TX */ 2801 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 2802 }; 2803 static const unsigned int scif1_data_b_mux[] = { 2804 RX1_B_MARK, TX1_B_MARK, 2805 }; 2806 /* - SCIF2 ------------------------------------------------------------------ */ 2807 static const unsigned int scif2_data_a_pins[] = { 2808 /* RX, TX */ 2809 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2810 }; 2811 static const unsigned int scif2_data_a_mux[] = { 2812 RX2_A_MARK, TX2_A_MARK, 2813 }; 2814 static const unsigned int scif2_clk_pins[] = { 2815 /* SCK */ 2816 RCAR_GP_PIN(5, 9), 2817 }; 2818 static const unsigned int scif2_clk_mux[] = { 2819 SCK2_MARK, 2820 }; 2821 static const unsigned int scif2_data_b_pins[] = { 2822 /* RX, TX */ 2823 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2824 }; 2825 static const unsigned int scif2_data_b_mux[] = { 2826 RX2_B_MARK, TX2_B_MARK, 2827 }; 2828 /* - SCIF3 ------------------------------------------------------------------ */ 2829 static const unsigned int scif3_data_a_pins[] = { 2830 /* RX, TX */ 2831 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2832 }; 2833 static const unsigned int scif3_data_a_mux[] = { 2834 RX3_A_MARK, TX3_A_MARK, 2835 }; 2836 static const unsigned int scif3_clk_pins[] = { 2837 /* SCK */ 2838 RCAR_GP_PIN(1, 22), 2839 }; 2840 static const unsigned int scif3_clk_mux[] = { 2841 SCK3_MARK, 2842 }; 2843 static const unsigned int scif3_ctrl_pins[] = { 2844 /* RTS, CTS */ 2845 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2846 }; 2847 static const unsigned int scif3_ctrl_mux[] = { 2848 RTS3_N_TANS_MARK, CTS3_N_MARK, 2849 }; 2850 static const unsigned int scif3_data_b_pins[] = { 2851 /* RX, TX */ 2852 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2853 }; 2854 static const unsigned int scif3_data_b_mux[] = { 2855 RX3_B_MARK, TX3_B_MARK, 2856 }; 2857 /* - SCIF4 ------------------------------------------------------------------ */ 2858 static const unsigned int scif4_data_a_pins[] = { 2859 /* RX, TX */ 2860 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 2861 }; 2862 static const unsigned int scif4_data_a_mux[] = { 2863 RX4_A_MARK, TX4_A_MARK, 2864 }; 2865 static const unsigned int scif4_clk_a_pins[] = { 2866 /* SCK */ 2867 RCAR_GP_PIN(2, 10), 2868 }; 2869 static const unsigned int scif4_clk_a_mux[] = { 2870 SCK4_A_MARK, 2871 }; 2872 static const unsigned int scif4_ctrl_a_pins[] = { 2873 /* RTS, CTS */ 2874 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 2875 }; 2876 static const unsigned int scif4_ctrl_a_mux[] = { 2877 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, 2878 }; 2879 static const unsigned int scif4_data_b_pins[] = { 2880 /* RX, TX */ 2881 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 2882 }; 2883 static const unsigned int scif4_data_b_mux[] = { 2884 RX4_B_MARK, TX4_B_MARK, 2885 }; 2886 static const unsigned int scif4_clk_b_pins[] = { 2887 /* SCK */ 2888 RCAR_GP_PIN(1, 5), 2889 }; 2890 static const unsigned int scif4_clk_b_mux[] = { 2891 SCK4_B_MARK, 2892 }; 2893 static const unsigned int scif4_ctrl_b_pins[] = { 2894 /* RTS, CTS */ 2895 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 2896 }; 2897 static const unsigned int scif4_ctrl_b_mux[] = { 2898 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, 2899 }; 2900 static const unsigned int scif4_data_c_pins[] = { 2901 /* RX, TX */ 2902 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 2903 }; 2904 static const unsigned int scif4_data_c_mux[] = { 2905 RX4_C_MARK, TX4_C_MARK, 2906 }; 2907 static const unsigned int scif4_clk_c_pins[] = { 2908 /* SCK */ 2909 RCAR_GP_PIN(0, 8), 2910 }; 2911 static const unsigned int scif4_clk_c_mux[] = { 2912 SCK4_C_MARK, 2913 }; 2914 static const unsigned int scif4_ctrl_c_pins[] = { 2915 /* RTS, CTS */ 2916 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2917 }; 2918 static const unsigned int scif4_ctrl_c_mux[] = { 2919 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, 2920 }; 2921 /* - SCIF5 ------------------------------------------------------------------ */ 2922 static const unsigned int scif5_data_a_pins[] = { 2923 /* RX, TX */ 2924 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 2925 }; 2926 static const unsigned int scif5_data_a_mux[] = { 2927 RX5_A_MARK, TX5_A_MARK, 2928 }; 2929 static const unsigned int scif5_clk_a_pins[] = { 2930 /* SCK */ 2931 RCAR_GP_PIN(6, 21), 2932 }; 2933 static const unsigned int scif5_clk_a_mux[] = { 2934 SCK5_A_MARK, 2935 }; 2936 static const unsigned int scif5_data_b_pins[] = { 2937 /* RX, TX */ 2938 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 2939 }; 2940 static const unsigned int scif5_data_b_mux[] = { 2941 RX5_B_MARK, TX5_B_MARK, 2942 }; 2943 static const unsigned int scif5_clk_b_pins[] = { 2944 /* SCK */ 2945 RCAR_GP_PIN(5, 0), 2946 }; 2947 static const unsigned int scif5_clk_b_mux[] = { 2948 SCK5_B_MARK, 2949 }; 2950 2951 /* - SDHI0 ------------------------------------------------------------------ */ 2952 static const unsigned int sdhi0_data1_pins[] = { 2953 /* D0 */ 2954 RCAR_GP_PIN(3, 2), 2955 }; 2956 static const unsigned int sdhi0_data1_mux[] = { 2957 SD0_DAT0_MARK, 2958 }; 2959 static const unsigned int sdhi0_data4_pins[] = { 2960 /* D[0:3] */ 2961 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 2962 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 2963 }; 2964 static const unsigned int sdhi0_data4_mux[] = { 2965 SD0_DAT0_MARK, SD0_DAT1_MARK, 2966 SD0_DAT2_MARK, SD0_DAT3_MARK, 2967 }; 2968 static const unsigned int sdhi0_ctrl_pins[] = { 2969 /* CLK, CMD */ 2970 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 2971 }; 2972 static const unsigned int sdhi0_ctrl_mux[] = { 2973 SD0_CLK_MARK, SD0_CMD_MARK, 2974 }; 2975 static const unsigned int sdhi0_cd_pins[] = { 2976 /* CD */ 2977 RCAR_GP_PIN(3, 12), 2978 }; 2979 static const unsigned int sdhi0_cd_mux[] = { 2980 SD0_CD_MARK, 2981 }; 2982 static const unsigned int sdhi0_wp_pins[] = { 2983 /* WP */ 2984 RCAR_GP_PIN(3, 13), 2985 }; 2986 static const unsigned int sdhi0_wp_mux[] = { 2987 SD0_WP_MARK, 2988 }; 2989 /* - SDHI1 ------------------------------------------------------------------ */ 2990 static const unsigned int sdhi1_data1_pins[] = { 2991 /* D0 */ 2992 RCAR_GP_PIN(3, 8), 2993 }; 2994 static const unsigned int sdhi1_data1_mux[] = { 2995 SD1_DAT0_MARK, 2996 }; 2997 static const unsigned int sdhi1_data4_pins[] = { 2998 /* D[0:3] */ 2999 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3000 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3001 }; 3002 static const unsigned int sdhi1_data4_mux[] = { 3003 SD1_DAT0_MARK, SD1_DAT1_MARK, 3004 SD1_DAT2_MARK, SD1_DAT3_MARK, 3005 }; 3006 static const unsigned int sdhi1_ctrl_pins[] = { 3007 /* CLK, CMD */ 3008 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3009 }; 3010 static const unsigned int sdhi1_ctrl_mux[] = { 3011 SD1_CLK_MARK, SD1_CMD_MARK, 3012 }; 3013 static const unsigned int sdhi1_cd_pins[] = { 3014 /* CD */ 3015 RCAR_GP_PIN(3, 14), 3016 }; 3017 static const unsigned int sdhi1_cd_mux[] = { 3018 SD1_CD_MARK, 3019 }; 3020 static const unsigned int sdhi1_wp_pins[] = { 3021 /* WP */ 3022 RCAR_GP_PIN(3, 15), 3023 }; 3024 static const unsigned int sdhi1_wp_mux[] = { 3025 SD1_WP_MARK, 3026 }; 3027 /* - SDHI2 ------------------------------------------------------------------ */ 3028 static const unsigned int sdhi2_data1_pins[] = { 3029 /* D0 */ 3030 RCAR_GP_PIN(4, 2), 3031 }; 3032 static const unsigned int sdhi2_data1_mux[] = { 3033 SD2_DAT0_MARK, 3034 }; 3035 static const unsigned int sdhi2_data4_pins[] = { 3036 /* D[0:3] */ 3037 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3038 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3039 }; 3040 static const unsigned int sdhi2_data4_mux[] = { 3041 SD2_DAT0_MARK, SD2_DAT1_MARK, 3042 SD2_DAT2_MARK, SD2_DAT3_MARK, 3043 }; 3044 static const unsigned int sdhi2_data8_pins[] = { 3045 /* D[0:7] */ 3046 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3047 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3048 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3049 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3050 }; 3051 static const unsigned int sdhi2_data8_mux[] = { 3052 SD2_DAT0_MARK, SD2_DAT1_MARK, 3053 SD2_DAT2_MARK, SD2_DAT3_MARK, 3054 SD2_DAT4_MARK, SD2_DAT5_MARK, 3055 SD2_DAT6_MARK, SD2_DAT7_MARK, 3056 }; 3057 static const unsigned int sdhi2_ctrl_pins[] = { 3058 /* CLK, CMD */ 3059 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3060 }; 3061 static const unsigned int sdhi2_ctrl_mux[] = { 3062 SD2_CLK_MARK, SD2_CMD_MARK, 3063 }; 3064 static const unsigned int sdhi2_cd_a_pins[] = { 3065 /* CD */ 3066 RCAR_GP_PIN(4, 13), 3067 }; 3068 static const unsigned int sdhi2_cd_a_mux[] = { 3069 SD2_CD_A_MARK, 3070 }; 3071 static const unsigned int sdhi2_cd_b_pins[] = { 3072 /* CD */ 3073 RCAR_GP_PIN(5, 10), 3074 }; 3075 static const unsigned int sdhi2_cd_b_mux[] = { 3076 SD2_CD_B_MARK, 3077 }; 3078 static const unsigned int sdhi2_wp_a_pins[] = { 3079 /* WP */ 3080 RCAR_GP_PIN(4, 14), 3081 }; 3082 static const unsigned int sdhi2_wp_a_mux[] = { 3083 SD2_WP_A_MARK, 3084 }; 3085 static const unsigned int sdhi2_wp_b_pins[] = { 3086 /* WP */ 3087 RCAR_GP_PIN(5, 11), 3088 }; 3089 static const unsigned int sdhi2_wp_b_mux[] = { 3090 SD2_WP_B_MARK, 3091 }; 3092 static const unsigned int sdhi2_ds_pins[] = { 3093 /* DS */ 3094 RCAR_GP_PIN(4, 6), 3095 }; 3096 static const unsigned int sdhi2_ds_mux[] = { 3097 SD2_DS_MARK, 3098 }; 3099 /* - SDHI3 ------------------------------------------------------------------ */ 3100 static const unsigned int sdhi3_data1_pins[] = { 3101 /* D0 */ 3102 RCAR_GP_PIN(4, 9), 3103 }; 3104 static const unsigned int sdhi3_data1_mux[] = { 3105 SD3_DAT0_MARK, 3106 }; 3107 static const unsigned int sdhi3_data4_pins[] = { 3108 /* D[0:3] */ 3109 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3110 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3111 }; 3112 static const unsigned int sdhi3_data4_mux[] = { 3113 SD3_DAT0_MARK, SD3_DAT1_MARK, 3114 SD3_DAT2_MARK, SD3_DAT3_MARK, 3115 }; 3116 static const unsigned int sdhi3_data8_pins[] = { 3117 /* D[0:7] */ 3118 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3119 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3120 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3121 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3122 }; 3123 static const unsigned int sdhi3_data8_mux[] = { 3124 SD3_DAT0_MARK, SD3_DAT1_MARK, 3125 SD3_DAT2_MARK, SD3_DAT3_MARK, 3126 SD3_DAT4_MARK, SD3_DAT5_MARK, 3127 SD3_DAT6_MARK, SD3_DAT7_MARK, 3128 }; 3129 static const unsigned int sdhi3_ctrl_pins[] = { 3130 /* CLK, CMD */ 3131 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3132 }; 3133 static const unsigned int sdhi3_ctrl_mux[] = { 3134 SD3_CLK_MARK, SD3_CMD_MARK, 3135 }; 3136 static const unsigned int sdhi3_cd_pins[] = { 3137 /* CD */ 3138 RCAR_GP_PIN(4, 15), 3139 }; 3140 static const unsigned int sdhi3_cd_mux[] = { 3141 SD3_CD_MARK, 3142 }; 3143 static const unsigned int sdhi3_wp_pins[] = { 3144 /* WP */ 3145 RCAR_GP_PIN(4, 16), 3146 }; 3147 static const unsigned int sdhi3_wp_mux[] = { 3148 SD3_WP_MARK, 3149 }; 3150 static const unsigned int sdhi3_ds_pins[] = { 3151 /* DS */ 3152 RCAR_GP_PIN(4, 17), 3153 }; 3154 static const unsigned int sdhi3_ds_mux[] = { 3155 SD3_DS_MARK, 3156 }; 3157 3158 /* - SCIF Clock ------------------------------------------------------------- */ 3159 static const unsigned int scif_clk_a_pins[] = { 3160 /* SCIF_CLK */ 3161 RCAR_GP_PIN(6, 23), 3162 }; 3163 static const unsigned int scif_clk_a_mux[] = { 3164 SCIF_CLK_A_MARK, 3165 }; 3166 static const unsigned int scif_clk_b_pins[] = { 3167 /* SCIF_CLK */ 3168 RCAR_GP_PIN(5, 9), 3169 }; 3170 static const unsigned int scif_clk_b_mux[] = { 3171 SCIF_CLK_B_MARK, 3172 }; 3173 3174 /* - USB0 ------------------------------------------------------------------- */ 3175 static const unsigned int usb0_pins[] = { 3176 /* PWEN, OVC */ 3177 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 3178 }; 3179 static const unsigned int usb0_mux[] = { 3180 USB0_PWEN_MARK, USB0_OVC_MARK, 3181 }; 3182 /* - USB1 ------------------------------------------------------------------- */ 3183 static const unsigned int usb1_pins[] = { 3184 /* PWEN, OVC */ 3185 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3186 }; 3187 static const unsigned int usb1_mux[] = { 3188 USB1_PWEN_MARK, USB1_OVC_MARK, 3189 }; 3190 /* - USB2 ------------------------------------------------------------------- */ 3191 static const unsigned int usb2_pins[] = { 3192 /* PWEN, OVC */ 3193 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3194 }; 3195 static const unsigned int usb2_mux[] = { 3196 USB2_PWEN_MARK, USB2_OVC_MARK, 3197 }; 3198 /* - USB2_CH3 --------------------------------------------------------------- */ 3199 static const unsigned int usb2_ch3_pins[] = { 3200 /* PWEN, OVC */ 3201 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 3202 }; 3203 static const unsigned int usb2_ch3_mux[] = { 3204 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK, 3205 }; 3206 3207 static const struct sh_pfc_pin_group pinmux_groups[] = { 3208 SH_PFC_PIN_GROUP(avb_link), 3209 SH_PFC_PIN_GROUP(avb_magic), 3210 SH_PFC_PIN_GROUP(avb_phy_int), 3211 SH_PFC_PIN_GROUP(avb_mdc), 3212 SH_PFC_PIN_GROUP(avb_mii), 3213 SH_PFC_PIN_GROUP(avb_avtp_pps), 3214 SH_PFC_PIN_GROUP(avb_avtp_match_a), 3215 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 3216 SH_PFC_PIN_GROUP(avb_avtp_match_b), 3217 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 3218 SH_PFC_PIN_GROUP(drif0_ctrl_a), 3219 SH_PFC_PIN_GROUP(drif0_data0_a), 3220 SH_PFC_PIN_GROUP(drif0_data1_a), 3221 SH_PFC_PIN_GROUP(drif0_ctrl_b), 3222 SH_PFC_PIN_GROUP(drif0_data0_b), 3223 SH_PFC_PIN_GROUP(drif0_data1_b), 3224 SH_PFC_PIN_GROUP(drif0_ctrl_c), 3225 SH_PFC_PIN_GROUP(drif0_data0_c), 3226 SH_PFC_PIN_GROUP(drif0_data1_c), 3227 SH_PFC_PIN_GROUP(drif1_ctrl_a), 3228 SH_PFC_PIN_GROUP(drif1_data0_a), 3229 SH_PFC_PIN_GROUP(drif1_data1_a), 3230 SH_PFC_PIN_GROUP(drif1_ctrl_b), 3231 SH_PFC_PIN_GROUP(drif1_data0_b), 3232 SH_PFC_PIN_GROUP(drif1_data1_b), 3233 SH_PFC_PIN_GROUP(drif1_ctrl_c), 3234 SH_PFC_PIN_GROUP(drif1_data0_c), 3235 SH_PFC_PIN_GROUP(drif1_data1_c), 3236 SH_PFC_PIN_GROUP(drif2_ctrl_a), 3237 SH_PFC_PIN_GROUP(drif2_data0_a), 3238 SH_PFC_PIN_GROUP(drif2_data1_a), 3239 SH_PFC_PIN_GROUP(drif2_ctrl_b), 3240 SH_PFC_PIN_GROUP(drif2_data0_b), 3241 SH_PFC_PIN_GROUP(drif2_data1_b), 3242 SH_PFC_PIN_GROUP(drif3_ctrl_a), 3243 SH_PFC_PIN_GROUP(drif3_data0_a), 3244 SH_PFC_PIN_GROUP(drif3_data1_a), 3245 SH_PFC_PIN_GROUP(drif3_ctrl_b), 3246 SH_PFC_PIN_GROUP(drif3_data0_b), 3247 SH_PFC_PIN_GROUP(drif3_data1_b), 3248 SH_PFC_PIN_GROUP(du_rgb666), 3249 SH_PFC_PIN_GROUP(du_rgb888), 3250 SH_PFC_PIN_GROUP(du_clk_out_0), 3251 SH_PFC_PIN_GROUP(du_clk_out_1), 3252 SH_PFC_PIN_GROUP(du_sync), 3253 SH_PFC_PIN_GROUP(du_oddf), 3254 SH_PFC_PIN_GROUP(du_cde), 3255 SH_PFC_PIN_GROUP(du_disp), 3256 SH_PFC_PIN_GROUP(msiof0_clk), 3257 SH_PFC_PIN_GROUP(msiof0_sync), 3258 SH_PFC_PIN_GROUP(msiof0_ss1), 3259 SH_PFC_PIN_GROUP(msiof0_ss2), 3260 SH_PFC_PIN_GROUP(msiof0_txd), 3261 SH_PFC_PIN_GROUP(msiof0_rxd), 3262 SH_PFC_PIN_GROUP(msiof1_clk_a), 3263 SH_PFC_PIN_GROUP(msiof1_sync_a), 3264 SH_PFC_PIN_GROUP(msiof1_ss1_a), 3265 SH_PFC_PIN_GROUP(msiof1_ss2_a), 3266 SH_PFC_PIN_GROUP(msiof1_txd_a), 3267 SH_PFC_PIN_GROUP(msiof1_rxd_a), 3268 SH_PFC_PIN_GROUP(msiof1_clk_b), 3269 SH_PFC_PIN_GROUP(msiof1_sync_b), 3270 SH_PFC_PIN_GROUP(msiof1_ss1_b), 3271 SH_PFC_PIN_GROUP(msiof1_ss2_b), 3272 SH_PFC_PIN_GROUP(msiof1_txd_b), 3273 SH_PFC_PIN_GROUP(msiof1_rxd_b), 3274 SH_PFC_PIN_GROUP(msiof1_clk_c), 3275 SH_PFC_PIN_GROUP(msiof1_sync_c), 3276 SH_PFC_PIN_GROUP(msiof1_ss1_c), 3277 SH_PFC_PIN_GROUP(msiof1_ss2_c), 3278 SH_PFC_PIN_GROUP(msiof1_txd_c), 3279 SH_PFC_PIN_GROUP(msiof1_rxd_c), 3280 SH_PFC_PIN_GROUP(msiof1_clk_d), 3281 SH_PFC_PIN_GROUP(msiof1_sync_d), 3282 SH_PFC_PIN_GROUP(msiof1_ss1_d), 3283 SH_PFC_PIN_GROUP(msiof1_ss2_d), 3284 SH_PFC_PIN_GROUP(msiof1_txd_d), 3285 SH_PFC_PIN_GROUP(msiof1_rxd_d), 3286 SH_PFC_PIN_GROUP(msiof1_clk_e), 3287 SH_PFC_PIN_GROUP(msiof1_sync_e), 3288 SH_PFC_PIN_GROUP(msiof1_ss1_e), 3289 SH_PFC_PIN_GROUP(msiof1_ss2_e), 3290 SH_PFC_PIN_GROUP(msiof1_txd_e), 3291 SH_PFC_PIN_GROUP(msiof1_rxd_e), 3292 SH_PFC_PIN_GROUP(msiof1_clk_f), 3293 SH_PFC_PIN_GROUP(msiof1_sync_f), 3294 SH_PFC_PIN_GROUP(msiof1_ss1_f), 3295 SH_PFC_PIN_GROUP(msiof1_ss2_f), 3296 SH_PFC_PIN_GROUP(msiof1_txd_f), 3297 SH_PFC_PIN_GROUP(msiof1_rxd_f), 3298 SH_PFC_PIN_GROUP(msiof1_clk_g), 3299 SH_PFC_PIN_GROUP(msiof1_sync_g), 3300 SH_PFC_PIN_GROUP(msiof1_ss1_g), 3301 SH_PFC_PIN_GROUP(msiof1_ss2_g), 3302 SH_PFC_PIN_GROUP(msiof1_txd_g), 3303 SH_PFC_PIN_GROUP(msiof1_rxd_g), 3304 SH_PFC_PIN_GROUP(msiof2_clk_a), 3305 SH_PFC_PIN_GROUP(msiof2_sync_a), 3306 SH_PFC_PIN_GROUP(msiof2_ss1_a), 3307 SH_PFC_PIN_GROUP(msiof2_ss2_a), 3308 SH_PFC_PIN_GROUP(msiof2_txd_a), 3309 SH_PFC_PIN_GROUP(msiof2_rxd_a), 3310 SH_PFC_PIN_GROUP(msiof2_clk_b), 3311 SH_PFC_PIN_GROUP(msiof2_sync_b), 3312 SH_PFC_PIN_GROUP(msiof2_ss1_b), 3313 SH_PFC_PIN_GROUP(msiof2_ss2_b), 3314 SH_PFC_PIN_GROUP(msiof2_txd_b), 3315 SH_PFC_PIN_GROUP(msiof2_rxd_b), 3316 SH_PFC_PIN_GROUP(msiof2_clk_c), 3317 SH_PFC_PIN_GROUP(msiof2_sync_c), 3318 SH_PFC_PIN_GROUP(msiof2_ss1_c), 3319 SH_PFC_PIN_GROUP(msiof2_ss2_c), 3320 SH_PFC_PIN_GROUP(msiof2_txd_c), 3321 SH_PFC_PIN_GROUP(msiof2_rxd_c), 3322 SH_PFC_PIN_GROUP(msiof2_clk_d), 3323 SH_PFC_PIN_GROUP(msiof2_sync_d), 3324 SH_PFC_PIN_GROUP(msiof2_ss1_d), 3325 SH_PFC_PIN_GROUP(msiof2_ss2_d), 3326 SH_PFC_PIN_GROUP(msiof2_txd_d), 3327 SH_PFC_PIN_GROUP(msiof2_rxd_d), 3328 SH_PFC_PIN_GROUP(msiof3_clk_a), 3329 SH_PFC_PIN_GROUP(msiof3_sync_a), 3330 SH_PFC_PIN_GROUP(msiof3_ss1_a), 3331 SH_PFC_PIN_GROUP(msiof3_ss2_a), 3332 SH_PFC_PIN_GROUP(msiof3_txd_a), 3333 SH_PFC_PIN_GROUP(msiof3_rxd_a), 3334 SH_PFC_PIN_GROUP(msiof3_clk_b), 3335 SH_PFC_PIN_GROUP(msiof3_sync_b), 3336 SH_PFC_PIN_GROUP(msiof3_ss1_b), 3337 SH_PFC_PIN_GROUP(msiof3_ss2_b), 3338 SH_PFC_PIN_GROUP(msiof3_txd_b), 3339 SH_PFC_PIN_GROUP(msiof3_rxd_b), 3340 SH_PFC_PIN_GROUP(msiof3_clk_c), 3341 SH_PFC_PIN_GROUP(msiof3_sync_c), 3342 SH_PFC_PIN_GROUP(msiof3_txd_c), 3343 SH_PFC_PIN_GROUP(msiof3_rxd_c), 3344 SH_PFC_PIN_GROUP(msiof3_clk_d), 3345 SH_PFC_PIN_GROUP(msiof3_sync_d), 3346 SH_PFC_PIN_GROUP(msiof3_ss1_d), 3347 SH_PFC_PIN_GROUP(msiof3_txd_d), 3348 SH_PFC_PIN_GROUP(msiof3_rxd_d), 3349 SH_PFC_PIN_GROUP(msiof3_clk_e), 3350 SH_PFC_PIN_GROUP(msiof3_sync_e), 3351 SH_PFC_PIN_GROUP(msiof3_ss1_e), 3352 SH_PFC_PIN_GROUP(msiof3_ss2_e), 3353 SH_PFC_PIN_GROUP(msiof3_txd_e), 3354 SH_PFC_PIN_GROUP(msiof3_rxd_e), 3355 SH_PFC_PIN_GROUP(pwm0), 3356 SH_PFC_PIN_GROUP(pwm1_a), 3357 SH_PFC_PIN_GROUP(pwm1_b), 3358 SH_PFC_PIN_GROUP(pwm2_a), 3359 SH_PFC_PIN_GROUP(pwm2_b), 3360 SH_PFC_PIN_GROUP(pwm3_a), 3361 SH_PFC_PIN_GROUP(pwm3_b), 3362 SH_PFC_PIN_GROUP(pwm4_a), 3363 SH_PFC_PIN_GROUP(pwm4_b), 3364 SH_PFC_PIN_GROUP(pwm5_a), 3365 SH_PFC_PIN_GROUP(pwm5_b), 3366 SH_PFC_PIN_GROUP(pwm6_a), 3367 SH_PFC_PIN_GROUP(pwm6_b), 3368 SH_PFC_PIN_GROUP(scif0_data), 3369 SH_PFC_PIN_GROUP(scif0_clk), 3370 SH_PFC_PIN_GROUP(scif0_ctrl), 3371 SH_PFC_PIN_GROUP(scif1_data_a), 3372 SH_PFC_PIN_GROUP(scif1_clk), 3373 SH_PFC_PIN_GROUP(scif1_ctrl), 3374 SH_PFC_PIN_GROUP(scif1_data_b), 3375 SH_PFC_PIN_GROUP(scif2_data_a), 3376 SH_PFC_PIN_GROUP(scif2_clk), 3377 SH_PFC_PIN_GROUP(scif2_data_b), 3378 SH_PFC_PIN_GROUP(scif3_data_a), 3379 SH_PFC_PIN_GROUP(scif3_clk), 3380 SH_PFC_PIN_GROUP(scif3_ctrl), 3381 SH_PFC_PIN_GROUP(scif3_data_b), 3382 SH_PFC_PIN_GROUP(scif4_data_a), 3383 SH_PFC_PIN_GROUP(scif4_clk_a), 3384 SH_PFC_PIN_GROUP(scif4_ctrl_a), 3385 SH_PFC_PIN_GROUP(scif4_data_b), 3386 SH_PFC_PIN_GROUP(scif4_clk_b), 3387 SH_PFC_PIN_GROUP(scif4_ctrl_b), 3388 SH_PFC_PIN_GROUP(scif4_data_c), 3389 SH_PFC_PIN_GROUP(scif4_clk_c), 3390 SH_PFC_PIN_GROUP(scif4_ctrl_c), 3391 SH_PFC_PIN_GROUP(scif5_data_a), 3392 SH_PFC_PIN_GROUP(scif5_clk_a), 3393 SH_PFC_PIN_GROUP(scif5_data_b), 3394 SH_PFC_PIN_GROUP(scif5_clk_b), 3395 SH_PFC_PIN_GROUP(scif_clk_a), 3396 SH_PFC_PIN_GROUP(scif_clk_b), 3397 SH_PFC_PIN_GROUP(sdhi0_data1), 3398 SH_PFC_PIN_GROUP(sdhi0_data4), 3399 SH_PFC_PIN_GROUP(sdhi0_ctrl), 3400 SH_PFC_PIN_GROUP(sdhi0_cd), 3401 SH_PFC_PIN_GROUP(sdhi0_wp), 3402 SH_PFC_PIN_GROUP(sdhi1_data1), 3403 SH_PFC_PIN_GROUP(sdhi1_data4), 3404 SH_PFC_PIN_GROUP(sdhi1_ctrl), 3405 SH_PFC_PIN_GROUP(sdhi1_cd), 3406 SH_PFC_PIN_GROUP(sdhi1_wp), 3407 SH_PFC_PIN_GROUP(sdhi2_data1), 3408 SH_PFC_PIN_GROUP(sdhi2_data4), 3409 SH_PFC_PIN_GROUP(sdhi2_data8), 3410 SH_PFC_PIN_GROUP(sdhi2_ctrl), 3411 SH_PFC_PIN_GROUP(sdhi2_cd_a), 3412 SH_PFC_PIN_GROUP(sdhi2_wp_a), 3413 SH_PFC_PIN_GROUP(sdhi2_cd_b), 3414 SH_PFC_PIN_GROUP(sdhi2_wp_b), 3415 SH_PFC_PIN_GROUP(sdhi2_ds), 3416 SH_PFC_PIN_GROUP(sdhi3_data1), 3417 SH_PFC_PIN_GROUP(sdhi3_data4), 3418 SH_PFC_PIN_GROUP(sdhi3_data8), 3419 SH_PFC_PIN_GROUP(sdhi3_ctrl), 3420 SH_PFC_PIN_GROUP(sdhi3_cd), 3421 SH_PFC_PIN_GROUP(sdhi3_wp), 3422 SH_PFC_PIN_GROUP(sdhi3_ds), 3423 SH_PFC_PIN_GROUP(usb0), 3424 SH_PFC_PIN_GROUP(usb1), 3425 SH_PFC_PIN_GROUP(usb2), 3426 SH_PFC_PIN_GROUP(usb2_ch3), 3427 }; 3428 3429 static const char * const avb_groups[] = { 3430 "avb_link", 3431 "avb_magic", 3432 "avb_phy_int", 3433 "avb_mdc", 3434 "avb_mii", 3435 "avb_avtp_pps", 3436 "avb_avtp_match_a", 3437 "avb_avtp_capture_a", 3438 "avb_avtp_match_b", 3439 "avb_avtp_capture_b", 3440 }; 3441 3442 static const char * const drif0_groups[] = { 3443 "drif0_ctrl_a", 3444 "drif0_data0_a", 3445 "drif0_data1_a", 3446 "drif0_ctrl_b", 3447 "drif0_data0_b", 3448 "drif0_data1_b", 3449 "drif0_ctrl_c", 3450 "drif0_data0_c", 3451 "drif0_data1_c", 3452 }; 3453 3454 static const char * const drif1_groups[] = { 3455 "drif1_ctrl_a", 3456 "drif1_data0_a", 3457 "drif1_data1_a", 3458 "drif1_ctrl_b", 3459 "drif1_data0_b", 3460 "drif1_data1_b", 3461 "drif1_ctrl_c", 3462 "drif1_data0_c", 3463 "drif1_data1_c", 3464 }; 3465 3466 static const char * const drif2_groups[] = { 3467 "drif2_ctrl_a", 3468 "drif2_data0_a", 3469 "drif2_data1_a", 3470 "drif2_ctrl_b", 3471 "drif2_data0_b", 3472 "drif2_data1_b", 3473 }; 3474 3475 static const char * const drif3_groups[] = { 3476 "drif3_ctrl_a", 3477 "drif3_data0_a", 3478 "drif3_data1_a", 3479 "drif3_ctrl_b", 3480 "drif3_data0_b", 3481 "drif3_data1_b", 3482 }; 3483 3484 static const char * const du_groups[] = { 3485 "du_rgb666", 3486 "du_rgb888", 3487 "du_clk_out_0", 3488 "du_clk_out_1", 3489 "du_sync", 3490 "du_oddf", 3491 "du_cde", 3492 "du_disp", 3493 }; 3494 3495 static const char * const msiof0_groups[] = { 3496 "msiof0_clk", 3497 "msiof0_sync", 3498 "msiof0_ss1", 3499 "msiof0_ss2", 3500 "msiof0_txd", 3501 "msiof0_rxd", 3502 }; 3503 3504 static const char * const msiof1_groups[] = { 3505 "msiof1_clk_a", 3506 "msiof1_sync_a", 3507 "msiof1_ss1_a", 3508 "msiof1_ss2_a", 3509 "msiof1_txd_a", 3510 "msiof1_rxd_a", 3511 "msiof1_clk_b", 3512 "msiof1_sync_b", 3513 "msiof1_ss1_b", 3514 "msiof1_ss2_b", 3515 "msiof1_txd_b", 3516 "msiof1_rxd_b", 3517 "msiof1_clk_c", 3518 "msiof1_sync_c", 3519 "msiof1_ss1_c", 3520 "msiof1_ss2_c", 3521 "msiof1_txd_c", 3522 "msiof1_rxd_c", 3523 "msiof1_clk_d", 3524 "msiof1_sync_d", 3525 "msiof1_ss1_d", 3526 "msiof1_ss2_d", 3527 "msiof1_txd_d", 3528 "msiof1_rxd_d", 3529 "msiof1_clk_e", 3530 "msiof1_sync_e", 3531 "msiof1_ss1_e", 3532 "msiof1_ss2_e", 3533 "msiof1_txd_e", 3534 "msiof1_rxd_e", 3535 "msiof1_clk_f", 3536 "msiof1_sync_f", 3537 "msiof1_ss1_f", 3538 "msiof1_ss2_f", 3539 "msiof1_txd_f", 3540 "msiof1_rxd_f", 3541 "msiof1_clk_g", 3542 "msiof1_sync_g", 3543 "msiof1_ss1_g", 3544 "msiof1_ss2_g", 3545 "msiof1_txd_g", 3546 "msiof1_rxd_g", 3547 }; 3548 3549 static const char * const msiof2_groups[] = { 3550 "msiof2_clk_a", 3551 "msiof2_sync_a", 3552 "msiof2_ss1_a", 3553 "msiof2_ss2_a", 3554 "msiof2_txd_a", 3555 "msiof2_rxd_a", 3556 "msiof2_clk_b", 3557 "msiof2_sync_b", 3558 "msiof2_ss1_b", 3559 "msiof2_ss2_b", 3560 "msiof2_txd_b", 3561 "msiof2_rxd_b", 3562 "msiof2_clk_c", 3563 "msiof2_sync_c", 3564 "msiof2_ss1_c", 3565 "msiof2_ss2_c", 3566 "msiof2_txd_c", 3567 "msiof2_rxd_c", 3568 "msiof2_clk_d", 3569 "msiof2_sync_d", 3570 "msiof2_ss1_d", 3571 "msiof2_ss2_d", 3572 "msiof2_txd_d", 3573 "msiof2_rxd_d", 3574 }; 3575 3576 static const char * const msiof3_groups[] = { 3577 "msiof3_clk_a", 3578 "msiof3_sync_a", 3579 "msiof3_ss1_a", 3580 "msiof3_ss2_a", 3581 "msiof3_txd_a", 3582 "msiof3_rxd_a", 3583 "msiof3_clk_b", 3584 "msiof3_sync_b", 3585 "msiof3_ss1_b", 3586 "msiof3_ss2_b", 3587 "msiof3_txd_b", 3588 "msiof3_rxd_b", 3589 "msiof3_clk_c", 3590 "msiof3_sync_c", 3591 "msiof3_txd_c", 3592 "msiof3_rxd_c", 3593 "msiof3_clk_d", 3594 "msiof3_sync_d", 3595 "msiof3_ss1_d", 3596 "msiof3_txd_d", 3597 "msiof3_rxd_d", 3598 "msiof3_clk_e", 3599 "msiof3_sync_e", 3600 "msiof3_ss1_e", 3601 "msiof3_ss2_e", 3602 "msiof3_txd_e", 3603 "msiof3_rxd_e", 3604 }; 3605 3606 static const char * const pwm0_groups[] = { 3607 "pwm0", 3608 }; 3609 3610 static const char * const pwm1_groups[] = { 3611 "pwm1_a", 3612 "pwm1_b", 3613 }; 3614 3615 static const char * const pwm2_groups[] = { 3616 "pwm2_a", 3617 "pwm2_b", 3618 }; 3619 3620 static const char * const pwm3_groups[] = { 3621 "pwm3_a", 3622 "pwm3_b", 3623 }; 3624 3625 static const char * const pwm4_groups[] = { 3626 "pwm4_a", 3627 "pwm4_b", 3628 }; 3629 3630 static const char * const pwm5_groups[] = { 3631 "pwm5_a", 3632 "pwm5_b", 3633 }; 3634 3635 static const char * const pwm6_groups[] = { 3636 "pwm6_a", 3637 "pwm6_b", 3638 }; 3639 3640 static const char * const scif0_groups[] = { 3641 "scif0_data", 3642 "scif0_clk", 3643 "scif0_ctrl", 3644 }; 3645 3646 static const char * const scif1_groups[] = { 3647 "scif1_data_a", 3648 "scif1_clk", 3649 "scif1_ctrl", 3650 "scif1_data_b", 3651 }; 3652 3653 static const char * const scif2_groups[] = { 3654 "scif2_data_a", 3655 "scif2_clk", 3656 "scif2_data_b", 3657 }; 3658 3659 static const char * const scif3_groups[] = { 3660 "scif3_data_a", 3661 "scif3_clk", 3662 "scif3_ctrl", 3663 "scif3_data_b", 3664 }; 3665 3666 static const char * const scif4_groups[] = { 3667 "scif4_data_a", 3668 "scif4_clk_a", 3669 "scif4_ctrl_a", 3670 "scif4_data_b", 3671 "scif4_clk_b", 3672 "scif4_ctrl_b", 3673 "scif4_data_c", 3674 "scif4_clk_c", 3675 "scif4_ctrl_c", 3676 }; 3677 3678 static const char * const scif5_groups[] = { 3679 "scif5_data_a", 3680 "scif5_clk_a", 3681 "scif5_data_b", 3682 "scif5_clk_b", 3683 }; 3684 3685 static const char * const scif_clk_groups[] = { 3686 "scif_clk_a", 3687 "scif_clk_b", 3688 }; 3689 3690 static const char * const sdhi0_groups[] = { 3691 "sdhi0_data1", 3692 "sdhi0_data4", 3693 "sdhi0_ctrl", 3694 "sdhi0_cd", 3695 "sdhi0_wp", 3696 }; 3697 3698 static const char * const sdhi1_groups[] = { 3699 "sdhi1_data1", 3700 "sdhi1_data4", 3701 "sdhi1_ctrl", 3702 "sdhi1_cd", 3703 "sdhi1_wp", 3704 }; 3705 3706 static const char * const sdhi2_groups[] = { 3707 "sdhi2_data1", 3708 "sdhi2_data4", 3709 "sdhi2_data8", 3710 "sdhi2_ctrl", 3711 "sdhi2_cd_a", 3712 "sdhi2_wp_a", 3713 "sdhi2_cd_b", 3714 "sdhi2_wp_b", 3715 "sdhi2_ds", 3716 }; 3717 3718 static const char * const sdhi3_groups[] = { 3719 "sdhi3_data1", 3720 "sdhi3_data4", 3721 "sdhi3_data8", 3722 "sdhi3_ctrl", 3723 "sdhi3_cd", 3724 "sdhi3_wp", 3725 "sdhi3_ds", 3726 }; 3727 3728 static const char * const usb0_groups[] = { 3729 "usb0", 3730 }; 3731 3732 static const char * const usb1_groups[] = { 3733 "usb1", 3734 }; 3735 3736 static const char * const usb2_groups[] = { 3737 "usb2", 3738 }; 3739 3740 static const char * const usb2_ch3_groups[] = { 3741 "usb2_ch3", 3742 }; 3743 3744 static const struct sh_pfc_function pinmux_functions[] = { 3745 SH_PFC_FUNCTION(avb), 3746 SH_PFC_FUNCTION(drif0), 3747 SH_PFC_FUNCTION(drif1), 3748 SH_PFC_FUNCTION(drif2), 3749 SH_PFC_FUNCTION(drif3), 3750 SH_PFC_FUNCTION(du), 3751 SH_PFC_FUNCTION(msiof0), 3752 SH_PFC_FUNCTION(msiof1), 3753 SH_PFC_FUNCTION(msiof2), 3754 SH_PFC_FUNCTION(msiof3), 3755 SH_PFC_FUNCTION(pwm0), 3756 SH_PFC_FUNCTION(pwm1), 3757 SH_PFC_FUNCTION(pwm2), 3758 SH_PFC_FUNCTION(pwm3), 3759 SH_PFC_FUNCTION(pwm4), 3760 SH_PFC_FUNCTION(pwm5), 3761 SH_PFC_FUNCTION(pwm6), 3762 SH_PFC_FUNCTION(scif0), 3763 SH_PFC_FUNCTION(scif1), 3764 SH_PFC_FUNCTION(scif2), 3765 SH_PFC_FUNCTION(scif3), 3766 SH_PFC_FUNCTION(scif4), 3767 SH_PFC_FUNCTION(scif5), 3768 SH_PFC_FUNCTION(scif_clk), 3769 SH_PFC_FUNCTION(sdhi0), 3770 SH_PFC_FUNCTION(sdhi1), 3771 SH_PFC_FUNCTION(sdhi2), 3772 SH_PFC_FUNCTION(sdhi3), 3773 SH_PFC_FUNCTION(usb0), 3774 SH_PFC_FUNCTION(usb1), 3775 SH_PFC_FUNCTION(usb2), 3776 SH_PFC_FUNCTION(usb2_ch3), 3777 }; 3778 3779 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3780 #define F_(x, y) FN_##y 3781 #define FM(x) FN_##x 3782 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 3783 0, 0, 3784 0, 0, 3785 0, 0, 3786 0, 0, 3787 0, 0, 3788 0, 0, 3789 0, 0, 3790 0, 0, 3791 0, 0, 3792 0, 0, 3793 0, 0, 3794 0, 0, 3795 0, 0, 3796 0, 0, 3797 0, 0, 3798 0, 0, 3799 GP_0_15_FN, GPSR0_15, 3800 GP_0_14_FN, GPSR0_14, 3801 GP_0_13_FN, GPSR0_13, 3802 GP_0_12_FN, GPSR0_12, 3803 GP_0_11_FN, GPSR0_11, 3804 GP_0_10_FN, GPSR0_10, 3805 GP_0_9_FN, GPSR0_9, 3806 GP_0_8_FN, GPSR0_8, 3807 GP_0_7_FN, GPSR0_7, 3808 GP_0_6_FN, GPSR0_6, 3809 GP_0_5_FN, GPSR0_5, 3810 GP_0_4_FN, GPSR0_4, 3811 GP_0_3_FN, GPSR0_3, 3812 GP_0_2_FN, GPSR0_2, 3813 GP_0_1_FN, GPSR0_1, 3814 GP_0_0_FN, GPSR0_0, } 3815 }, 3816 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 3817 0, 0, 3818 0, 0, 3819 0, 0, 3820 0, 0, 3821 GP_1_27_FN, GPSR1_27, 3822 GP_1_26_FN, GPSR1_26, 3823 GP_1_25_FN, GPSR1_25, 3824 GP_1_24_FN, GPSR1_24, 3825 GP_1_23_FN, GPSR1_23, 3826 GP_1_22_FN, GPSR1_22, 3827 GP_1_21_FN, GPSR1_21, 3828 GP_1_20_FN, GPSR1_20, 3829 GP_1_19_FN, GPSR1_19, 3830 GP_1_18_FN, GPSR1_18, 3831 GP_1_17_FN, GPSR1_17, 3832 GP_1_16_FN, GPSR1_16, 3833 GP_1_15_FN, GPSR1_15, 3834 GP_1_14_FN, GPSR1_14, 3835 GP_1_13_FN, GPSR1_13, 3836 GP_1_12_FN, GPSR1_12, 3837 GP_1_11_FN, GPSR1_11, 3838 GP_1_10_FN, GPSR1_10, 3839 GP_1_9_FN, GPSR1_9, 3840 GP_1_8_FN, GPSR1_8, 3841 GP_1_7_FN, GPSR1_7, 3842 GP_1_6_FN, GPSR1_6, 3843 GP_1_5_FN, GPSR1_5, 3844 GP_1_4_FN, GPSR1_4, 3845 GP_1_3_FN, GPSR1_3, 3846 GP_1_2_FN, GPSR1_2, 3847 GP_1_1_FN, GPSR1_1, 3848 GP_1_0_FN, GPSR1_0, } 3849 }, 3850 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 3851 0, 0, 3852 0, 0, 3853 0, 0, 3854 0, 0, 3855 0, 0, 3856 0, 0, 3857 0, 0, 3858 0, 0, 3859 0, 0, 3860 0, 0, 3861 0, 0, 3862 0, 0, 3863 0, 0, 3864 0, 0, 3865 0, 0, 3866 0, 0, 3867 0, 0, 3868 GP_2_14_FN, GPSR2_14, 3869 GP_2_13_FN, GPSR2_13, 3870 GP_2_12_FN, GPSR2_12, 3871 GP_2_11_FN, GPSR2_11, 3872 GP_2_10_FN, GPSR2_10, 3873 GP_2_9_FN, GPSR2_9, 3874 GP_2_8_FN, GPSR2_8, 3875 GP_2_7_FN, GPSR2_7, 3876 GP_2_6_FN, GPSR2_6, 3877 GP_2_5_FN, GPSR2_5, 3878 GP_2_4_FN, GPSR2_4, 3879 GP_2_3_FN, GPSR2_3, 3880 GP_2_2_FN, GPSR2_2, 3881 GP_2_1_FN, GPSR2_1, 3882 GP_2_0_FN, GPSR2_0, } 3883 }, 3884 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 3885 0, 0, 3886 0, 0, 3887 0, 0, 3888 0, 0, 3889 0, 0, 3890 0, 0, 3891 0, 0, 3892 0, 0, 3893 0, 0, 3894 0, 0, 3895 0, 0, 3896 0, 0, 3897 0, 0, 3898 0, 0, 3899 0, 0, 3900 0, 0, 3901 GP_3_15_FN, GPSR3_15, 3902 GP_3_14_FN, GPSR3_14, 3903 GP_3_13_FN, GPSR3_13, 3904 GP_3_12_FN, GPSR3_12, 3905 GP_3_11_FN, GPSR3_11, 3906 GP_3_10_FN, GPSR3_10, 3907 GP_3_9_FN, GPSR3_9, 3908 GP_3_8_FN, GPSR3_8, 3909 GP_3_7_FN, GPSR3_7, 3910 GP_3_6_FN, GPSR3_6, 3911 GP_3_5_FN, GPSR3_5, 3912 GP_3_4_FN, GPSR3_4, 3913 GP_3_3_FN, GPSR3_3, 3914 GP_3_2_FN, GPSR3_2, 3915 GP_3_1_FN, GPSR3_1, 3916 GP_3_0_FN, GPSR3_0, } 3917 }, 3918 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 3919 0, 0, 3920 0, 0, 3921 0, 0, 3922 0, 0, 3923 0, 0, 3924 0, 0, 3925 0, 0, 3926 0, 0, 3927 0, 0, 3928 0, 0, 3929 0, 0, 3930 0, 0, 3931 0, 0, 3932 0, 0, 3933 GP_4_17_FN, GPSR4_17, 3934 GP_4_16_FN, GPSR4_16, 3935 GP_4_15_FN, GPSR4_15, 3936 GP_4_14_FN, GPSR4_14, 3937 GP_4_13_FN, GPSR4_13, 3938 GP_4_12_FN, GPSR4_12, 3939 GP_4_11_FN, GPSR4_11, 3940 GP_4_10_FN, GPSR4_10, 3941 GP_4_9_FN, GPSR4_9, 3942 GP_4_8_FN, GPSR4_8, 3943 GP_4_7_FN, GPSR4_7, 3944 GP_4_6_FN, GPSR4_6, 3945 GP_4_5_FN, GPSR4_5, 3946 GP_4_4_FN, GPSR4_4, 3947 GP_4_3_FN, GPSR4_3, 3948 GP_4_2_FN, GPSR4_2, 3949 GP_4_1_FN, GPSR4_1, 3950 GP_4_0_FN, GPSR4_0, } 3951 }, 3952 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 3953 0, 0, 3954 0, 0, 3955 0, 0, 3956 0, 0, 3957 0, 0, 3958 0, 0, 3959 GP_5_25_FN, GPSR5_25, 3960 GP_5_24_FN, GPSR5_24, 3961 GP_5_23_FN, GPSR5_23, 3962 GP_5_22_FN, GPSR5_22, 3963 GP_5_21_FN, GPSR5_21, 3964 GP_5_20_FN, GPSR5_20, 3965 GP_5_19_FN, GPSR5_19, 3966 GP_5_18_FN, GPSR5_18, 3967 GP_5_17_FN, GPSR5_17, 3968 GP_5_16_FN, GPSR5_16, 3969 GP_5_15_FN, GPSR5_15, 3970 GP_5_14_FN, GPSR5_14, 3971 GP_5_13_FN, GPSR5_13, 3972 GP_5_12_FN, GPSR5_12, 3973 GP_5_11_FN, GPSR5_11, 3974 GP_5_10_FN, GPSR5_10, 3975 GP_5_9_FN, GPSR5_9, 3976 GP_5_8_FN, GPSR5_8, 3977 GP_5_7_FN, GPSR5_7, 3978 GP_5_6_FN, GPSR5_6, 3979 GP_5_5_FN, GPSR5_5, 3980 GP_5_4_FN, GPSR5_4, 3981 GP_5_3_FN, GPSR5_3, 3982 GP_5_2_FN, GPSR5_2, 3983 GP_5_1_FN, GPSR5_1, 3984 GP_5_0_FN, GPSR5_0, } 3985 }, 3986 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { 3987 GP_6_31_FN, GPSR6_31, 3988 GP_6_30_FN, GPSR6_30, 3989 GP_6_29_FN, GPSR6_29, 3990 GP_6_28_FN, GPSR6_28, 3991 GP_6_27_FN, GPSR6_27, 3992 GP_6_26_FN, GPSR6_26, 3993 GP_6_25_FN, GPSR6_25, 3994 GP_6_24_FN, GPSR6_24, 3995 GP_6_23_FN, GPSR6_23, 3996 GP_6_22_FN, GPSR6_22, 3997 GP_6_21_FN, GPSR6_21, 3998 GP_6_20_FN, GPSR6_20, 3999 GP_6_19_FN, GPSR6_19, 4000 GP_6_18_FN, GPSR6_18, 4001 GP_6_17_FN, GPSR6_17, 4002 GP_6_16_FN, GPSR6_16, 4003 GP_6_15_FN, GPSR6_15, 4004 GP_6_14_FN, GPSR6_14, 4005 GP_6_13_FN, GPSR6_13, 4006 GP_6_12_FN, GPSR6_12, 4007 GP_6_11_FN, GPSR6_11, 4008 GP_6_10_FN, GPSR6_10, 4009 GP_6_9_FN, GPSR6_9, 4010 GP_6_8_FN, GPSR6_8, 4011 GP_6_7_FN, GPSR6_7, 4012 GP_6_6_FN, GPSR6_6, 4013 GP_6_5_FN, GPSR6_5, 4014 GP_6_4_FN, GPSR6_4, 4015 GP_6_3_FN, GPSR6_3, 4016 GP_6_2_FN, GPSR6_2, 4017 GP_6_1_FN, GPSR6_1, 4018 GP_6_0_FN, GPSR6_0, } 4019 }, 4020 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { 4021 0, 0, 4022 0, 0, 4023 0, 0, 4024 0, 0, 4025 0, 0, 4026 0, 0, 4027 0, 0, 4028 0, 0, 4029 0, 0, 4030 0, 0, 4031 0, 0, 4032 0, 0, 4033 0, 0, 4034 0, 0, 4035 0, 0, 4036 0, 0, 4037 0, 0, 4038 0, 0, 4039 0, 0, 4040 0, 0, 4041 0, 0, 4042 0, 0, 4043 0, 0, 4044 0, 0, 4045 0, 0, 4046 0, 0, 4047 0, 0, 4048 0, 0, 4049 GP_7_3_FN, GPSR7_3, 4050 GP_7_2_FN, GPSR7_2, 4051 GP_7_1_FN, GPSR7_1, 4052 GP_7_0_FN, GPSR7_0, } 4053 }, 4054 #undef F_ 4055 #undef FM 4056 4057 #define F_(x, y) x, 4058 #define FM(x) FN_##x, 4059 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 4060 IP0_31_28 4061 IP0_27_24 4062 IP0_23_20 4063 IP0_19_16 4064 IP0_15_12 4065 IP0_11_8 4066 IP0_7_4 4067 IP0_3_0 } 4068 }, 4069 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 4070 IP1_31_28 4071 IP1_27_24 4072 IP1_23_20 4073 IP1_19_16 4074 IP1_15_12 4075 IP1_11_8 4076 IP1_7_4 4077 IP1_3_0 } 4078 }, 4079 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 4080 IP2_31_28 4081 IP2_27_24 4082 IP2_23_20 4083 IP2_19_16 4084 IP2_15_12 4085 IP2_11_8 4086 IP2_7_4 4087 IP2_3_0 } 4088 }, 4089 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 4090 IP3_31_28 4091 IP3_27_24 4092 IP3_23_20 4093 IP3_19_16 4094 IP3_15_12 4095 IP3_11_8 4096 IP3_7_4 4097 IP3_3_0 } 4098 }, 4099 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 4100 IP4_31_28 4101 IP4_27_24 4102 IP4_23_20 4103 IP4_19_16 4104 IP4_15_12 4105 IP4_11_8 4106 IP4_7_4 4107 IP4_3_0 } 4108 }, 4109 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 4110 IP5_31_28 4111 IP5_27_24 4112 IP5_23_20 4113 IP5_19_16 4114 IP5_15_12 4115 IP5_11_8 4116 IP5_7_4 4117 IP5_3_0 } 4118 }, 4119 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 4120 IP6_31_28 4121 IP6_27_24 4122 IP6_23_20 4123 IP6_19_16 4124 IP6_15_12 4125 IP6_11_8 4126 IP6_7_4 4127 IP6_3_0 } 4128 }, 4129 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 4130 IP7_31_28 4131 IP7_27_24 4132 IP7_23_20 4133 IP7_19_16 4134 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4135 IP7_11_8 4136 IP7_7_4 4137 IP7_3_0 } 4138 }, 4139 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 4140 IP8_31_28 4141 IP8_27_24 4142 IP8_23_20 4143 IP8_19_16 4144 IP8_15_12 4145 IP8_11_8 4146 IP8_7_4 4147 IP8_3_0 } 4148 }, 4149 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { 4150 IP9_31_28 4151 IP9_27_24 4152 IP9_23_20 4153 IP9_19_16 4154 IP9_15_12 4155 IP9_11_8 4156 IP9_7_4 4157 IP9_3_0 } 4158 }, 4159 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { 4160 IP10_31_28 4161 IP10_27_24 4162 IP10_23_20 4163 IP10_19_16 4164 IP10_15_12 4165 IP10_11_8 4166 IP10_7_4 4167 IP10_3_0 } 4168 }, 4169 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { 4170 IP11_31_28 4171 IP11_27_24 4172 IP11_23_20 4173 IP11_19_16 4174 IP11_15_12 4175 IP11_11_8 4176 IP11_7_4 4177 IP11_3_0 } 4178 }, 4179 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { 4180 IP12_31_28 4181 IP12_27_24 4182 IP12_23_20 4183 IP12_19_16 4184 IP12_15_12 4185 IP12_11_8 4186 IP12_7_4 4187 IP12_3_0 } 4188 }, 4189 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { 4190 IP13_31_28 4191 IP13_27_24 4192 IP13_23_20 4193 IP13_19_16 4194 IP13_15_12 4195 IP13_11_8 4196 IP13_7_4 4197 IP13_3_0 } 4198 }, 4199 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { 4200 IP14_31_28 4201 IP14_27_24 4202 IP14_23_20 4203 IP14_19_16 4204 IP14_15_12 4205 IP14_11_8 4206 IP14_7_4 4207 IP14_3_0 } 4208 }, 4209 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { 4210 IP15_31_28 4211 IP15_27_24 4212 IP15_23_20 4213 IP15_19_16 4214 IP15_15_12 4215 IP15_11_8 4216 IP15_7_4 4217 IP15_3_0 } 4218 }, 4219 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { 4220 IP16_31_28 4221 IP16_27_24 4222 IP16_23_20 4223 IP16_19_16 4224 IP16_15_12 4225 IP16_11_8 4226 IP16_7_4 4227 IP16_3_0 } 4228 }, 4229 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { 4230 IP17_31_28 4231 IP17_27_24 4232 IP17_23_20 4233 IP17_19_16 4234 IP17_15_12 4235 IP17_11_8 4236 IP17_7_4 4237 IP17_3_0 } 4238 }, 4239 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { 4240 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4241 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4242 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4243 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4244 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4245 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4246 IP18_7_4 4247 IP18_3_0 } 4248 }, 4249 #undef F_ 4250 #undef FM 4251 4252 #define F_(x, y) x, 4253 #define FM(x) FN_##x, 4254 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 4255 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 4256 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { 4257 MOD_SEL0_31_30_29 4258 MOD_SEL0_28_27 4259 MOD_SEL0_26_25_24 4260 MOD_SEL0_23 4261 MOD_SEL0_22 4262 MOD_SEL0_21 4263 MOD_SEL0_20 4264 MOD_SEL0_19 4265 MOD_SEL0_18_17 4266 MOD_SEL0_16 4267 0, 0, /* RESERVED 15 */ 4268 MOD_SEL0_14_13 4269 MOD_SEL0_12 4270 MOD_SEL0_11 4271 MOD_SEL0_10 4272 MOD_SEL0_9_8 4273 MOD_SEL0_7_6 4274 MOD_SEL0_5 4275 MOD_SEL0_4_3 4276 /* RESERVED 2, 1, 0 */ 4277 0, 0, 0, 0, 0, 0, 0, 0 } 4278 }, 4279 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 4280 2, 3, 1, 2, 3, 1, 1, 2, 1, 4281 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { 4282 MOD_SEL1_31_30 4283 MOD_SEL1_29_28_27 4284 MOD_SEL1_26 4285 MOD_SEL1_25_24 4286 MOD_SEL1_23_22_21 4287 MOD_SEL1_20 4288 MOD_SEL1_19 4289 MOD_SEL1_18_17 4290 MOD_SEL1_16 4291 MOD_SEL1_15_14 4292 MOD_SEL1_13 4293 MOD_SEL1_12 4294 MOD_SEL1_11 4295 MOD_SEL1_10 4296 MOD_SEL1_9 4297 0, 0, 0, 0, /* RESERVED 8, 7 */ 4298 MOD_SEL1_6 4299 MOD_SEL1_5 4300 MOD_SEL1_4 4301 MOD_SEL1_3 4302 MOD_SEL1_2 4303 MOD_SEL1_1 4304 MOD_SEL1_0 } 4305 }, 4306 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 4307 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4308 4, 4, 4, 3, 1) { 4309 MOD_SEL2_31 4310 MOD_SEL2_30 4311 MOD_SEL2_29 4312 MOD_SEL2_28_27 4313 MOD_SEL2_26 4314 MOD_SEL2_25_24_23 4315 /* RESERVED 22 */ 4316 0, 0, 4317 MOD_SEL2_21 4318 MOD_SEL2_20 4319 MOD_SEL2_19 4320 MOD_SEL2_18 4321 MOD_SEL2_17 4322 /* RESERVED 16 */ 4323 0, 0, 4324 /* RESERVED 15, 14, 13, 12 */ 4325 0, 0, 0, 0, 0, 0, 0, 0, 4326 0, 0, 0, 0, 0, 0, 0, 0, 4327 /* RESERVED 11, 10, 9, 8 */ 4328 0, 0, 0, 0, 0, 0, 0, 0, 4329 0, 0, 0, 0, 0, 0, 0, 0, 4330 /* RESERVED 7, 6, 5, 4 */ 4331 0, 0, 0, 0, 0, 0, 0, 0, 4332 0, 0, 0, 0, 0, 0, 0, 0, 4333 /* RESERVED 3, 2, 1 */ 4334 0, 0, 0, 0, 0, 0, 0, 0, 4335 MOD_SEL2_0 } 4336 }, 4337 { }, 4338 }; 4339 4340 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 4341 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 4342 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ 4343 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ 4344 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ 4345 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ 4346 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ 4347 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ 4348 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ 4349 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ 4350 } }, 4351 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 4352 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ 4353 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ 4354 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ 4355 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ 4356 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ 4357 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ 4358 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ 4359 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ 4360 } }, 4361 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 4362 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ 4363 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ 4364 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ 4365 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ 4366 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ 4367 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ 4368 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ 4369 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ 4370 } }, 4371 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 4372 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ 4373 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ 4374 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ 4375 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ 4376 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ 4377 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 4378 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 4379 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 4380 } }, 4381 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 4382 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 4383 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 4384 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 4385 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 4386 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 4387 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 4388 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 4389 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 4390 } }, 4391 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 4392 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 4393 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 4394 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 4395 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 4396 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 4397 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 4398 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 4399 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 4400 } }, 4401 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 4402 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 4403 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 4404 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 4405 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 4406 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 4407 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 4408 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 4409 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 4410 } }, 4411 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 4412 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 4413 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 4414 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 4415 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 4416 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 4417 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 4418 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 4419 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 4420 } }, 4421 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 4422 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */ 4423 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 4424 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 4425 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 4426 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 4427 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 4428 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 4429 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 4430 } }, 4431 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 4432 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 4433 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ 4434 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 4435 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 4436 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 4437 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 4438 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 4439 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 4440 } }, 4441 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 4442 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 4443 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 4444 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 4445 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 4446 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 4447 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 4448 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 4449 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 4450 } }, 4451 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 4452 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 4453 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 4454 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 4455 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 4456 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ 4457 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */ 4458 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ 4459 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ 4460 } }, 4461 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 4462 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */ 4463 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */ 4464 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */ 4465 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ 4466 } }, 4467 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 4468 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ 4469 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ 4470 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 4471 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 4472 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 4473 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 4474 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 4475 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 4476 } }, 4477 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 4478 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 4479 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 4480 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 4481 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 4482 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 4483 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 4484 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 4485 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 4486 } }, 4487 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 4488 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 4489 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 4490 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 4491 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 4492 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 4493 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 4494 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 4495 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 4496 } }, 4497 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 4498 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 4499 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 4500 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 4501 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 4502 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 4503 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 4504 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 4505 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 4506 } }, 4507 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 4508 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 4509 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 4510 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 4511 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 4512 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 4513 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 4514 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 4515 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 4516 } }, 4517 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 4518 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ 4519 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 4520 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 4521 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 4522 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ 4523 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 4524 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 4525 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 4526 } }, 4527 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 4528 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 4529 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 4530 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 4531 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 4532 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 4533 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 4534 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 4535 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 4536 } }, 4537 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 4538 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 4539 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 4540 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 4541 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 4542 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 4543 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 4544 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ 4545 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 4546 } }, 4547 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 4548 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 4549 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 4550 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 4551 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 4552 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 4553 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 4554 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 4555 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 4556 } }, 4557 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 4558 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 4559 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 4560 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 4561 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 4562 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 4563 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 4564 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 4565 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 4566 } }, 4567 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 4568 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 4569 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 4570 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 4571 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 4572 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 4573 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 4574 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 4575 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 4576 } }, 4577 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 4578 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 4579 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 4580 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 4581 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 4582 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 4583 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */ 4584 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */ 4585 } }, 4586 { }, 4587 }; 4588 4589 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 4590 { 4591 int bit = -EINVAL; 4592 4593 *pocctrl = 0xe6060380; 4594 4595 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 4596 bit = pin & 0x1f; 4597 4598 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 4599 bit = (pin & 0x1f) + 12; 4600 4601 return bit; 4602 } 4603 4604 #define PUEN 0xe6060400 4605 #define PUD 0xe6060440 4606 4607 #define PU0 0x00 4608 #define PU1 0x04 4609 #define PU2 0x08 4610 #define PU3 0x0c 4611 #define PU4 0x10 4612 #define PU5 0x14 4613 #define PU6 0x18 4614 4615 static const struct sh_pfc_bias_info bias_info[] = { 4616 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ 4617 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ 4618 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ 4619 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ 4620 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ 4621 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ 4622 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ 4623 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ 4624 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ 4625 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ 4626 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ 4627 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ 4628 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ 4629 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ 4630 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ 4631 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ 4632 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ 4633 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ 4634 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ 4635 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ 4636 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ 4637 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ 4638 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ 4639 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ 4640 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ 4641 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ 4642 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ 4643 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ 4644 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ 4645 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ 4646 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ 4647 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ 4648 4649 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ 4650 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ 4651 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ 4652 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ 4653 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ 4654 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ 4655 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ 4656 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ 4657 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ 4658 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ 4659 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ 4660 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ 4661 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ 4662 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ 4663 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ 4664 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ 4665 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ 4666 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ 4667 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ 4668 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ 4669 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ 4670 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ 4671 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ 4672 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ 4673 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ 4674 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ 4675 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ 4676 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ 4677 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ 4678 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ 4679 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ 4680 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ 4681 4682 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ 4683 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ 4684 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ 4685 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ 4686 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ 4687 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ 4688 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ 4689 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ 4690 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ 4691 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ 4692 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ 4693 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ 4694 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ 4695 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ 4696 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ 4697 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ 4698 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ 4699 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ 4700 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ 4701 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ 4702 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ 4703 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ 4704 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ 4705 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ 4706 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ 4707 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ 4708 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ 4709 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ 4710 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ 4711 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */ 4712 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ 4713 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ 4714 4715 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ 4716 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ 4717 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ 4718 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ 4719 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ 4720 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ 4721 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ 4722 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ 4723 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ 4724 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ 4725 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ 4726 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ 4727 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ 4728 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ 4729 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ 4730 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ 4731 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ 4732 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ 4733 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ 4734 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ 4735 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ 4736 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ 4737 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ 4738 /* bit 8 n/a */ 4739 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ 4740 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ 4741 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ 4742 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ 4743 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ 4744 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */ 4745 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */ 4746 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */ 4747 4748 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ 4749 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ 4750 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ 4751 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ 4752 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ 4753 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ 4754 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ 4755 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ 4756 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ 4757 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ 4758 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ 4759 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ 4760 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ 4761 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ 4762 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ 4763 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ 4764 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ 4765 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ 4766 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ 4767 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ 4768 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ 4769 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ 4770 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ 4771 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ 4772 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ 4773 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ 4774 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ 4775 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ 4776 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ 4777 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ 4778 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ 4779 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ 4780 4781 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ 4782 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ 4783 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ 4784 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ 4785 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ 4786 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ 4787 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ 4788 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ 4789 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ 4790 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ 4791 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ 4792 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ 4793 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ 4794 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ 4795 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ 4796 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ 4797 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ 4798 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ 4799 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ 4800 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ 4801 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ 4802 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ 4803 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ 4804 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ 4805 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ 4806 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ 4807 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ 4808 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ 4809 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ 4810 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ 4811 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ 4812 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ 4813 4814 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */ 4815 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */ 4816 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ 4817 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ 4818 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ 4819 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ 4820 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ 4821 }; 4822 4823 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, 4824 unsigned int pin) 4825 { 4826 const struct sh_pfc_bias_info *info; 4827 u32 reg; 4828 u32 bit; 4829 4830 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 4831 if (!info) 4832 return PIN_CONFIG_BIAS_DISABLE; 4833 4834 reg = info->reg; 4835 bit = BIT(info->bit); 4836 4837 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) 4838 return PIN_CONFIG_BIAS_DISABLE; 4839 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) 4840 return PIN_CONFIG_BIAS_PULL_UP; 4841 else 4842 return PIN_CONFIG_BIAS_PULL_DOWN; 4843 } 4844 4845 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 4846 unsigned int bias) 4847 { 4848 const struct sh_pfc_bias_info *info; 4849 u32 enable, updown; 4850 u32 reg; 4851 u32 bit; 4852 4853 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 4854 if (!info) 4855 return; 4856 4857 reg = info->reg; 4858 bit = BIT(info->bit); 4859 4860 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; 4861 if (bias != PIN_CONFIG_BIAS_DISABLE) 4862 enable |= bit; 4863 4864 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; 4865 if (bias == PIN_CONFIG_BIAS_PULL_UP) 4866 updown |= bit; 4867 4868 sh_pfc_write_reg(pfc, PUD + reg, 32, updown); 4869 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); 4870 } 4871 4872 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { 4873 .pin_to_pocctrl = r8a7795_pin_to_pocctrl, 4874 .get_bias = r8a7795_pinmux_get_bias, 4875 .set_bias = r8a7795_pinmux_set_bias, 4876 }; 4877 4878 const struct sh_pfc_soc_info r8a7795_pinmux_info = { 4879 .name = "r8a77951_pfc", 4880 .ops = &r8a7795_pinmux_ops, 4881 .unlock_reg = 0xe6060000, /* PMMR */ 4882 4883 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 4884 4885 .pins = pinmux_pins, 4886 .nr_pins = ARRAY_SIZE(pinmux_pins), 4887 .groups = pinmux_groups, 4888 .nr_groups = ARRAY_SIZE(pinmux_groups), 4889 .functions = pinmux_functions, 4890 .nr_functions = ARRAY_SIZE(pinmux_functions), 4891 4892 .cfg_regs = pinmux_config_regs, 4893 .drive_regs = pinmux_drive_regs, 4894 4895 .pinmux_data = pinmux_data, 4896 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 4897 }; 4898