1 /* 2 * r8a7794/r8a7745 processor support - PFC hardware block. 3 * 4 * Copyright (C) 2014-2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <dm/pinctrl.h> 15 #include <linux/kernel.h> 16 17 #include "sh_pfc.h" 18 19 #define CPU_ALL_PORT(fn, sfx) \ 20 PORT_GP_32(0, fn, sfx), \ 21 PORT_GP_26(1, fn, sfx), \ 22 PORT_GP_32(2, fn, sfx), \ 23 PORT_GP_32(3, fn, sfx), \ 24 PORT_GP_32(4, fn, sfx), \ 25 PORT_GP_28(5, fn, sfx), \ 26 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 27 PORT_GP_1(6, 24, fn, sfx), \ 28 PORT_GP_1(6, 25, fn, sfx) 29 30 enum { 31 PINMUX_RESERVED = 0, 32 33 PINMUX_DATA_BEGIN, 34 GP_ALL(DATA), 35 PINMUX_DATA_END, 36 37 PINMUX_FUNCTION_BEGIN, 38 GP_ALL(FN), 39 40 /* GPSR0 */ 41 FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, 42 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, 43 FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, 44 FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, 45 FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, 46 FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, 47 FN_IP2_17_16, 48 49 /* GPSR1 */ 50 FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, 51 FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, 52 FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, 53 FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, 54 FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, 55 56 /* GPSR2 */ 57 FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, 58 FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, 59 FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, 60 FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, 61 FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, 62 FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, 63 FN_IP6_5_4, FN_IP6_7_6, 64 65 /* GPSR3 */ 66 FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, 67 FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, 68 FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, 69 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, 70 FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, 71 FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, 72 FN_IP8_22_20, 73 74 /* GPSR4 */ 75 FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, 76 FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, 77 FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, 78 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, 79 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, 80 FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, 81 FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, 82 83 /* GPSR5 */ 84 FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, 85 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, 86 FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, 87 FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, 88 FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, 89 FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, 90 91 /* GPSR6 */ 92 FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, 93 FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, 94 FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, 95 FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, 96 FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, 97 98 /* IPSR0 */ 99 FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK, 100 FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1, 101 FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3, 102 FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD, 103 FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, 104 FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B, 105 FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4, 106 FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 107 108 /* IPSR1 */ 109 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 110 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, 111 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 112 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 113 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, 114 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, 115 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, 116 FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B, 117 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 118 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 119 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 120 FN_A1, FN_SCIFB1_TXD, 121 FN_A3, FN_SCIFB0_SCK, 122 FN_A4, FN_SCIFB0_TXD, 123 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, 124 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, 125 126 /* IPSR2 */ 127 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 128 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 129 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 130 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 131 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 132 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 133 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 134 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, 135 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, 136 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C, 137 FN_TPUTO2_B, 138 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, 139 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, 140 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, 141 FN_A20, FN_SPCLK, 142 143 /* IPSR3 */ 144 FN_A21, FN_MOSI_IO0, 145 FN_A22, FN_MISO_IO1, FN_ATADIR1_N, 146 FN_A23, FN_IO2, FN_ATAWR1_N, 147 FN_A24, FN_IO3, FN_EX_WAIT2, 148 FN_A25, FN_SSL, FN_ATARD1_N, 149 FN_CS0_N, FN_VI1_DATA8, 150 FN_CS1_N_A26, FN_VI1_DATA9, 151 FN_EX_CS0_N, FN_VI1_DATA10, 152 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, 153 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3, 154 FN_SCIFB2_TXD, 155 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK, 156 FN_SCIFB2_SCK, 157 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK, 158 FN_SCIFB2_CTS_N, 159 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN, 160 FN_SCIFB2_RTS_N, 161 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, 162 FN_RD_N, FN_ATACS11_N, 163 FN_RD_WR_N, FN_ATAG1_N, 164 165 /* IPSR4 */ 166 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 167 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, 168 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, 169 FN_DU0_DR2, FN_LCDOUT18, 170 FN_DU0_DR3, FN_LCDOUT19, 171 FN_DU0_DR4, FN_LCDOUT20, 172 FN_DU0_DR5, FN_LCDOUT21, 173 FN_DU0_DR6, FN_LCDOUT22, 174 FN_DU0_DR7, FN_LCDOUT23, 175 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, 176 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, 177 FN_DU0_DG2, FN_LCDOUT10, 178 FN_DU0_DG3, FN_LCDOUT11, 179 FN_DU0_DG4, FN_LCDOUT12, 180 181 /* IPSR5 */ 182 FN_DU0_DG5, FN_LCDOUT13, 183 FN_DU0_DG6, FN_LCDOUT14, 184 FN_DU0_DG7, FN_LCDOUT15, 185 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, 186 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C, 187 FN_DU0_DB2, FN_LCDOUT2, 188 FN_DU0_DB3, FN_LCDOUT3, 189 FN_DU0_DB4, FN_LCDOUT4, 190 FN_DU0_DB5, FN_LCDOUT5, 191 FN_DU0_DB6, FN_LCDOUT6, 192 FN_DU0_DB7, FN_LCDOUT7, 193 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 194 FN_DU0_DOTCLKOUT0, FN_QCLK, 195 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 196 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 197 198 /* IPSR6 */ 199 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 200 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 201 FN_DU0_DISP, FN_QPOLA, 202 FN_DU0_CDE, FN_QPOLB, 203 FN_VI0_CLK, FN_AVB_RX_CLK, 204 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, 205 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, 206 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, 207 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, 208 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, 209 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, 210 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, 211 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, 212 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, 213 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, 214 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, 215 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, 216 FN_AVB_TX_EN, 217 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK, 218 FN_ADIDATA, 219 220 /* IPSR7 */ 221 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0, 222 FN_ADICS_SAMP, 223 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1, 224 FN_ADICLK, 225 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, 226 FN_ADICHS0, 227 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, 228 FN_ADICHS1, 229 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4, 230 FN_ADICHS2, 231 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B, 232 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6, 233 FN_SSI_WS5_B, 234 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7, 235 FN_SSI_SDATA5_B, 236 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, 237 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, 238 FN_SSI_WS6_B, 239 FN_DREQ0_N, FN_SCIFB1_RXD, 240 241 /* IPSR8 */ 242 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, 243 FN_SSI_SDATA6_B, 244 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO, 245 FN_SSI_SCK78_B, 246 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, 247 FN_SSI_WS78_B, 248 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, 249 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 250 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, 251 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 252 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, 253 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, 254 FN_CAN1_RX_D, FN_TPUTO0_B, 255 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE, 256 FN_CAN1_TX_D, 257 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D, 258 FN_TPUTO1_B, 259 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D, 260 FN_BPFCLK_C, 261 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D, 262 FN_FMCLK_C, 263 264 /* IPSR9 */ 265 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D, 266 FN_FMIN_C, 267 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C, 268 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B, 269 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B, 270 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B, 271 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, 272 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, 273 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B, 274 FN_SPEEDIN_B, 275 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B, 276 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B, 277 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B, 278 279 /* IPSR10 */ 280 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, 281 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B, 282 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, 283 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, 284 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, 285 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B, 286 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C, 287 FN_SSI_SCK4_B, 288 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, 289 FN_SSI_WS4_B, 290 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, 291 FN_SSI_SDATA4_B, 292 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, 293 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 294 295 /* IPSR11 */ 296 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, 297 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, 298 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 299 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, 300 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, 301 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 302 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, 303 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, 304 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, 305 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, 306 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, 307 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, 308 309 /* IPSR12 */ 310 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, 311 FN_DREQ1_N_B, 312 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, 313 FN_CAN1_RX_C, FN_DACK1_B, 314 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, 315 FN_CAN1_TX_C, FN_DREQ2_N, 316 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 317 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 318 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON, 319 FN_DACK2, FN_ETH_MDIO_B, 320 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, 321 FN_ETH_CRS_DV_B, 322 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, 323 FN_ETH_RX_ER_B, 324 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N, 325 FN_ETH_RXD0_B, 326 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B, 327 328 /* IPSR13 */ 329 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, 330 FN_ATACS00_N, FN_ETH_LINK_B, 331 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4, 332 FN_ATACS10_N, FN_ETH_REFCLK_B, 333 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1, 334 FN_ETH_TXD1_B, 335 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N, 336 FN_ETH_TX_EN_B, 337 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, 338 FN_ATADIR0_N, FN_ETH_MAGIC_B, 339 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, 340 FN_TS_SDATA_C, FN_ETH_TXD0_B, 341 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, 342 FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B, 343 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, 344 FN_TS_SDEN_C, FN_FMCLK_E, 345 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, 346 FN_TS_SPSYNC_C, FN_FMIN_E, 347 348 /* MOD_SEL */ 349 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, 350 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, 351 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, 352 FN_SEL_DARC_4, 353 FN_SEL_ETH_0, FN_SEL_ETH_1, 354 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, 355 FN_SEL_I2C00_4, 356 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, 357 FN_SEL_I2C01_4, 358 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, 359 FN_SEL_I2C02_4, 360 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, 361 FN_SEL_I2C03_4, 362 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, 363 FN_SEL_I2C04_4, 364 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, 365 366 /* MOD_SEL2 */ 367 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 368 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, 369 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, 370 FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, 371 FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, 372 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, 373 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 374 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, 375 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, 376 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, 377 FN_SEL_TMU_0, FN_SEL_TMU_1, 378 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 379 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 380 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 381 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 382 383 /* MOD_SEL3 */ 384 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 385 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, 386 FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, 387 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 388 FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, 389 FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, 390 FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, 391 FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, 392 FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, 393 FN_SEL_SSI9_1, 394 PINMUX_FUNCTION_END, 395 396 PINMUX_MARK_BEGIN, 397 A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, 398 399 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, 400 401 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, 402 SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, 403 404 SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, 405 SD1_DATA2_MARK, SD1_DATA3_MARK, 406 407 /* IPSR0 */ 408 SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK, 409 MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK, 410 SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK, 411 SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK, 412 MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK, 413 CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK, 414 CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK, 415 SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK, 416 SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK, 417 SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, 418 419 /* IPSR1 */ 420 D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, 421 D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK, 422 D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK, 423 D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, 424 D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, 425 D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK, 426 D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK, 427 D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK, 428 D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK, 429 D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK, 430 A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, 431 A1_MARK, SCIFB1_TXD_MARK, 432 A3_MARK, SCIFB0_SCK_MARK, 433 A4_MARK, SCIFB0_TXD_MARK, 434 A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, 435 A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK, 436 437 /* IPSR2 */ 438 A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, 439 A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK, 440 A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK, 441 A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK, 442 A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK, 443 A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK, 444 A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, 445 A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK, 446 A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK, 447 A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, 448 CAN_CLK_C_MARK, TPUTO2_B_MARK, 449 A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK, 450 A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, 451 A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, 452 A20_MARK, SPCLK_MARK, 453 454 /* IPSR3 */ 455 A21_MARK, MOSI_IO0_MARK, 456 A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK, 457 A23_MARK, IO2_MARK, ATAWR1_N_MARK, 458 A24_MARK, IO3_MARK, EX_WAIT2_MARK, 459 A25_MARK, SSL_MARK, ATARD1_N_MARK, 460 CS0_N_MARK, VI1_DATA8_MARK, 461 CS1_N_A26_MARK, VI1_DATA9_MARK, 462 EX_CS0_N_MARK, VI1_DATA10_MARK, 463 EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, 464 EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, 465 TPUTO3_MARK, SCIFB2_TXD_MARK, 466 EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, 467 BPFCLK_MARK, SCIFB2_SCK_MARK, 468 EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, 469 FMCLK_MARK, SCIFB2_CTS_N_MARK, 470 EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, 471 FMIN_MARK, SCIFB2_RTS_N_MARK, 472 BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, 473 RD_N_MARK, ATACS11_N_MARK, 474 RD_WR_N_MARK, ATAG1_N_MARK, 475 476 /* IPSR4 */ 477 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, 478 DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK, 479 DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK, 480 DU0_DR2_MARK, LCDOUT18_MARK, 481 DU0_DR3_MARK, LCDOUT19_MARK, 482 DU0_DR4_MARK, LCDOUT20_MARK, 483 DU0_DR5_MARK, LCDOUT21_MARK, 484 DU0_DR6_MARK, LCDOUT22_MARK, 485 DU0_DR7_MARK, LCDOUT23_MARK, 486 DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK, 487 DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK, 488 DU0_DG2_MARK, LCDOUT10_MARK, 489 DU0_DG3_MARK, LCDOUT11_MARK, 490 DU0_DG4_MARK, LCDOUT12_MARK, 491 492 /* IPSR5 */ 493 DU0_DG5_MARK, LCDOUT13_MARK, 494 DU0_DG6_MARK, LCDOUT14_MARK, 495 DU0_DG7_MARK, LCDOUT15_MARK, 496 DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK, 497 CAN0_RX_C_MARK, 498 DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, 499 CAN0_TX_C_MARK, 500 DU0_DB2_MARK, LCDOUT2_MARK, 501 DU0_DB3_MARK, LCDOUT3_MARK, 502 DU0_DB4_MARK, LCDOUT4_MARK, 503 DU0_DB5_MARK, LCDOUT5_MARK, 504 DU0_DB6_MARK, LCDOUT6_MARK, 505 DU0_DB7_MARK, LCDOUT7_MARK, 506 DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK, 507 DU0_DOTCLKOUT0_MARK, QCLK_MARK, 508 DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, 509 DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, 510 511 /* IPSR6 */ 512 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, 513 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 514 DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK, 515 VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK, 516 VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, 517 VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, 518 VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK, 519 VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, 520 VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, 521 VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK, 522 VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, 523 VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, 524 AVB_RXD7_MARK, 525 VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, 526 AVB_RX_ER_MARK, 527 VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK, 528 AVB_COL_MARK, 529 VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK, 530 AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, 531 ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK, 532 AVB_TX_CLK_MARK, ADIDATA_MARK, 533 534 /* IPSR7 */ 535 ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK, 536 AVB_TXD0_MARK, ADICS_SAMP_MARK, 537 ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, 538 AVB_TXD1_MARK, ADICLK_MARK, 539 ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK, 540 AVB_TXD2_MARK, ADICHS0_MARK, 541 ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, 542 AVB_TXD3_MARK, ADICHS1_MARK, 543 ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, 544 AVB_TXD4_MARK, ADICHS2_MARK, 545 ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, 546 SSI_SCK5_B_MARK, 547 ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK, 548 AVB_TXD6_MARK, SSI_WS5_B_MARK, 549 ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK, 550 AVB_TXD7_MARK, SSI_SDATA5_B_MARK, 551 ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK, 552 SSI_SCK6_B_MARK, 553 ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, 554 AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, 555 DREQ0_N_MARK, SCIFB1_RXD_MARK, 556 557 /* IPSR8 */ 558 ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, 559 AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, 560 I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, 561 HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, 562 AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, 563 SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, 564 HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, 565 AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, 566 HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, 567 I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, 568 AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, 569 SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, 570 CAN1_TX_D_MARK, 571 I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK, 572 TS_SDATA_D_MARK, TPUTO1_B_MARK, 573 I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK, 574 BPFCLK_C_MARK, 575 MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK, 576 TS_SDEN_D_MARK, FMCLK_C_MARK, 577 578 /* IPSR9 */ 579 MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK, 580 TS_SPSYNC_D_MARK, FMIN_C_MARK, 581 MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK, 582 MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK, 583 MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK, 584 FMCLK_B_MARK, 585 MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK, 586 FMIN_B_MARK, 587 HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, 588 HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, 589 HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, 590 SPEEDIN_B_MARK, 591 HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK, 592 SSI_SCK1_B_MARK, 593 HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK, 594 SSI_WS1_B_MARK, 595 SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK, 596 CAN_TXCLK_MARK, 597 598 /* IPSR10 */ 599 SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, 600 SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK, 601 SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, 602 SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, 603 SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK, 604 SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK, 605 SSI_SDATA9_B_MARK, 606 SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK, 607 AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, 608 SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK, 609 AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, 610 I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, 611 SSI_SDATA4_B_MARK, 612 I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, 613 SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, 614 615 /* IPSR11 */ 616 SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, 617 SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK, 618 SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, 619 SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, 620 DU1_EXVSYNC_DU1_VSYNC_MARK, 621 SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, 622 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 623 SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK, 624 SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK, 625 SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, 626 CAN_CLK_D_MARK, 627 SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, 628 SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK, 629 SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK, 630 631 /* IPSR12 */ 632 SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK, 633 DREQ1_N_B_MARK, 634 SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, 635 CAN1_RX_C_MARK, DACK1_B_MARK, 636 SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK, 637 CAN1_TX_C_MARK, DREQ2_N_MARK, 638 SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, 639 SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, 640 SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, 641 SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK, 642 DACK2_MARK, ETH_MDIO_B_MARK, 643 SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK, 644 CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK, 645 SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK, 646 CAN0_TX_D_MARK, ETH_RX_ER_B_MARK, 647 SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK, 648 ETH_RXD0_B_MARK, 649 SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK, 650 ETH_RXD1_B_MARK, 651 652 /* IPSR13 */ 653 SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, 654 ATACS00_N_MARK, ETH_LINK_B_MARK, 655 SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, 656 VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK, 657 SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK, 658 EX_WAIT1_MARK, ETH_TXD1_B_MARK, 659 SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK, 660 ATARD0_N_MARK, ETH_TX_EN_B_MARK, 661 SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, 662 ATADIR0_N_MARK, ETH_MAGIC_B_MARK, 663 AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK, 664 TS_SDATA_C_MARK, ETH_TXD0_B_MARK, 665 AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK, 666 TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, 667 AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK, 668 TS_SDEN_C_MARK, FMCLK_E_MARK, 669 AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK, 670 TS_SPSYNC_C_MARK, FMIN_E_MARK, 671 PINMUX_MARK_END, 672 }; 673 674 static const u16 pinmux_data[] = { 675 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 676 677 PINMUX_SINGLE(A2), 678 PINMUX_SINGLE(WE0_N), 679 PINMUX_SINGLE(WE1_N), 680 PINMUX_SINGLE(DACK0), 681 PINMUX_SINGLE(USB0_PWEN), 682 PINMUX_SINGLE(USB0_OVC), 683 PINMUX_SINGLE(USB1_PWEN), 684 PINMUX_SINGLE(USB1_OVC), 685 PINMUX_SINGLE(SD0_CLK), 686 PINMUX_SINGLE(SD0_CMD), 687 PINMUX_SINGLE(SD0_DATA0), 688 PINMUX_SINGLE(SD0_DATA1), 689 PINMUX_SINGLE(SD0_DATA2), 690 PINMUX_SINGLE(SD0_DATA3), 691 PINMUX_SINGLE(SD0_CD), 692 PINMUX_SINGLE(SD0_WP), 693 PINMUX_SINGLE(SD1_CLK), 694 PINMUX_SINGLE(SD1_CMD), 695 PINMUX_SINGLE(SD1_DATA0), 696 PINMUX_SINGLE(SD1_DATA1), 697 PINMUX_SINGLE(SD1_DATA2), 698 PINMUX_SINGLE(SD1_DATA3), 699 700 /* IPSR0 */ 701 PINMUX_IPSR_GPSR(IP0_0, SD1_CD), 702 PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0), 703 PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP), 704 PINMUX_IPSR_GPSR(IP0_9_8, IRQ7), 705 PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0), 706 PINMUX_IPSR_GPSR(IP0_10, MMC_CLK), 707 PINMUX_IPSR_GPSR(IP0_10, SD2_CLK), 708 PINMUX_IPSR_GPSR(IP0_11, MMC_CMD), 709 PINMUX_IPSR_GPSR(IP0_11, SD2_CMD), 710 PINMUX_IPSR_GPSR(IP0_12, MMC_D0), 711 PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0), 712 PINMUX_IPSR_GPSR(IP0_13, MMC_D1), 713 PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1), 714 PINMUX_IPSR_GPSR(IP0_14, MMC_D2), 715 PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2), 716 PINMUX_IPSR_GPSR(IP0_15, MMC_D3), 717 PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3), 718 PINMUX_IPSR_GPSR(IP0_16, MMC_D4), 719 PINMUX_IPSR_GPSR(IP0_16, SD2_CD), 720 PINMUX_IPSR_GPSR(IP0_17, MMC_D5), 721 PINMUX_IPSR_GPSR(IP0_17, SD2_WP), 722 PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6), 723 PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), 724 PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), 725 PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0), 726 PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7), 727 PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), 728 PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), 729 PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0), 730 PINMUX_IPSR_GPSR(IP0_23_22, D0), 731 PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), 732 PINMUX_IPSR_GPSR(IP0_23_22, IRQ4), 733 PINMUX_IPSR_GPSR(IP0_24, D1), 734 PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), 735 PINMUX_IPSR_GPSR(IP0_25, D2), 736 PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), 737 PINMUX_IPSR_GPSR(IP0_27_26, D3), 738 PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), 739 PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), 740 PINMUX_IPSR_GPSR(IP0_29_28, D4), 741 PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), 742 PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), 743 PINMUX_IPSR_GPSR(IP0_31_30, D5), 744 PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), 745 PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), 746 747 /* IPSR1 */ 748 PINMUX_IPSR_GPSR(IP1_1_0, D6), 749 PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), 750 PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), 751 PINMUX_IPSR_GPSR(IP1_3_2, D7), 752 PINMUX_IPSR_GPSR(IP1_3_2, IRQ3), 753 PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0), 754 PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B), 755 PINMUX_IPSR_GPSR(IP1_5_4, D8), 756 PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX), 757 PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), 758 PINMUX_IPSR_GPSR(IP1_7_6, D9), 759 PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX), 760 PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), 761 PINMUX_IPSR_GPSR(IP1_10_8, D10), 762 PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK), 763 PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), 764 PINMUX_IPSR_GPSR(IP1_10_8, IRQ6), 765 PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C), 766 PINMUX_IPSR_GPSR(IP1_12_11, D11), 767 PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N), 768 PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), 769 PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), 770 PINMUX_IPSR_GPSR(IP1_14_13, D12), 771 PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N), 772 PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), 773 PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), 774 PINMUX_IPSR_GPSR(IP1_17_15, D13), 775 PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), 776 PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C), 777 PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1), 778 PINMUX_IPSR_GPSR(IP1_19_18, D14), 779 PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), 780 PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1), 781 PINMUX_IPSR_GPSR(IP1_21_20, D15), 782 PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), 783 PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1), 784 PINMUX_IPSR_GPSR(IP1_23_22, A0), 785 PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK), 786 PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B), 787 PINMUX_IPSR_GPSR(IP1_24, A1), 788 PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD), 789 PINMUX_IPSR_GPSR(IP1_26, A3), 790 PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK), 791 PINMUX_IPSR_GPSR(IP1_27, A4), 792 PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD), 793 PINMUX_IPSR_GPSR(IP1_29_28, A5), 794 PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD), 795 PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B), 796 PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C), 797 PINMUX_IPSR_GPSR(IP1_31_30, A6), 798 PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N), 799 PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), 800 PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C), 801 802 /* IPSR2 */ 803 PINMUX_IPSR_GPSR(IP2_1_0, A7), 804 PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N), 805 PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), 806 PINMUX_IPSR_GPSR(IP2_3_2, A8), 807 PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), 808 PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), 809 PINMUX_IPSR_GPSR(IP2_5_4, A9), 810 PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), 811 PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), 812 PINMUX_IPSR_GPSR(IP2_7_6, A10), 813 PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), 814 PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1), 815 PINMUX_IPSR_GPSR(IP2_9_8, A11), 816 PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), 817 PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1), 818 PINMUX_IPSR_GPSR(IP2_11_10, A12), 819 PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), 820 PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), 821 PINMUX_IPSR_GPSR(IP2_13_12, A13), 822 PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), 823 PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), 824 PINMUX_IPSR_GPSR(IP2_15_14, A14), 825 PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), 826 PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), 827 PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0), 828 PINMUX_IPSR_GPSR(IP2_17_16, A15), 829 PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), 830 PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), 831 PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0), 832 PINMUX_IPSR_GPSR(IP2_20_18, A16), 833 PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), 834 PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), 835 PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), 836 PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2), 837 PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B), 838 PINMUX_IPSR_GPSR(IP2_23_21, A17), 839 PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), 840 PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), 841 PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), 842 PINMUX_IPSR_GPSR(IP2_26_24, A18), 843 PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), 844 PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), 845 PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), 846 PINMUX_IPSR_GPSR(IP2_29_27, A19), 847 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), 848 PINMUX_IPSR_GPSR(IP2_29_27, PWM4), 849 PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2), 850 PINMUX_IPSR_GPSR(IP2_31_30, A20), 851 PINMUX_IPSR_GPSR(IP2_31_30, SPCLK), 852 853 /* IPSR3 */ 854 PINMUX_IPSR_GPSR(IP3_1_0, A21), 855 PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0), 856 PINMUX_IPSR_GPSR(IP3_3_2, A22), 857 PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1), 858 PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N), 859 PINMUX_IPSR_GPSR(IP3_5_4, A23), 860 PINMUX_IPSR_GPSR(IP3_5_4, IO2), 861 PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N), 862 PINMUX_IPSR_GPSR(IP3_7_6, A24), 863 PINMUX_IPSR_GPSR(IP3_7_6, IO3), 864 PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2), 865 PINMUX_IPSR_GPSR(IP3_9_8, A25), 866 PINMUX_IPSR_GPSR(IP3_9_8, SSL), 867 PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N), 868 PINMUX_IPSR_GPSR(IP3_10, CS0_N), 869 PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8), 870 PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26), 871 PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9), 872 PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N), 873 PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10), 874 PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N), 875 PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B), 876 PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD), 877 PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11), 878 PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N), 879 PINMUX_IPSR_GPSR(IP3_17_15, PWM0), 880 PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), 881 PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), 882 PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3), 883 PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD), 884 PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N), 885 PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), 886 PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), 887 PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), 888 PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), 889 PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK), 890 PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N), 891 PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), 892 PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), 893 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), 894 PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), 895 PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N), 896 PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N), 897 PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), 898 PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), 899 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), 900 PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), 901 PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N), 902 PINMUX_IPSR_GPSR(IP3_29_27, BS_N), 903 PINMUX_IPSR_GPSR(IP3_29_27, DRACK0), 904 PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C), 905 PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C), 906 PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N), 907 PINMUX_IPSR_GPSR(IP3_30, RD_N), 908 PINMUX_IPSR_GPSR(IP3_30, ATACS11_N), 909 PINMUX_IPSR_GPSR(IP3_31, RD_WR_N), 910 PINMUX_IPSR_GPSR(IP3_31, ATAG1_N), 911 912 /* IPSR4 */ 913 PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0), 914 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1), 915 PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), 916 PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0), 917 PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16), 918 PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), 919 PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), 920 PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1), 921 PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17), 922 PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), 923 PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), 924 PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2), 925 PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18), 926 PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3), 927 PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19), 928 PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4), 929 PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20), 930 PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5), 931 PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21), 932 PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6), 933 PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22), 934 PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7), 935 PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23), 936 PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0), 937 PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8), 938 PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), 939 PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), 940 PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1), 941 PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9), 942 PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), 943 PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), 944 PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2), 945 PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10), 946 PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3), 947 PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11), 948 PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4), 949 PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12), 950 951 /* IPSR5 */ 952 PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5), 953 PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13), 954 PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6), 955 PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14), 956 PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7), 957 PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15), 958 PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0), 959 PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0), 960 PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), 961 PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), 962 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), 963 PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1), 964 PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1), 965 PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), 966 PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), 967 PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), 968 PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2), 969 PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2), 970 PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3), 971 PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3), 972 PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4), 973 PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4), 974 PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5), 975 PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5), 976 PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6), 977 PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6), 978 PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7), 979 PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7), 980 PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN), 981 PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS), 982 PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0), 983 PINMUX_IPSR_GPSR(IP5_27_26, QCLK), 984 PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1), 985 PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE), 986 PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC), 987 PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS), 988 989 /* IPSR6 */ 990 PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), 991 PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE), 992 PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), 993 PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE), 994 PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP), 995 PINMUX_IPSR_GPSR(IP6_5_4, QPOLA), 996 PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE), 997 PINMUX_IPSR_GPSR(IP6_7_6, QPOLB), 998 PINMUX_IPSR_GPSR(IP6_8, VI0_CLK), 999 PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK), 1000 PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0), 1001 PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV), 1002 PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1), 1003 PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0), 1004 PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2), 1005 PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1), 1006 PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3), 1007 PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2), 1008 PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4), 1009 PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3), 1010 PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5), 1011 PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4), 1012 PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6), 1013 PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5), 1014 PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7), 1015 PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6), 1016 PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB), 1017 PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0), 1018 PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), 1019 PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), 1020 PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7), 1021 PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD), 1022 PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0), 1023 PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), 1024 PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), 1025 PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER), 1026 PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N), 1027 PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), 1028 PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), 1029 PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), 1030 PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL), 1031 PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N), 1032 PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), 1033 PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), 1034 PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), 1035 PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN), 1036 PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0), 1037 PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0), 1038 PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), 1039 PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3), 1040 PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK), 1041 PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), 1042 1043 /* IPSR7 */ 1044 PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), 1045 PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1), 1046 PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), 1047 PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3), 1048 PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0), 1049 PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), 1050 PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0), 1051 PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2), 1052 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), 1053 PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), 1054 PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1), 1055 PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0), 1056 PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0), 1057 PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3), 1058 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), 1059 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), 1060 PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2), 1061 PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), 1062 PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0), 1063 PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4), 1064 PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), 1065 PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), 1066 PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3), 1067 PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), 1068 PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0), 1069 PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5), 1070 PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), 1071 PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), 1072 PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4), 1073 PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), 1074 PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0), 1075 PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6), 1076 PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), 1077 PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5), 1078 PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), 1079 PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0), 1080 PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7), 1081 PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), 1082 PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3), 1083 PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6), 1084 PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), 1085 PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0), 1086 PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0), 1087 PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), 1088 PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3), 1089 PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7), 1090 PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), 1091 PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0), 1092 PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1), 1093 PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), 1094 PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER), 1095 PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), 1096 PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0), 1097 PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2), 1098 PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), 1099 PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), 1100 PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK), 1101 PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), 1102 PINMUX_IPSR_GPSR(IP7_31, DREQ0_N), 1103 PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD), 1104 1105 /* IPSR8 */ 1106 PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0), 1107 PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3), 1108 PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), 1109 PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), 1110 PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC), 1111 PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), 1112 PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), 1113 PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4), 1114 PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), 1115 PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), 1116 PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO), 1117 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), 1118 PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), 1119 PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5), 1120 PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), 1121 PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), 1122 PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK), 1123 PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), 1124 PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N), 1125 PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6), 1126 PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), 1127 PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), 1128 PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC), 1129 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), 1130 PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N), 1131 PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7), 1132 PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), 1133 PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), 1134 PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT), 1135 PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), 1136 PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), 1137 PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), 1138 PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS), 1139 PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), 1140 PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0), 1141 PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), 1142 PINMUX_IPSR_GPSR(IP8_19_17, PWM5), 1143 PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1), 1144 PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK), 1145 PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), 1146 PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B), 1147 PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0), 1148 PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), 1149 PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0), 1150 PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0), 1151 PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE), 1152 PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), 1153 PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0), 1154 PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), 1155 PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B), 1156 PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0), 1157 PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), 1158 PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B), 1159 PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0), 1160 PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), 1161 PINMUX_IPSR_GPSR(IP8_28_26, IRQ5), 1162 PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1), 1163 PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), 1164 PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), 1165 PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD), 1166 PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), 1167 PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), 1168 PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2), 1169 PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), 1170 PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), 1171 1172 /* IPSR9 */ 1173 PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD), 1174 PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), 1175 PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), 1176 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3), 1177 PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), 1178 PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), 1179 PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK), 1180 PINMUX_IPSR_GPSR(IP9_5_3, IRQ0), 1181 PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), 1182 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4), 1183 PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C), 1184 PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC), 1185 PINMUX_IPSR_GPSR(IP9_8_6, PWM1), 1186 PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), 1187 PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5), 1188 PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), 1189 PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1), 1190 PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), 1191 PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), 1192 PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6), 1193 PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), 1194 PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2), 1195 PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), 1196 PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), 1197 PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7), 1198 PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), 1199 PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), 1200 PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0), 1201 PINMUX_IPSR_GPSR(IP9_16_15, PWM6), 1202 PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0), 1203 PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), 1204 PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0), 1205 PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1), 1206 PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1), 1207 PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK), 1208 PINMUX_IPSR_GPSR(IP9_21_19, PWM2), 1209 PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), 1210 PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2), 1211 PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), 1212 PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), 1213 PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), 1214 PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), 1215 PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), 1216 PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3), 1217 PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), 1218 PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), 1219 PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), 1220 PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), 1221 PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4), 1222 PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), 1223 PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), 1224 PINMUX_IPSR_GPSR(IP9_30_28, PWM3), 1225 PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0), 1226 PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5), 1227 PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), 1228 1229 /* IPSR10 */ 1230 PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), 1231 PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0), 1232 PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6), 1233 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), 1234 PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), 1235 PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0), 1236 PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7), 1237 PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), 1238 PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), 1239 PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0), 1240 PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0), 1241 PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), 1242 PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), 1243 PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0), 1244 PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1), 1245 PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), 1246 PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), 1247 PINMUX_IPSR_GPSR(IP10_14_12, IRQ1), 1248 PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2), 1249 PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), 1250 PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), 1251 PINMUX_IPSR_GPSR(IP10_17_15, IRQ2), 1252 PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), 1253 PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3), 1254 PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), 1255 PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), 1256 PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), 1257 PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), 1258 PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4), 1259 PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), 1260 PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), 1261 PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), 1262 PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), 1263 PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), 1264 PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5), 1265 PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), 1266 PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), 1267 PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0), 1268 PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), 1269 PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6), 1270 PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), 1271 PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), 1272 PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0), 1273 PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), 1274 PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7), 1275 PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), 1276 PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0), 1277 PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), 1278 PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN), 1279 1280 /* IPSR11 */ 1281 PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0), 1282 PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), 1283 PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), 1284 PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0), 1285 PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), 1286 PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), 1287 PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), 1288 PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1), 1289 PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0), 1290 PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), 1291 PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), 1292 PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0), 1293 PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), 1294 PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), 1295 PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), 1296 PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), 1297 PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), 1298 PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), 1299 PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1300 PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0), 1301 PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), 1302 PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2), 1303 PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP), 1304 PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0), 1305 PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), 1306 PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2), 1307 PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE), 1308 PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), 1309 PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), 1310 PINMUX_IPSR_GPSR(IP11_20_18, IRQ8), 1311 PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), 1312 PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3), 1313 PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129), 1314 PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), 1315 PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), 1316 PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), 1317 PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129), 1318 PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), 1319 PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), 1320 PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), 1321 PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0), 1322 PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), 1323 PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B), 1324 PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), 1325 1326 /* IPSR12 */ 1327 PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34), 1328 PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), 1329 PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), 1330 PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), 1331 PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1), 1332 PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34), 1333 PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), 1334 PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), 1335 PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), 1336 PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), 1337 PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1), 1338 PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3), 1339 PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), 1340 PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), 1341 PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), 1342 PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), 1343 PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N), 1344 PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0), 1345 PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK), 1346 PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), 1347 PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0), 1348 PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG), 1349 PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), 1350 PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), 1351 PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT), 1352 PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), 1353 PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), 1354 PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), 1355 PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B), 1356 PINMUX_IPSR_GPSR(IP12_17_15, IRQ9), 1357 PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), 1358 PINMUX_IPSR_GPSR(IP12_17_15, DACK2), 1359 PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), 1360 PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0), 1361 PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), 1362 PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2), 1363 PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK), 1364 PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), 1365 PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), 1366 PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0), 1367 PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), 1368 PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2), 1369 PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0), 1370 PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), 1371 PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), 1372 PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), 1373 PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), 1374 PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1), 1375 PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N), 1376 PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), 1377 PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0), 1378 PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), 1379 PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2), 1380 PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N), 1381 PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), 1382 1383 /* IPSR13 */ 1384 PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0), 1385 PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), 1386 PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), 1387 PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3), 1388 PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N), 1389 PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1), 1390 PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), 1391 PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), 1392 PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), 1393 PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4), 1394 PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N), 1395 PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), 1396 PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0), 1397 PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), 1398 PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B), 1399 PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5), 1400 PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1), 1401 PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), 1402 PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0), 1403 PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), 1404 PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), 1405 PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6), 1406 PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N), 1407 PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), 1408 PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), 1409 PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), 1410 PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), 1411 PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7), 1412 PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N), 1413 PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), 1414 PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), 1415 PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), 1416 PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), 1417 PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB), 1418 PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), 1419 PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), 1420 PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), 1421 PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), 1422 PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), 1423 PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD), 1424 PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), 1425 PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), 1426 PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1), 1427 PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), 1428 PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), 1429 PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), 1430 PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N), 1431 PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), 1432 PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), 1433 PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), 1434 PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), 1435 PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), 1436 PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N), 1437 PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), 1438 PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), 1439 }; 1440 1441 static const struct sh_pfc_pin pinmux_pins[] = { 1442 PINMUX_GPIO_GP_ALL(), 1443 }; 1444 1445 /* - Audio Clock ------------------------------------------------------------ */ 1446 static const unsigned int audio_clka_pins[] = { 1447 /* CLKA */ 1448 RCAR_GP_PIN(5, 20), 1449 }; 1450 static const unsigned int audio_clka_mux[] = { 1451 AUDIO_CLKA_MARK, 1452 }; 1453 static const unsigned int audio_clka_b_pins[] = { 1454 /* CLKA */ 1455 RCAR_GP_PIN(3, 25), 1456 }; 1457 static const unsigned int audio_clka_b_mux[] = { 1458 AUDIO_CLKA_B_MARK, 1459 }; 1460 static const unsigned int audio_clka_c_pins[] = { 1461 /* CLKA */ 1462 RCAR_GP_PIN(4, 20), 1463 }; 1464 static const unsigned int audio_clka_c_mux[] = { 1465 AUDIO_CLKA_C_MARK, 1466 }; 1467 static const unsigned int audio_clka_d_pins[] = { 1468 /* CLKA */ 1469 RCAR_GP_PIN(5, 0), 1470 }; 1471 static const unsigned int audio_clka_d_mux[] = { 1472 AUDIO_CLKA_D_MARK, 1473 }; 1474 static const unsigned int audio_clkb_pins[] = { 1475 /* CLKB */ 1476 RCAR_GP_PIN(5, 21), 1477 }; 1478 static const unsigned int audio_clkb_mux[] = { 1479 AUDIO_CLKB_MARK, 1480 }; 1481 static const unsigned int audio_clkb_b_pins[] = { 1482 /* CLKB */ 1483 RCAR_GP_PIN(3, 26), 1484 }; 1485 static const unsigned int audio_clkb_b_mux[] = { 1486 AUDIO_CLKB_B_MARK, 1487 }; 1488 static const unsigned int audio_clkb_c_pins[] = { 1489 /* CLKB */ 1490 RCAR_GP_PIN(4, 21), 1491 }; 1492 static const unsigned int audio_clkb_c_mux[] = { 1493 AUDIO_CLKB_C_MARK, 1494 }; 1495 static const unsigned int audio_clkc_pins[] = { 1496 /* CLKC */ 1497 RCAR_GP_PIN(5, 22), 1498 }; 1499 static const unsigned int audio_clkc_mux[] = { 1500 AUDIO_CLKC_MARK, 1501 }; 1502 static const unsigned int audio_clkc_b_pins[] = { 1503 /* CLKC */ 1504 RCAR_GP_PIN(3, 29), 1505 }; 1506 static const unsigned int audio_clkc_b_mux[] = { 1507 AUDIO_CLKC_B_MARK, 1508 }; 1509 static const unsigned int audio_clkc_c_pins[] = { 1510 /* CLKC */ 1511 RCAR_GP_PIN(4, 22), 1512 }; 1513 static const unsigned int audio_clkc_c_mux[] = { 1514 AUDIO_CLKC_C_MARK, 1515 }; 1516 static const unsigned int audio_clkout_pins[] = { 1517 /* CLKOUT */ 1518 RCAR_GP_PIN(5, 23), 1519 }; 1520 static const unsigned int audio_clkout_mux[] = { 1521 AUDIO_CLKOUT_MARK, 1522 }; 1523 static const unsigned int audio_clkout_b_pins[] = { 1524 /* CLKOUT */ 1525 RCAR_GP_PIN(3, 12), 1526 }; 1527 static const unsigned int audio_clkout_b_mux[] = { 1528 AUDIO_CLKOUT_B_MARK, 1529 }; 1530 static const unsigned int audio_clkout_c_pins[] = { 1531 /* CLKOUT */ 1532 RCAR_GP_PIN(4, 23), 1533 }; 1534 static const unsigned int audio_clkout_c_mux[] = { 1535 AUDIO_CLKOUT_C_MARK, 1536 }; 1537 /* - AVB -------------------------------------------------------------------- */ 1538 static const unsigned int avb_link_pins[] = { 1539 RCAR_GP_PIN(3, 26), 1540 }; 1541 static const unsigned int avb_link_mux[] = { 1542 AVB_LINK_MARK, 1543 }; 1544 static const unsigned int avb_magic_pins[] = { 1545 RCAR_GP_PIN(3, 27), 1546 }; 1547 static const unsigned int avb_magic_mux[] = { 1548 AVB_MAGIC_MARK, 1549 }; 1550 static const unsigned int avb_phy_int_pins[] = { 1551 RCAR_GP_PIN(3, 28), 1552 }; 1553 static const unsigned int avb_phy_int_mux[] = { 1554 AVB_PHY_INT_MARK, 1555 }; 1556 static const unsigned int avb_mdio_pins[] = { 1557 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 1558 }; 1559 static const unsigned int avb_mdio_mux[] = { 1560 AVB_MDC_MARK, AVB_MDIO_MARK, 1561 }; 1562 static const unsigned int avb_mii_pins[] = { 1563 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 1564 RCAR_GP_PIN(3, 17), 1565 1566 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), 1567 RCAR_GP_PIN(3, 5), 1568 1569 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 1570 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), 1571 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11), 1572 }; 1573 static const unsigned int avb_mii_mux[] = { 1574 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1575 AVB_TXD3_MARK, 1576 1577 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1578 AVB_RXD3_MARK, 1579 1580 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1581 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, 1582 AVB_TX_CLK_MARK, AVB_COL_MARK, 1583 }; 1584 static const unsigned int avb_gmii_pins[] = { 1585 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 1586 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 1587 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 1588 1589 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), 1590 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1591 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1592 1593 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 1594 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30), 1595 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13), 1596 RCAR_GP_PIN(3, 11), 1597 }; 1598 static const unsigned int avb_gmii_mux[] = { 1599 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1600 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1601 AVB_TXD6_MARK, AVB_TXD7_MARK, 1602 1603 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1604 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1605 AVB_RXD6_MARK, AVB_RXD7_MARK, 1606 1607 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1608 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1609 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1610 AVB_COL_MARK, 1611 }; 1612 /* - DU --------------------------------------------------------------------- */ 1613 static const unsigned int du0_rgb666_pins[] = { 1614 /* R[7:2], G[7:2], B[7:2] */ 1615 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5), 1616 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 1617 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 1618 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1619 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), 1620 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18), 1621 }; 1622 static const unsigned int du0_rgb666_mux[] = { 1623 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1624 DU0_DR3_MARK, DU0_DR2_MARK, 1625 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, 1626 DU0_DG3_MARK, DU0_DG2_MARK, 1627 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, 1628 DU0_DB3_MARK, DU0_DB2_MARK, 1629 }; 1630 static const unsigned int du0_rgb888_pins[] = { 1631 /* R[7:0], G[7:0], B[7:0] */ 1632 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5), 1633 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 1634 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0), 1635 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 1636 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1637 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8), 1638 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), 1639 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18), 1640 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16), 1641 }; 1642 static const unsigned int du0_rgb888_mux[] = { 1643 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, 1644 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK, 1645 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, 1646 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK, 1647 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, 1648 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, 1649 }; 1650 static const unsigned int du0_clk0_out_pins[] = { 1651 /* DOTCLKOUT0 */ 1652 RCAR_GP_PIN(2, 25), 1653 }; 1654 static const unsigned int du0_clk0_out_mux[] = { 1655 DU0_DOTCLKOUT0_MARK 1656 }; 1657 static const unsigned int du0_clk1_out_pins[] = { 1658 /* DOTCLKOUT1 */ 1659 RCAR_GP_PIN(2, 26), 1660 }; 1661 static const unsigned int du0_clk1_out_mux[] = { 1662 DU0_DOTCLKOUT1_MARK 1663 }; 1664 static const unsigned int du0_clk_in_pins[] = { 1665 /* CLKIN */ 1666 RCAR_GP_PIN(2, 24), 1667 }; 1668 static const unsigned int du0_clk_in_mux[] = { 1669 DU0_DOTCLKIN_MARK 1670 }; 1671 static const unsigned int du0_sync_pins[] = { 1672 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 1673 RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27), 1674 }; 1675 static const unsigned int du0_sync_mux[] = { 1676 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK 1677 }; 1678 static const unsigned int du0_oddf_pins[] = { 1679 /* EXODDF/ODDF/DISP/CDE */ 1680 RCAR_GP_PIN(2, 29), 1681 }; 1682 static const unsigned int du0_oddf_mux[] = { 1683 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, 1684 }; 1685 static const unsigned int du0_cde_pins[] = { 1686 /* CDE */ 1687 RCAR_GP_PIN(2, 31), 1688 }; 1689 static const unsigned int du0_cde_mux[] = { 1690 DU0_CDE_MARK, 1691 }; 1692 static const unsigned int du0_disp_pins[] = { 1693 /* DISP */ 1694 RCAR_GP_PIN(2, 30), 1695 }; 1696 static const unsigned int du0_disp_mux[] = { 1697 DU0_DISP_MARK 1698 }; 1699 static const unsigned int du1_rgb666_pins[] = { 1700 /* R[7:2], G[7:2], B[7:2] */ 1701 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), 1702 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1703 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 1704 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), 1705 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), 1706 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), 1707 }; 1708 static const unsigned int du1_rgb666_mux[] = { 1709 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1710 DU1_DR3_MARK, DU1_DR2_MARK, 1711 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1712 DU1_DG3_MARK, DU1_DG2_MARK, 1713 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1714 DU1_DB3_MARK, DU1_DB2_MARK, 1715 }; 1716 static const unsigned int du1_rgb888_pins[] = { 1717 /* R[7:0], G[7:0], B[7:0] */ 1718 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), 1719 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1720 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), 1721 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 1722 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), 1723 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), 1724 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), 1725 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), 1726 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1727 }; 1728 static const unsigned int du1_rgb888_mux[] = { 1729 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, 1730 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, 1731 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, 1732 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, 1733 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1734 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, 1735 }; 1736 static const unsigned int du1_clk0_out_pins[] = { 1737 /* DOTCLKOUT0 */ 1738 RCAR_GP_PIN(4, 25), 1739 }; 1740 static const unsigned int du1_clk0_out_mux[] = { 1741 DU1_DOTCLKOUT0_MARK 1742 }; 1743 static const unsigned int du1_clk1_out_pins[] = { 1744 /* DOTCLKOUT1 */ 1745 RCAR_GP_PIN(4, 26), 1746 }; 1747 static const unsigned int du1_clk1_out_mux[] = { 1748 DU1_DOTCLKOUT1_MARK 1749 }; 1750 static const unsigned int du1_clk_in_pins[] = { 1751 /* DOTCLKIN */ 1752 RCAR_GP_PIN(4, 24), 1753 }; 1754 static const unsigned int du1_clk_in_mux[] = { 1755 DU1_DOTCLKIN_MARK 1756 }; 1757 static const unsigned int du1_sync_pins[] = { 1758 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 1759 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27), 1760 }; 1761 static const unsigned int du1_sync_mux[] = { 1762 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK 1763 }; 1764 static const unsigned int du1_oddf_pins[] = { 1765 /* EXODDF/ODDF/DISP/CDE */ 1766 RCAR_GP_PIN(4, 29), 1767 }; 1768 static const unsigned int du1_oddf_mux[] = { 1769 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 1770 }; 1771 static const unsigned int du1_cde_pins[] = { 1772 /* CDE */ 1773 RCAR_GP_PIN(4, 31), 1774 }; 1775 static const unsigned int du1_cde_mux[] = { 1776 DU1_CDE_MARK 1777 }; 1778 static const unsigned int du1_disp_pins[] = { 1779 /* DISP */ 1780 RCAR_GP_PIN(4, 30), 1781 }; 1782 static const unsigned int du1_disp_mux[] = { 1783 DU1_DISP_MARK 1784 }; 1785 /* - ETH -------------------------------------------------------------------- */ 1786 static const unsigned int eth_link_pins[] = { 1787 /* LINK */ 1788 RCAR_GP_PIN(3, 18), 1789 }; 1790 static const unsigned int eth_link_mux[] = { 1791 ETH_LINK_MARK, 1792 }; 1793 static const unsigned int eth_magic_pins[] = { 1794 /* MAGIC */ 1795 RCAR_GP_PIN(3, 22), 1796 }; 1797 static const unsigned int eth_magic_mux[] = { 1798 ETH_MAGIC_MARK, 1799 }; 1800 static const unsigned int eth_mdio_pins[] = { 1801 /* MDC, MDIO */ 1802 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13), 1803 }; 1804 static const unsigned int eth_mdio_mux[] = { 1805 ETH_MDC_MARK, ETH_MDIO_MARK, 1806 }; 1807 static const unsigned int eth_rmii_pins[] = { 1808 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 1809 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15), 1810 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20), 1811 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19), 1812 }; 1813 static const unsigned int eth_rmii_mux[] = { 1814 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 1815 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 1816 }; 1817 static const unsigned int eth_link_b_pins[] = { 1818 /* LINK */ 1819 RCAR_GP_PIN(5, 15), 1820 }; 1821 static const unsigned int eth_link_b_mux[] = { 1822 ETH_LINK_B_MARK, 1823 }; 1824 static const unsigned int eth_magic_b_pins[] = { 1825 /* MAGIC */ 1826 RCAR_GP_PIN(5, 19), 1827 }; 1828 static const unsigned int eth_magic_b_mux[] = { 1829 ETH_MAGIC_B_MARK, 1830 }; 1831 static const unsigned int eth_mdio_b_pins[] = { 1832 /* MDC, MDIO */ 1833 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10), 1834 }; 1835 static const unsigned int eth_mdio_b_mux[] = { 1836 ETH_MDC_B_MARK, ETH_MDIO_B_MARK, 1837 }; 1838 static const unsigned int eth_rmii_b_pins[] = { 1839 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 1840 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12), 1841 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17), 1842 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16), 1843 }; 1844 static const unsigned int eth_rmii_b_mux[] = { 1845 ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK, 1846 ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK, 1847 }; 1848 /* - HSCIF0 ----------------------------------------------------------------- */ 1849 static const unsigned int hscif0_data_pins[] = { 1850 /* RX, TX */ 1851 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 1852 }; 1853 static const unsigned int hscif0_data_mux[] = { 1854 HSCIF0_HRX_MARK, HSCIF0_HTX_MARK, 1855 }; 1856 static const unsigned int hscif0_clk_pins[] = { 1857 /* SCK */ 1858 RCAR_GP_PIN(3, 29), 1859 }; 1860 static const unsigned int hscif0_clk_mux[] = { 1861 HSCIF0_HSCK_MARK, 1862 }; 1863 static const unsigned int hscif0_ctrl_pins[] = { 1864 /* RTS, CTS */ 1865 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), 1866 }; 1867 static const unsigned int hscif0_ctrl_mux[] = { 1868 HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK, 1869 }; 1870 static const unsigned int hscif0_data_b_pins[] = { 1871 /* RX, TX */ 1872 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31), 1873 }; 1874 static const unsigned int hscif0_data_b_mux[] = { 1875 HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK, 1876 }; 1877 static const unsigned int hscif0_clk_b_pins[] = { 1878 /* SCK */ 1879 RCAR_GP_PIN(1, 0), 1880 }; 1881 static const unsigned int hscif0_clk_b_mux[] = { 1882 HSCIF0_HSCK_B_MARK, 1883 }; 1884 /* - HSCIF1 ----------------------------------------------------------------- */ 1885 static const unsigned int hscif1_data_pins[] = { 1886 /* RX, TX */ 1887 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 1888 }; 1889 static const unsigned int hscif1_data_mux[] = { 1890 HSCIF1_HRX_MARK, HSCIF1_HTX_MARK, 1891 }; 1892 static const unsigned int hscif1_clk_pins[] = { 1893 /* SCK */ 1894 RCAR_GP_PIN(4, 10), 1895 }; 1896 static const unsigned int hscif1_clk_mux[] = { 1897 HSCIF1_HSCK_MARK, 1898 }; 1899 static const unsigned int hscif1_ctrl_pins[] = { 1900 /* RTS, CTS */ 1901 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), 1902 }; 1903 static const unsigned int hscif1_ctrl_mux[] = { 1904 HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK, 1905 }; 1906 static const unsigned int hscif1_data_b_pins[] = { 1907 /* RX, TX */ 1908 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 1909 }; 1910 static const unsigned int hscif1_data_b_mux[] = { 1911 HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK, 1912 }; 1913 static const unsigned int hscif1_ctrl_b_pins[] = { 1914 /* RTS, CTS */ 1915 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 1916 }; 1917 static const unsigned int hscif1_ctrl_b_mux[] = { 1918 HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK, 1919 }; 1920 /* - HSCIF2 ----------------------------------------------------------------- */ 1921 static const unsigned int hscif2_data_pins[] = { 1922 /* RX, TX */ 1923 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 1924 }; 1925 static const unsigned int hscif2_data_mux[] = { 1926 HSCIF2_HRX_MARK, HSCIF2_HTX_MARK, 1927 }; 1928 static const unsigned int hscif2_clk_pins[] = { 1929 /* SCK */ 1930 RCAR_GP_PIN(0, 10), 1931 }; 1932 static const unsigned int hscif2_clk_mux[] = { 1933 HSCIF2_HSCK_MARK, 1934 }; 1935 static const unsigned int hscif2_ctrl_pins[] = { 1936 /* RTS, CTS */ 1937 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), 1938 }; 1939 static const unsigned int hscif2_ctrl_mux[] = { 1940 HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK, 1941 }; 1942 /* - I2C0 ------------------------------------------------------------------- */ 1943 static const unsigned int i2c0_pins[] = { 1944 /* SCL, SDA */ 1945 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 1946 }; 1947 static const unsigned int i2c0_mux[] = { 1948 I2C0_SCL_MARK, I2C0_SDA_MARK, 1949 }; 1950 static const unsigned int i2c0_b_pins[] = { 1951 /* SCL, SDA */ 1952 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), 1953 }; 1954 static const unsigned int i2c0_b_mux[] = { 1955 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, 1956 }; 1957 static const unsigned int i2c0_c_pins[] = { 1958 /* SCL, SDA */ 1959 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), 1960 }; 1961 static const unsigned int i2c0_c_mux[] = { 1962 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, 1963 }; 1964 static const unsigned int i2c0_d_pins[] = { 1965 /* SCL, SDA */ 1966 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 1967 }; 1968 static const unsigned int i2c0_d_mux[] = { 1969 I2C0_SCL_D_MARK, I2C0_SDA_D_MARK, 1970 }; 1971 static const unsigned int i2c0_e_pins[] = { 1972 /* SCL, SDA */ 1973 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 1974 }; 1975 static const unsigned int i2c0_e_mux[] = { 1976 I2C0_SCL_E_MARK, I2C0_SDA_E_MARK, 1977 }; 1978 /* - I2C1 ------------------------------------------------------------------- */ 1979 static const unsigned int i2c1_pins[] = { 1980 /* SCL, SDA */ 1981 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 1982 }; 1983 static const unsigned int i2c1_mux[] = { 1984 I2C1_SCL_MARK, I2C1_SDA_MARK, 1985 }; 1986 static const unsigned int i2c1_b_pins[] = { 1987 /* SCL, SDA */ 1988 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 1989 }; 1990 static const unsigned int i2c1_b_mux[] = { 1991 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 1992 }; 1993 static const unsigned int i2c1_c_pins[] = { 1994 /* SCL, SDA */ 1995 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 1996 }; 1997 static const unsigned int i2c1_c_mux[] = { 1998 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 1999 }; 2000 static const unsigned int i2c1_d_pins[] = { 2001 /* SCL, SDA */ 2002 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), 2003 }; 2004 static const unsigned int i2c1_d_mux[] = { 2005 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, 2006 }; 2007 static const unsigned int i2c1_e_pins[] = { 2008 /* SCL, SDA */ 2009 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 2010 }; 2011 static const unsigned int i2c1_e_mux[] = { 2012 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, 2013 }; 2014 /* - I2C2 ------------------------------------------------------------------- */ 2015 static const unsigned int i2c2_pins[] = { 2016 /* SCL, SDA */ 2017 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 2018 }; 2019 static const unsigned int i2c2_mux[] = { 2020 I2C2_SCL_MARK, I2C2_SDA_MARK, 2021 }; 2022 static const unsigned int i2c2_b_pins[] = { 2023 /* SCL, SDA */ 2024 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2025 }; 2026 static const unsigned int i2c2_b_mux[] = { 2027 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2028 }; 2029 static const unsigned int i2c2_c_pins[] = { 2030 /* SCL, SDA */ 2031 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 2032 }; 2033 static const unsigned int i2c2_c_mux[] = { 2034 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2035 }; 2036 static const unsigned int i2c2_d_pins[] = { 2037 /* SCL, SDA */ 2038 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 2039 }; 2040 static const unsigned int i2c2_d_mux[] = { 2041 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2042 }; 2043 static const unsigned int i2c2_e_pins[] = { 2044 /* SCL, SDA */ 2045 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2046 }; 2047 static const unsigned int i2c2_e_mux[] = { 2048 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, 2049 }; 2050 /* - I2C3 ------------------------------------------------------------------- */ 2051 static const unsigned int i2c3_pins[] = { 2052 /* SCL, SDA */ 2053 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 2054 }; 2055 static const unsigned int i2c3_mux[] = { 2056 I2C3_SCL_MARK, I2C3_SDA_MARK, 2057 }; 2058 static const unsigned int i2c3_b_pins[] = { 2059 /* SCL, SDA */ 2060 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), 2061 }; 2062 static const unsigned int i2c3_b_mux[] = { 2063 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, 2064 }; 2065 static const unsigned int i2c3_c_pins[] = { 2066 /* SCL, SDA */ 2067 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 2068 }; 2069 static const unsigned int i2c3_c_mux[] = { 2070 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, 2071 }; 2072 static const unsigned int i2c3_d_pins[] = { 2073 /* SCL, SDA */ 2074 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 2075 }; 2076 static const unsigned int i2c3_d_mux[] = { 2077 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, 2078 }; 2079 static const unsigned int i2c3_e_pins[] = { 2080 /* SCL, SDA */ 2081 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 2082 }; 2083 static const unsigned int i2c3_e_mux[] = { 2084 I2C3_SCL_E_MARK, I2C3_SDA_E_MARK, 2085 }; 2086 /* - I2C4 ------------------------------------------------------------------- */ 2087 static const unsigned int i2c4_pins[] = { 2088 /* SCL, SDA */ 2089 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 2090 }; 2091 static const unsigned int i2c4_mux[] = { 2092 I2C4_SCL_MARK, I2C4_SDA_MARK, 2093 }; 2094 static const unsigned int i2c4_b_pins[] = { 2095 /* SCL, SDA */ 2096 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 2097 }; 2098 static const unsigned int i2c4_b_mux[] = { 2099 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, 2100 }; 2101 static const unsigned int i2c4_c_pins[] = { 2102 /* SCL, SDA */ 2103 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2104 }; 2105 static const unsigned int i2c4_c_mux[] = { 2106 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, 2107 }; 2108 static const unsigned int i2c4_d_pins[] = { 2109 /* SCL, SDA */ 2110 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 2111 }; 2112 static const unsigned int i2c4_d_mux[] = { 2113 I2C4_SCL_D_MARK, I2C4_SDA_D_MARK, 2114 }; 2115 static const unsigned int i2c4_e_pins[] = { 2116 /* SCL, SDA */ 2117 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), 2118 }; 2119 static const unsigned int i2c4_e_mux[] = { 2120 I2C4_SCL_E_MARK, I2C4_SDA_E_MARK, 2121 }; 2122 /* - INTC ------------------------------------------------------------------- */ 2123 static const unsigned int intc_irq0_pins[] = { 2124 /* IRQ0 */ 2125 RCAR_GP_PIN(4, 4), 2126 }; 2127 static const unsigned int intc_irq0_mux[] = { 2128 IRQ0_MARK, 2129 }; 2130 static const unsigned int intc_irq1_pins[] = { 2131 /* IRQ1 */ 2132 RCAR_GP_PIN(4, 18), 2133 }; 2134 static const unsigned int intc_irq1_mux[] = { 2135 IRQ1_MARK, 2136 }; 2137 static const unsigned int intc_irq2_pins[] = { 2138 /* IRQ2 */ 2139 RCAR_GP_PIN(4, 19), 2140 }; 2141 static const unsigned int intc_irq2_mux[] = { 2142 IRQ2_MARK, 2143 }; 2144 static const unsigned int intc_irq3_pins[] = { 2145 /* IRQ3 */ 2146 RCAR_GP_PIN(0, 7), 2147 }; 2148 static const unsigned int intc_irq3_mux[] = { 2149 IRQ3_MARK, 2150 }; 2151 static const unsigned int intc_irq4_pins[] = { 2152 /* IRQ4 */ 2153 RCAR_GP_PIN(0, 0), 2154 }; 2155 static const unsigned int intc_irq4_mux[] = { 2156 IRQ4_MARK, 2157 }; 2158 static const unsigned int intc_irq5_pins[] = { 2159 /* IRQ5 */ 2160 RCAR_GP_PIN(4, 1), 2161 }; 2162 static const unsigned int intc_irq5_mux[] = { 2163 IRQ5_MARK, 2164 }; 2165 static const unsigned int intc_irq6_pins[] = { 2166 /* IRQ6 */ 2167 RCAR_GP_PIN(0, 10), 2168 }; 2169 static const unsigned int intc_irq6_mux[] = { 2170 IRQ6_MARK, 2171 }; 2172 static const unsigned int intc_irq7_pins[] = { 2173 /* IRQ7 */ 2174 RCAR_GP_PIN(6, 15), 2175 }; 2176 static const unsigned int intc_irq7_mux[] = { 2177 IRQ7_MARK, 2178 }; 2179 static const unsigned int intc_irq8_pins[] = { 2180 /* IRQ8 */ 2181 RCAR_GP_PIN(5, 0), 2182 }; 2183 static const unsigned int intc_irq8_mux[] = { 2184 IRQ8_MARK, 2185 }; 2186 static const unsigned int intc_irq9_pins[] = { 2187 /* IRQ9 */ 2188 RCAR_GP_PIN(5, 10), 2189 }; 2190 static const unsigned int intc_irq9_mux[] = { 2191 IRQ9_MARK, 2192 }; 2193 /* - MMCIF ------------------------------------------------------------------ */ 2194 static const unsigned int mmc_data1_pins[] = { 2195 /* D[0] */ 2196 RCAR_GP_PIN(6, 18), 2197 }; 2198 static const unsigned int mmc_data1_mux[] = { 2199 MMC_D0_MARK, 2200 }; 2201 static const unsigned int mmc_data4_pins[] = { 2202 /* D[0:3] */ 2203 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2204 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2205 }; 2206 static const unsigned int mmc_data4_mux[] = { 2207 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2208 }; 2209 static const unsigned int mmc_data8_pins[] = { 2210 /* D[0:7] */ 2211 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 2212 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 2213 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), 2214 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2215 }; 2216 static const unsigned int mmc_data8_mux[] = { 2217 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2218 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, 2219 }; 2220 static const unsigned int mmc_ctrl_pins[] = { 2221 /* CLK, CMD */ 2222 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 2223 }; 2224 static const unsigned int mmc_ctrl_mux[] = { 2225 MMC_CLK_MARK, MMC_CMD_MARK, 2226 }; 2227 /* - MSIOF0 ----------------------------------------------------------------- */ 2228 static const unsigned int msiof0_clk_pins[] = { 2229 /* SCK */ 2230 RCAR_GP_PIN(4, 4), 2231 }; 2232 static const unsigned int msiof0_clk_mux[] = { 2233 MSIOF0_SCK_MARK, 2234 }; 2235 static const unsigned int msiof0_sync_pins[] = { 2236 /* SYNC */ 2237 RCAR_GP_PIN(4, 5), 2238 }; 2239 static const unsigned int msiof0_sync_mux[] = { 2240 MSIOF0_SYNC_MARK, 2241 }; 2242 static const unsigned int msiof0_ss1_pins[] = { 2243 /* SS1 */ 2244 RCAR_GP_PIN(4, 6), 2245 }; 2246 static const unsigned int msiof0_ss1_mux[] = { 2247 MSIOF0_SS1_MARK, 2248 }; 2249 static const unsigned int msiof0_ss2_pins[] = { 2250 /* SS2 */ 2251 RCAR_GP_PIN(4, 7), 2252 }; 2253 static const unsigned int msiof0_ss2_mux[] = { 2254 MSIOF0_SS2_MARK, 2255 }; 2256 static const unsigned int msiof0_rx_pins[] = { 2257 /* RXD */ 2258 RCAR_GP_PIN(4, 2), 2259 }; 2260 static const unsigned int msiof0_rx_mux[] = { 2261 MSIOF0_RXD_MARK, 2262 }; 2263 static const unsigned int msiof0_tx_pins[] = { 2264 /* TXD */ 2265 RCAR_GP_PIN(4, 3), 2266 }; 2267 static const unsigned int msiof0_tx_mux[] = { 2268 MSIOF0_TXD_MARK, 2269 }; 2270 /* - MSIOF1 ----------------------------------------------------------------- */ 2271 static const unsigned int msiof1_clk_pins[] = { 2272 /* SCK */ 2273 RCAR_GP_PIN(0, 26), 2274 }; 2275 static const unsigned int msiof1_clk_mux[] = { 2276 MSIOF1_SCK_MARK, 2277 }; 2278 static const unsigned int msiof1_sync_pins[] = { 2279 /* SYNC */ 2280 RCAR_GP_PIN(0, 27), 2281 }; 2282 static const unsigned int msiof1_sync_mux[] = { 2283 MSIOF1_SYNC_MARK, 2284 }; 2285 static const unsigned int msiof1_ss1_pins[] = { 2286 /* SS1 */ 2287 RCAR_GP_PIN(0, 28), 2288 }; 2289 static const unsigned int msiof1_ss1_mux[] = { 2290 MSIOF1_SS1_MARK, 2291 }; 2292 static const unsigned int msiof1_ss2_pins[] = { 2293 /* SS2 */ 2294 RCAR_GP_PIN(0, 29), 2295 }; 2296 static const unsigned int msiof1_ss2_mux[] = { 2297 MSIOF1_SS2_MARK, 2298 }; 2299 static const unsigned int msiof1_rx_pins[] = { 2300 /* RXD */ 2301 RCAR_GP_PIN(0, 24), 2302 }; 2303 static const unsigned int msiof1_rx_mux[] = { 2304 MSIOF1_RXD_MARK, 2305 }; 2306 static const unsigned int msiof1_tx_pins[] = { 2307 /* TXD */ 2308 RCAR_GP_PIN(0, 25), 2309 }; 2310 static const unsigned int msiof1_tx_mux[] = { 2311 MSIOF1_TXD_MARK, 2312 }; 2313 static const unsigned int msiof1_clk_b_pins[] = { 2314 /* SCK */ 2315 RCAR_GP_PIN(5, 3), 2316 }; 2317 static const unsigned int msiof1_clk_b_mux[] = { 2318 MSIOF1_SCK_B_MARK, 2319 }; 2320 static const unsigned int msiof1_sync_b_pins[] = { 2321 /* SYNC */ 2322 RCAR_GP_PIN(5, 4), 2323 }; 2324 static const unsigned int msiof1_sync_b_mux[] = { 2325 MSIOF1_SYNC_B_MARK, 2326 }; 2327 static const unsigned int msiof1_ss1_b_pins[] = { 2328 /* SS1 */ 2329 RCAR_GP_PIN(5, 5), 2330 }; 2331 static const unsigned int msiof1_ss1_b_mux[] = { 2332 MSIOF1_SS1_B_MARK, 2333 }; 2334 static const unsigned int msiof1_ss2_b_pins[] = { 2335 /* SS2 */ 2336 RCAR_GP_PIN(5, 6), 2337 }; 2338 static const unsigned int msiof1_ss2_b_mux[] = { 2339 MSIOF1_SS2_B_MARK, 2340 }; 2341 static const unsigned int msiof1_rx_b_pins[] = { 2342 /* RXD */ 2343 RCAR_GP_PIN(5, 1), 2344 }; 2345 static const unsigned int msiof1_rx_b_mux[] = { 2346 MSIOF1_RXD_B_MARK, 2347 }; 2348 static const unsigned int msiof1_tx_b_pins[] = { 2349 /* TXD */ 2350 RCAR_GP_PIN(5, 2), 2351 }; 2352 static const unsigned int msiof1_tx_b_mux[] = { 2353 MSIOF1_TXD_B_MARK, 2354 }; 2355 /* - MSIOF2 ----------------------------------------------------------------- */ 2356 static const unsigned int msiof2_clk_pins[] = { 2357 /* SCK */ 2358 RCAR_GP_PIN(1, 0), 2359 }; 2360 static const unsigned int msiof2_clk_mux[] = { 2361 MSIOF2_SCK_MARK, 2362 }; 2363 static const unsigned int msiof2_sync_pins[] = { 2364 /* SYNC */ 2365 RCAR_GP_PIN(1, 1), 2366 }; 2367 static const unsigned int msiof2_sync_mux[] = { 2368 MSIOF2_SYNC_MARK, 2369 }; 2370 static const unsigned int msiof2_ss1_pins[] = { 2371 /* SS1 */ 2372 RCAR_GP_PIN(1, 2), 2373 }; 2374 static const unsigned int msiof2_ss1_mux[] = { 2375 MSIOF2_SS1_MARK, 2376 }; 2377 static const unsigned int msiof2_ss2_pins[] = { 2378 /* SS2 */ 2379 RCAR_GP_PIN(1, 3), 2380 }; 2381 static const unsigned int msiof2_ss2_mux[] = { 2382 MSIOF2_SS2_MARK, 2383 }; 2384 static const unsigned int msiof2_rx_pins[] = { 2385 /* RXD */ 2386 RCAR_GP_PIN(0, 30), 2387 }; 2388 static const unsigned int msiof2_rx_mux[] = { 2389 MSIOF2_RXD_MARK, 2390 }; 2391 static const unsigned int msiof2_tx_pins[] = { 2392 /* TXD */ 2393 RCAR_GP_PIN(0, 31), 2394 }; 2395 static const unsigned int msiof2_tx_mux[] = { 2396 MSIOF2_TXD_MARK, 2397 }; 2398 static const unsigned int msiof2_clk_b_pins[] = { 2399 /* SCK */ 2400 RCAR_GP_PIN(3, 15), 2401 }; 2402 static const unsigned int msiof2_clk_b_mux[] = { 2403 MSIOF2_SCK_B_MARK, 2404 }; 2405 static const unsigned int msiof2_sync_b_pins[] = { 2406 /* SYNC */ 2407 RCAR_GP_PIN(3, 16), 2408 }; 2409 static const unsigned int msiof2_sync_b_mux[] = { 2410 MSIOF2_SYNC_B_MARK, 2411 }; 2412 static const unsigned int msiof2_ss1_b_pins[] = { 2413 /* SS1 */ 2414 RCAR_GP_PIN(3, 17), 2415 }; 2416 static const unsigned int msiof2_ss1_b_mux[] = { 2417 MSIOF2_SS1_B_MARK, 2418 }; 2419 static const unsigned int msiof2_ss2_b_pins[] = { 2420 /* SS2 */ 2421 RCAR_GP_PIN(3, 18), 2422 }; 2423 static const unsigned int msiof2_ss2_b_mux[] = { 2424 MSIOF2_SS2_B_MARK, 2425 }; 2426 static const unsigned int msiof2_rx_b_pins[] = { 2427 /* RXD */ 2428 RCAR_GP_PIN(3, 13), 2429 }; 2430 static const unsigned int msiof2_rx_b_mux[] = { 2431 MSIOF2_RXD_B_MARK, 2432 }; 2433 static const unsigned int msiof2_tx_b_pins[] = { 2434 /* TXD */ 2435 RCAR_GP_PIN(3, 14), 2436 }; 2437 static const unsigned int msiof2_tx_b_mux[] = { 2438 MSIOF2_TXD_B_MARK, 2439 }; 2440 /* - QSPI ------------------------------------------------------------------- */ 2441 static const unsigned int qspi_ctrl_pins[] = { 2442 /* SPCLK, SSL */ 2443 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 2444 }; 2445 static const unsigned int qspi_ctrl_mux[] = { 2446 SPCLK_MARK, SSL_MARK, 2447 }; 2448 static const unsigned int qspi_data2_pins[] = { 2449 /* MOSI_IO0, MISO_IO1 */ 2450 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 2451 }; 2452 static const unsigned int qspi_data2_mux[] = { 2453 MOSI_IO0_MARK, MISO_IO1_MARK, 2454 }; 2455 static const unsigned int qspi_data4_pins[] = { 2456 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2457 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 2458 RCAR_GP_PIN(1, 8), 2459 }; 2460 static const unsigned int qspi_data4_mux[] = { 2461 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 2462 }; 2463 /* - SCIF0 ------------------------------------------------------------------ */ 2464 static const unsigned int scif0_data_pins[] = { 2465 /* RX, TX */ 2466 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2467 }; 2468 static const unsigned int scif0_data_mux[] = { 2469 SCIF0_RXD_MARK, SCIF0_TXD_MARK, 2470 }; 2471 static const unsigned int scif0_data_b_pins[] = { 2472 /* RX, TX */ 2473 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), 2474 }; 2475 static const unsigned int scif0_data_b_mux[] = { 2476 SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK, 2477 }; 2478 static const unsigned int scif0_data_c_pins[] = { 2479 /* RX, TX */ 2480 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2481 }; 2482 static const unsigned int scif0_data_c_mux[] = { 2483 SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK, 2484 }; 2485 static const unsigned int scif0_data_d_pins[] = { 2486 /* RX, TX */ 2487 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 2488 }; 2489 static const unsigned int scif0_data_d_mux[] = { 2490 SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK, 2491 }; 2492 /* - SCIF1 ------------------------------------------------------------------ */ 2493 static const unsigned int scif1_data_pins[] = { 2494 /* RX, TX */ 2495 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 2496 }; 2497 static const unsigned int scif1_data_mux[] = { 2498 SCIF1_RXD_MARK, SCIF1_TXD_MARK, 2499 }; 2500 static const unsigned int scif1_clk_pins[] = { 2501 /* SCK */ 2502 RCAR_GP_PIN(4, 13), 2503 }; 2504 static const unsigned int scif1_clk_mux[] = { 2505 SCIF1_SCK_MARK, 2506 }; 2507 static const unsigned int scif1_data_b_pins[] = { 2508 /* RX, TX */ 2509 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), 2510 }; 2511 static const unsigned int scif1_data_b_mux[] = { 2512 SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK, 2513 }; 2514 static const unsigned int scif1_clk_b_pins[] = { 2515 /* SCK */ 2516 RCAR_GP_PIN(5, 10), 2517 }; 2518 static const unsigned int scif1_clk_b_mux[] = { 2519 SCIF1_SCK_B_MARK, 2520 }; 2521 static const unsigned int scif1_data_c_pins[] = { 2522 /* RX, TX */ 2523 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), 2524 }; 2525 static const unsigned int scif1_data_c_mux[] = { 2526 SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK, 2527 }; 2528 static const unsigned int scif1_clk_c_pins[] = { 2529 /* SCK */ 2530 RCAR_GP_PIN(0, 10), 2531 }; 2532 static const unsigned int scif1_clk_c_mux[] = { 2533 SCIF1_SCK_C_MARK, 2534 }; 2535 /* - SCIF2 ------------------------------------------------------------------ */ 2536 static const unsigned int scif2_data_pins[] = { 2537 /* RX, TX */ 2538 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 2539 }; 2540 static const unsigned int scif2_data_mux[] = { 2541 SCIF2_RXD_MARK, SCIF2_TXD_MARK, 2542 }; 2543 static const unsigned int scif2_clk_pins[] = { 2544 /* SCK */ 2545 RCAR_GP_PIN(4, 18), 2546 }; 2547 static const unsigned int scif2_clk_mux[] = { 2548 SCIF2_SCK_MARK, 2549 }; 2550 static const unsigned int scif2_data_b_pins[] = { 2551 /* RX, TX */ 2552 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 2553 }; 2554 static const unsigned int scif2_data_b_mux[] = { 2555 SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK, 2556 }; 2557 static const unsigned int scif2_clk_b_pins[] = { 2558 /* SCK */ 2559 RCAR_GP_PIN(5, 17), 2560 }; 2561 static const unsigned int scif2_clk_b_mux[] = { 2562 SCIF2_SCK_B_MARK, 2563 }; 2564 static const unsigned int scif2_data_c_pins[] = { 2565 /* RX, TX */ 2566 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2567 }; 2568 static const unsigned int scif2_data_c_mux[] = { 2569 SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK, 2570 }; 2571 static const unsigned int scif2_clk_c_pins[] = { 2572 /* SCK */ 2573 RCAR_GP_PIN(3, 19), 2574 }; 2575 static const unsigned int scif2_clk_c_mux[] = { 2576 SCIF2_SCK_C_MARK, 2577 }; 2578 /* - SCIF3 ------------------------------------------------------------------ */ 2579 static const unsigned int scif3_data_pins[] = { 2580 /* RX, TX */ 2581 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 2582 }; 2583 static const unsigned int scif3_data_mux[] = { 2584 SCIF3_RXD_MARK, SCIF3_TXD_MARK, 2585 }; 2586 static const unsigned int scif3_clk_pins[] = { 2587 /* SCK */ 2588 RCAR_GP_PIN(4, 19), 2589 }; 2590 static const unsigned int scif3_clk_mux[] = { 2591 SCIF3_SCK_MARK, 2592 }; 2593 static const unsigned int scif3_data_b_pins[] = { 2594 /* RX, TX */ 2595 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), 2596 }; 2597 static const unsigned int scif3_data_b_mux[] = { 2598 SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK, 2599 }; 2600 static const unsigned int scif3_clk_b_pins[] = { 2601 /* SCK */ 2602 RCAR_GP_PIN(3, 22), 2603 }; 2604 static const unsigned int scif3_clk_b_mux[] = { 2605 SCIF3_SCK_B_MARK, 2606 }; 2607 /* - SCIF4 ------------------------------------------------------------------ */ 2608 static const unsigned int scif4_data_pins[] = { 2609 /* RX, TX */ 2610 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2611 }; 2612 static const unsigned int scif4_data_mux[] = { 2613 SCIF4_RXD_MARK, SCIF4_TXD_MARK, 2614 }; 2615 static const unsigned int scif4_data_b_pins[] = { 2616 /* RX, TX */ 2617 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 2618 }; 2619 static const unsigned int scif4_data_b_mux[] = { 2620 SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK, 2621 }; 2622 static const unsigned int scif4_data_c_pins[] = { 2623 /* RX, TX */ 2624 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 2625 }; 2626 static const unsigned int scif4_data_c_mux[] = { 2627 SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK, 2628 }; 2629 static const unsigned int scif4_data_d_pins[] = { 2630 /* RX, TX */ 2631 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), 2632 }; 2633 static const unsigned int scif4_data_d_mux[] = { 2634 SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK, 2635 }; 2636 static const unsigned int scif4_data_e_pins[] = { 2637 /* RX, TX */ 2638 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 2639 }; 2640 static const unsigned int scif4_data_e_mux[] = { 2641 SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK, 2642 }; 2643 /* - SCIF5 ------------------------------------------------------------------ */ 2644 static const unsigned int scif5_data_pins[] = { 2645 /* RX, TX */ 2646 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 2647 }; 2648 static const unsigned int scif5_data_mux[] = { 2649 SCIF5_RXD_MARK, SCIF5_TXD_MARK, 2650 }; 2651 static const unsigned int scif5_data_b_pins[] = { 2652 /* RX, TX */ 2653 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), 2654 }; 2655 static const unsigned int scif5_data_b_mux[] = { 2656 SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK, 2657 }; 2658 static const unsigned int scif5_data_c_pins[] = { 2659 /* RX, TX */ 2660 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11), 2661 }; 2662 static const unsigned int scif5_data_c_mux[] = { 2663 SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK, 2664 }; 2665 static const unsigned int scif5_data_d_pins[] = { 2666 /* RX, TX */ 2667 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2668 }; 2669 static const unsigned int scif5_data_d_mux[] = { 2670 SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK, 2671 }; 2672 /* - SCIFA0 ----------------------------------------------------------------- */ 2673 static const unsigned int scifa0_data_pins[] = { 2674 /* RXD, TXD */ 2675 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 2676 }; 2677 static const unsigned int scifa0_data_mux[] = { 2678 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 2679 }; 2680 static const unsigned int scifa0_data_b_pins[] = { 2681 /* RXD, TXD */ 2682 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2683 }; 2684 static const unsigned int scifa0_data_b_mux[] = { 2685 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 2686 }; 2687 static const unsigned int scifa0_data_c_pins[] = { 2688 /* RXD, TXD */ 2689 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 2690 }; 2691 static const unsigned int scifa0_data_c_mux[] = { 2692 SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK 2693 }; 2694 static const unsigned int scifa0_data_d_pins[] = { 2695 /* RXD, TXD */ 2696 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 2697 }; 2698 static const unsigned int scifa0_data_d_mux[] = { 2699 SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK 2700 }; 2701 /* - SCIFA1 ----------------------------------------------------------------- */ 2702 static const unsigned int scifa1_data_pins[] = { 2703 /* RXD, TXD */ 2704 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2705 }; 2706 static const unsigned int scifa1_data_mux[] = { 2707 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 2708 }; 2709 static const unsigned int scifa1_clk_pins[] = { 2710 /* SCK */ 2711 RCAR_GP_PIN(0, 13), 2712 }; 2713 static const unsigned int scifa1_clk_mux[] = { 2714 SCIFA1_SCK_MARK, 2715 }; 2716 static const unsigned int scifa1_data_b_pins[] = { 2717 /* RXD, TXD */ 2718 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2719 }; 2720 static const unsigned int scifa1_data_b_mux[] = { 2721 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 2722 }; 2723 static const unsigned int scifa1_clk_b_pins[] = { 2724 /* SCK */ 2725 RCAR_GP_PIN(4, 27), 2726 }; 2727 static const unsigned int scifa1_clk_b_mux[] = { 2728 SCIFA1_SCK_B_MARK, 2729 }; 2730 static const unsigned int scifa1_data_c_pins[] = { 2731 /* RXD, TXD */ 2732 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2733 }; 2734 static const unsigned int scifa1_data_c_mux[] = { 2735 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 2736 }; 2737 static const unsigned int scifa1_clk_c_pins[] = { 2738 /* SCK */ 2739 RCAR_GP_PIN(5, 4), 2740 }; 2741 static const unsigned int scifa1_clk_c_mux[] = { 2742 SCIFA1_SCK_C_MARK, 2743 }; 2744 /* - SCIFA2 ----------------------------------------------------------------- */ 2745 static const unsigned int scifa2_data_pins[] = { 2746 /* RXD, TXD */ 2747 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2748 }; 2749 static const unsigned int scifa2_data_mux[] = { 2750 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 2751 }; 2752 static const unsigned int scifa2_clk_pins[] = { 2753 /* SCK */ 2754 RCAR_GP_PIN(1, 15), 2755 }; 2756 static const unsigned int scifa2_clk_mux[] = { 2757 SCIFA2_SCK_MARK, 2758 }; 2759 static const unsigned int scifa2_data_b_pins[] = { 2760 /* RXD, TXD */ 2761 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0), 2762 }; 2763 static const unsigned int scifa2_data_b_mux[] = { 2764 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 2765 }; 2766 static const unsigned int scifa2_clk_b_pins[] = { 2767 /* SCK */ 2768 RCAR_GP_PIN(4, 30), 2769 }; 2770 static const unsigned int scifa2_clk_b_mux[] = { 2771 SCIFA2_SCK_B_MARK, 2772 }; 2773 /* - SCIFA3 ----------------------------------------------------------------- */ 2774 static const unsigned int scifa3_data_pins[] = { 2775 /* RXD, TXD */ 2776 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), 2777 }; 2778 static const unsigned int scifa3_data_mux[] = { 2779 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, 2780 }; 2781 static const unsigned int scifa3_clk_pins[] = { 2782 /* SCK */ 2783 RCAR_GP_PIN(4, 24), 2784 }; 2785 static const unsigned int scifa3_clk_mux[] = { 2786 SCIFA3_SCK_MARK, 2787 }; 2788 static const unsigned int scifa3_data_b_pins[] = { 2789 /* RXD, TXD */ 2790 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), 2791 }; 2792 static const unsigned int scifa3_data_b_mux[] = { 2793 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, 2794 }; 2795 static const unsigned int scifa3_clk_b_pins[] = { 2796 /* SCK */ 2797 RCAR_GP_PIN(0, 0), 2798 }; 2799 static const unsigned int scifa3_clk_b_mux[] = { 2800 SCIFA3_SCK_B_MARK, 2801 }; 2802 /* - SCIFA4 ----------------------------------------------------------------- */ 2803 static const unsigned int scifa4_data_pins[] = { 2804 /* RXD, TXD */ 2805 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12), 2806 }; 2807 static const unsigned int scifa4_data_mux[] = { 2808 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, 2809 }; 2810 static const unsigned int scifa4_data_b_pins[] = { 2811 /* RXD, TXD */ 2812 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23), 2813 }; 2814 static const unsigned int scifa4_data_b_mux[] = { 2815 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, 2816 }; 2817 static const unsigned int scifa4_data_c_pins[] = { 2818 /* RXD, TXD */ 2819 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 2820 }; 2821 static const unsigned int scifa4_data_c_mux[] = { 2822 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, 2823 }; 2824 static const unsigned int scifa4_data_d_pins[] = { 2825 /* RXD, TXD */ 2826 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), 2827 }; 2828 static const unsigned int scifa4_data_d_mux[] = { 2829 SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK, 2830 }; 2831 /* - SCIFA5 ----------------------------------------------------------------- */ 2832 static const unsigned int scifa5_data_pins[] = { 2833 /* RXD, TXD */ 2834 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 2835 }; 2836 static const unsigned int scifa5_data_mux[] = { 2837 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, 2838 }; 2839 static const unsigned int scifa5_data_b_pins[] = { 2840 /* RXD, TXD */ 2841 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29), 2842 }; 2843 static const unsigned int scifa5_data_b_mux[] = { 2844 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, 2845 }; 2846 static const unsigned int scifa5_data_c_pins[] = { 2847 /* RXD, TXD */ 2848 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 2849 }; 2850 static const unsigned int scifa5_data_c_mux[] = { 2851 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, 2852 }; 2853 static const unsigned int scifa5_data_d_pins[] = { 2854 /* RXD, TXD */ 2855 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 2856 }; 2857 static const unsigned int scifa5_data_d_mux[] = { 2858 SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK, 2859 }; 2860 /* - SCIFB0 ----------------------------------------------------------------- */ 2861 static const unsigned int scifb0_data_pins[] = { 2862 /* RXD, TXD */ 2863 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20), 2864 }; 2865 static const unsigned int scifb0_data_mux[] = { 2866 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 2867 }; 2868 static const unsigned int scifb0_clk_pins[] = { 2869 /* SCK */ 2870 RCAR_GP_PIN(0, 19), 2871 }; 2872 static const unsigned int scifb0_clk_mux[] = { 2873 SCIFB0_SCK_MARK, 2874 }; 2875 static const unsigned int scifb0_ctrl_pins[] = { 2876 /* RTS, CTS */ 2877 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), 2878 }; 2879 static const unsigned int scifb0_ctrl_mux[] = { 2880 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 2881 }; 2882 /* - SCIFB1 ----------------------------------------------------------------- */ 2883 static const unsigned int scifb1_data_pins[] = { 2884 /* RXD, TXD */ 2885 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17), 2886 }; 2887 static const unsigned int scifb1_data_mux[] = { 2888 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 2889 }; 2890 static const unsigned int scifb1_clk_pins[] = { 2891 /* SCK */ 2892 RCAR_GP_PIN(0, 16), 2893 }; 2894 static const unsigned int scifb1_clk_mux[] = { 2895 SCIFB1_SCK_MARK, 2896 }; 2897 /* - SCIFB2 ----------------------------------------------------------------- */ 2898 static const unsigned int scifb2_data_pins[] = { 2899 /* RXD, TXD */ 2900 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 2901 }; 2902 static const unsigned int scifb2_data_mux[] = { 2903 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 2904 }; 2905 static const unsigned int scifb2_clk_pins[] = { 2906 /* SCK */ 2907 RCAR_GP_PIN(1, 15), 2908 }; 2909 static const unsigned int scifb2_clk_mux[] = { 2910 SCIFB2_SCK_MARK, 2911 }; 2912 static const unsigned int scifb2_ctrl_pins[] = { 2913 /* RTS, CTS */ 2914 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2915 }; 2916 static const unsigned int scifb2_ctrl_mux[] = { 2917 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 2918 }; 2919 /* - SCIF Clock ------------------------------------------------------------- */ 2920 static const unsigned int scif_clk_pins[] = { 2921 /* SCIF_CLK */ 2922 RCAR_GP_PIN(1, 23), 2923 }; 2924 static const unsigned int scif_clk_mux[] = { 2925 SCIF_CLK_MARK, 2926 }; 2927 static const unsigned int scif_clk_b_pins[] = { 2928 /* SCIF_CLK */ 2929 RCAR_GP_PIN(3, 29), 2930 }; 2931 static const unsigned int scif_clk_b_mux[] = { 2932 SCIF_CLK_B_MARK, 2933 }; 2934 /* - SDHI0 ------------------------------------------------------------------ */ 2935 static const unsigned int sdhi0_data1_pins[] = { 2936 /* D0 */ 2937 RCAR_GP_PIN(6, 2), 2938 }; 2939 static const unsigned int sdhi0_data1_mux[] = { 2940 SD0_DATA0_MARK, 2941 }; 2942 static const unsigned int sdhi0_data4_pins[] = { 2943 /* D[0:3] */ 2944 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 2945 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), 2946 }; 2947 static const unsigned int sdhi0_data4_mux[] = { 2948 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, 2949 }; 2950 static const unsigned int sdhi0_ctrl_pins[] = { 2951 /* CLK, CMD */ 2952 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 2953 }; 2954 static const unsigned int sdhi0_ctrl_mux[] = { 2955 SD0_CLK_MARK, SD0_CMD_MARK, 2956 }; 2957 static const unsigned int sdhi0_cd_pins[] = { 2958 /* CD */ 2959 RCAR_GP_PIN(6, 6), 2960 }; 2961 static const unsigned int sdhi0_cd_mux[] = { 2962 SD0_CD_MARK, 2963 }; 2964 static const unsigned int sdhi0_wp_pins[] = { 2965 /* WP */ 2966 RCAR_GP_PIN(6, 7), 2967 }; 2968 static const unsigned int sdhi0_wp_mux[] = { 2969 SD0_WP_MARK, 2970 }; 2971 /* - SDHI1 ------------------------------------------------------------------ */ 2972 static const unsigned int sdhi1_data1_pins[] = { 2973 /* D0 */ 2974 RCAR_GP_PIN(6, 10), 2975 }; 2976 static const unsigned int sdhi1_data1_mux[] = { 2977 SD1_DATA0_MARK, 2978 }; 2979 static const unsigned int sdhi1_data4_pins[] = { 2980 /* D[0:3] */ 2981 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), 2982 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), 2983 }; 2984 static const unsigned int sdhi1_data4_mux[] = { 2985 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, 2986 }; 2987 static const unsigned int sdhi1_ctrl_pins[] = { 2988 /* CLK, CMD */ 2989 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2990 }; 2991 static const unsigned int sdhi1_ctrl_mux[] = { 2992 SD1_CLK_MARK, SD1_CMD_MARK, 2993 }; 2994 static const unsigned int sdhi1_cd_pins[] = { 2995 /* CD */ 2996 RCAR_GP_PIN(6, 14), 2997 }; 2998 static const unsigned int sdhi1_cd_mux[] = { 2999 SD1_CD_MARK, 3000 }; 3001 static const unsigned int sdhi1_wp_pins[] = { 3002 /* WP */ 3003 RCAR_GP_PIN(6, 15), 3004 }; 3005 static const unsigned int sdhi1_wp_mux[] = { 3006 SD1_WP_MARK, 3007 }; 3008 /* - SDHI2 ------------------------------------------------------------------ */ 3009 static const unsigned int sdhi2_data1_pins[] = { 3010 /* D0 */ 3011 RCAR_GP_PIN(6, 18), 3012 }; 3013 static const unsigned int sdhi2_data1_mux[] = { 3014 SD2_DATA0_MARK, 3015 }; 3016 static const unsigned int sdhi2_data4_pins[] = { 3017 /* D[0:3] */ 3018 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), 3019 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), 3020 }; 3021 static const unsigned int sdhi2_data4_mux[] = { 3022 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, 3023 }; 3024 static const unsigned int sdhi2_ctrl_pins[] = { 3025 /* CLK, CMD */ 3026 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 3027 }; 3028 static const unsigned int sdhi2_ctrl_mux[] = { 3029 SD2_CLK_MARK, SD2_CMD_MARK, 3030 }; 3031 static const unsigned int sdhi2_cd_pins[] = { 3032 /* CD */ 3033 RCAR_GP_PIN(6, 22), 3034 }; 3035 static const unsigned int sdhi2_cd_mux[] = { 3036 SD2_CD_MARK, 3037 }; 3038 static const unsigned int sdhi2_wp_pins[] = { 3039 /* WP */ 3040 RCAR_GP_PIN(6, 23), 3041 }; 3042 static const unsigned int sdhi2_wp_mux[] = { 3043 SD2_WP_MARK, 3044 }; 3045 /* - SSI -------------------------------------------------------------------- */ 3046 static const unsigned int ssi0_data_pins[] = { 3047 /* SDATA0 */ 3048 RCAR_GP_PIN(5, 3), 3049 }; 3050 static const unsigned int ssi0_data_mux[] = { 3051 SSI_SDATA0_MARK, 3052 }; 3053 static const unsigned int ssi0129_ctrl_pins[] = { 3054 /* SCK0129, WS0129 */ 3055 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3056 }; 3057 static const unsigned int ssi0129_ctrl_mux[] = { 3058 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3059 }; 3060 static const unsigned int ssi1_data_pins[] = { 3061 /* SDATA1 */ 3062 RCAR_GP_PIN(5, 13), 3063 }; 3064 static const unsigned int ssi1_data_mux[] = { 3065 SSI_SDATA1_MARK, 3066 }; 3067 static const unsigned int ssi1_ctrl_pins[] = { 3068 /* SCK1, WS1 */ 3069 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), 3070 }; 3071 static const unsigned int ssi1_ctrl_mux[] = { 3072 SSI_SCK1_MARK, SSI_WS1_MARK, 3073 }; 3074 static const unsigned int ssi1_data_b_pins[] = { 3075 /* SDATA1 */ 3076 RCAR_GP_PIN(4, 13), 3077 }; 3078 static const unsigned int ssi1_data_b_mux[] = { 3079 SSI_SDATA1_B_MARK, 3080 }; 3081 static const unsigned int ssi1_ctrl_b_pins[] = { 3082 /* SCK1, WS1 */ 3083 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3084 }; 3085 static const unsigned int ssi1_ctrl_b_mux[] = { 3086 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3087 }; 3088 static const unsigned int ssi2_data_pins[] = { 3089 /* SDATA2 */ 3090 RCAR_GP_PIN(5, 16), 3091 }; 3092 static const unsigned int ssi2_data_mux[] = { 3093 SSI_SDATA2_MARK, 3094 }; 3095 static const unsigned int ssi2_ctrl_pins[] = { 3096 /* SCK2, WS2 */ 3097 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 3098 }; 3099 static const unsigned int ssi2_ctrl_mux[] = { 3100 SSI_SCK2_MARK, SSI_WS2_MARK, 3101 }; 3102 static const unsigned int ssi2_data_b_pins[] = { 3103 /* SDATA2 */ 3104 RCAR_GP_PIN(4, 16), 3105 }; 3106 static const unsigned int ssi2_data_b_mux[] = { 3107 SSI_SDATA2_B_MARK, 3108 }; 3109 static const unsigned int ssi2_ctrl_b_pins[] = { 3110 /* SCK2, WS2 */ 3111 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 3112 }; 3113 static const unsigned int ssi2_ctrl_b_mux[] = { 3114 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3115 }; 3116 static const unsigned int ssi3_data_pins[] = { 3117 /* SDATA3 */ 3118 RCAR_GP_PIN(5, 6), 3119 }; 3120 static const unsigned int ssi3_data_mux[] = { 3121 SSI_SDATA3_MARK 3122 }; 3123 static const unsigned int ssi34_ctrl_pins[] = { 3124 /* SCK34, WS34 */ 3125 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), 3126 }; 3127 static const unsigned int ssi34_ctrl_mux[] = { 3128 SSI_SCK34_MARK, SSI_WS34_MARK, 3129 }; 3130 static const unsigned int ssi4_data_pins[] = { 3131 /* SDATA4 */ 3132 RCAR_GP_PIN(5, 9), 3133 }; 3134 static const unsigned int ssi4_data_mux[] = { 3135 SSI_SDATA4_MARK, 3136 }; 3137 static const unsigned int ssi4_ctrl_pins[] = { 3138 /* SCK4, WS4 */ 3139 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 3140 }; 3141 static const unsigned int ssi4_ctrl_mux[] = { 3142 SSI_SCK4_MARK, SSI_WS4_MARK, 3143 }; 3144 static const unsigned int ssi4_data_b_pins[] = { 3145 /* SDATA4 */ 3146 RCAR_GP_PIN(4, 22), 3147 }; 3148 static const unsigned int ssi4_data_b_mux[] = { 3149 SSI_SDATA4_B_MARK, 3150 }; 3151 static const unsigned int ssi4_ctrl_b_pins[] = { 3152 /* SCK4, WS4 */ 3153 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 3154 }; 3155 static const unsigned int ssi4_ctrl_b_mux[] = { 3156 SSI_SCK4_B_MARK, SSI_WS4_B_MARK, 3157 }; 3158 static const unsigned int ssi5_data_pins[] = { 3159 /* SDATA5 */ 3160 RCAR_GP_PIN(4, 26), 3161 }; 3162 static const unsigned int ssi5_data_mux[] = { 3163 SSI_SDATA5_MARK, 3164 }; 3165 static const unsigned int ssi5_ctrl_pins[] = { 3166 /* SCK5, WS5 */ 3167 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25), 3168 }; 3169 static const unsigned int ssi5_ctrl_mux[] = { 3170 SSI_SCK5_MARK, SSI_WS5_MARK, 3171 }; 3172 static const unsigned int ssi5_data_b_pins[] = { 3173 /* SDATA5 */ 3174 RCAR_GP_PIN(3, 21), 3175 }; 3176 static const unsigned int ssi5_data_b_mux[] = { 3177 SSI_SDATA5_B_MARK, 3178 }; 3179 static const unsigned int ssi5_ctrl_b_pins[] = { 3180 /* SCK5, WS5 */ 3181 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), 3182 }; 3183 static const unsigned int ssi5_ctrl_b_mux[] = { 3184 SSI_SCK5_B_MARK, SSI_WS5_B_MARK, 3185 }; 3186 static const unsigned int ssi6_data_pins[] = { 3187 /* SDATA6 */ 3188 RCAR_GP_PIN(4, 29), 3189 }; 3190 static const unsigned int ssi6_data_mux[] = { 3191 SSI_SDATA6_MARK, 3192 }; 3193 static const unsigned int ssi6_ctrl_pins[] = { 3194 /* SCK6, WS6 */ 3195 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), 3196 }; 3197 static const unsigned int ssi6_ctrl_mux[] = { 3198 SSI_SCK6_MARK, SSI_WS6_MARK, 3199 }; 3200 static const unsigned int ssi6_data_b_pins[] = { 3201 /* SDATA6 */ 3202 RCAR_GP_PIN(3, 24), 3203 }; 3204 static const unsigned int ssi6_data_b_mux[] = { 3205 SSI_SDATA6_B_MARK, 3206 }; 3207 static const unsigned int ssi6_ctrl_b_pins[] = { 3208 /* SCK6, WS6 */ 3209 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 3210 }; 3211 static const unsigned int ssi6_ctrl_b_mux[] = { 3212 SSI_SCK6_B_MARK, SSI_WS6_B_MARK, 3213 }; 3214 static const unsigned int ssi7_data_pins[] = { 3215 /* SDATA7 */ 3216 RCAR_GP_PIN(5, 0), 3217 }; 3218 static const unsigned int ssi7_data_mux[] = { 3219 SSI_SDATA7_MARK, 3220 }; 3221 static const unsigned int ssi78_ctrl_pins[] = { 3222 /* SCK78, WS78 */ 3223 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31), 3224 }; 3225 static const unsigned int ssi78_ctrl_mux[] = { 3226 SSI_SCK78_MARK, SSI_WS78_MARK, 3227 }; 3228 static const unsigned int ssi7_data_b_pins[] = { 3229 /* SDATA7 */ 3230 RCAR_GP_PIN(3, 27), 3231 }; 3232 static const unsigned int ssi7_data_b_mux[] = { 3233 SSI_SDATA7_B_MARK, 3234 }; 3235 static const unsigned int ssi78_ctrl_b_pins[] = { 3236 /* SCK78, WS78 */ 3237 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 3238 }; 3239 static const unsigned int ssi78_ctrl_b_mux[] = { 3240 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 3241 }; 3242 static const unsigned int ssi8_data_pins[] = { 3243 /* SDATA8 */ 3244 RCAR_GP_PIN(5, 10), 3245 }; 3246 static const unsigned int ssi8_data_mux[] = { 3247 SSI_SDATA8_MARK, 3248 }; 3249 static const unsigned int ssi8_data_b_pins[] = { 3250 /* SDATA8 */ 3251 RCAR_GP_PIN(3, 28), 3252 }; 3253 static const unsigned int ssi8_data_b_mux[] = { 3254 SSI_SDATA8_B_MARK, 3255 }; 3256 static const unsigned int ssi9_data_pins[] = { 3257 /* SDATA9 */ 3258 RCAR_GP_PIN(5, 19), 3259 }; 3260 static const unsigned int ssi9_data_mux[] = { 3261 SSI_SDATA9_MARK, 3262 }; 3263 static const unsigned int ssi9_ctrl_pins[] = { 3264 /* SCK9, WS9 */ 3265 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 3266 }; 3267 static const unsigned int ssi9_ctrl_mux[] = { 3268 SSI_SCK9_MARK, SSI_WS9_MARK, 3269 }; 3270 static const unsigned int ssi9_data_b_pins[] = { 3271 /* SDATA9 */ 3272 RCAR_GP_PIN(4, 19), 3273 }; 3274 static const unsigned int ssi9_data_b_mux[] = { 3275 SSI_SDATA9_B_MARK, 3276 }; 3277 static const unsigned int ssi9_ctrl_b_pins[] = { 3278 /* SCK9, WS9 */ 3279 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 3280 }; 3281 static const unsigned int ssi9_ctrl_b_mux[] = { 3282 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3283 }; 3284 /* - USB0 ------------------------------------------------------------------- */ 3285 static const unsigned int usb0_pins[] = { 3286 RCAR_GP_PIN(5, 24), /* PWEN */ 3287 RCAR_GP_PIN(5, 25), /* OVC */ 3288 }; 3289 static const unsigned int usb0_mux[] = { 3290 USB0_PWEN_MARK, 3291 USB0_OVC_MARK, 3292 }; 3293 /* - USB1 ------------------------------------------------------------------- */ 3294 static const unsigned int usb1_pins[] = { 3295 RCAR_GP_PIN(5, 26), /* PWEN */ 3296 RCAR_GP_PIN(5, 27), /* OVC */ 3297 }; 3298 static const unsigned int usb1_mux[] = { 3299 USB1_PWEN_MARK, 3300 USB1_OVC_MARK, 3301 }; 3302 /* - VIN0 ------------------------------------------------------------------- */ 3303 static const union vin_data vin0_data_pins = { 3304 .data24 = { 3305 /* B */ 3306 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), 3307 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), 3308 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 3309 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), 3310 /* G */ 3311 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 3312 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 3313 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), 3314 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), 3315 /* R */ 3316 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), 3317 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), 3318 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 3319 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 3320 }, 3321 }; 3322 static const union vin_data vin0_data_mux = { 3323 .data24 = { 3324 /* B */ 3325 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 3326 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3327 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3328 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3329 /* G */ 3330 VI0_G0_MARK, VI0_G1_MARK, 3331 VI0_G2_MARK, VI0_G3_MARK, 3332 VI0_G4_MARK, VI0_G5_MARK, 3333 VI0_G6_MARK, VI0_G7_MARK, 3334 /* R */ 3335 VI0_R0_MARK, VI0_R1_MARK, 3336 VI0_R2_MARK, VI0_R3_MARK, 3337 VI0_R4_MARK, VI0_R5_MARK, 3338 VI0_R6_MARK, VI0_R7_MARK, 3339 }, 3340 }; 3341 static const unsigned int vin0_data18_pins[] = { 3342 /* B */ 3343 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), 3344 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 3345 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), 3346 /* G */ 3347 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 3348 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), 3349 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), 3350 /* R */ 3351 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), 3352 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 3353 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 3354 }; 3355 static const unsigned int vin0_data18_mux[] = { 3356 /* B */ 3357 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3358 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3359 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3360 /* G */ 3361 VI0_G2_MARK, VI0_G3_MARK, 3362 VI0_G4_MARK, VI0_G5_MARK, 3363 VI0_G6_MARK, VI0_G7_MARK, 3364 /* R */ 3365 VI0_R2_MARK, VI0_R3_MARK, 3366 VI0_R4_MARK, VI0_R5_MARK, 3367 VI0_R6_MARK, VI0_R7_MARK, 3368 }; 3369 static const unsigned int vin0_sync_pins[] = { 3370 RCAR_GP_PIN(3, 11), /* HSYNC */ 3371 RCAR_GP_PIN(3, 12), /* VSYNC */ 3372 }; 3373 static const unsigned int vin0_sync_mux[] = { 3374 VI0_HSYNC_N_MARK, 3375 VI0_VSYNC_N_MARK, 3376 }; 3377 static const unsigned int vin0_field_pins[] = { 3378 RCAR_GP_PIN(3, 10), 3379 }; 3380 static const unsigned int vin0_field_mux[] = { 3381 VI0_FIELD_MARK, 3382 }; 3383 static const unsigned int vin0_clkenb_pins[] = { 3384 RCAR_GP_PIN(3, 9), 3385 }; 3386 static const unsigned int vin0_clkenb_mux[] = { 3387 VI0_CLKENB_MARK, 3388 }; 3389 static const unsigned int vin0_clk_pins[] = { 3390 RCAR_GP_PIN(3, 0), 3391 }; 3392 static const unsigned int vin0_clk_mux[] = { 3393 VI0_CLK_MARK, 3394 }; 3395 /* - VIN1 ------------------------------------------------------------------- */ 3396 static const union vin_data vin1_data_pins = { 3397 .data12 = { 3398 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), 3399 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 3400 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), 3401 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 3402 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), 3403 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 3404 }, 3405 }; 3406 static const union vin_data vin1_data_mux = { 3407 .data12 = { 3408 VI1_DATA0_MARK, VI1_DATA1_MARK, 3409 VI1_DATA2_MARK, VI1_DATA3_MARK, 3410 VI1_DATA4_MARK, VI1_DATA5_MARK, 3411 VI1_DATA6_MARK, VI1_DATA7_MARK, 3412 VI1_DATA8_MARK, VI1_DATA9_MARK, 3413 VI1_DATA10_MARK, VI1_DATA11_MARK, 3414 }, 3415 }; 3416 static const unsigned int vin1_sync_pins[] = { 3417 RCAR_GP_PIN(5, 22), /* HSYNC */ 3418 RCAR_GP_PIN(5, 23), /* VSYNC */ 3419 }; 3420 static const unsigned int vin1_sync_mux[] = { 3421 VI1_HSYNC_N_MARK, 3422 VI1_VSYNC_N_MARK, 3423 }; 3424 static const unsigned int vin1_field_pins[] = { 3425 RCAR_GP_PIN(5, 21), 3426 }; 3427 static const unsigned int vin1_field_mux[] = { 3428 VI1_FIELD_MARK, 3429 }; 3430 static const unsigned int vin1_clkenb_pins[] = { 3431 RCAR_GP_PIN(5, 20), 3432 }; 3433 static const unsigned int vin1_clkenb_mux[] = { 3434 VI1_CLKENB_MARK, 3435 }; 3436 static const unsigned int vin1_clk_pins[] = { 3437 RCAR_GP_PIN(5, 11), 3438 }; 3439 static const unsigned int vin1_clk_mux[] = { 3440 VI1_CLK_MARK, 3441 }; 3442 3443 static const struct sh_pfc_pin_group pinmux_groups[] = { 3444 SH_PFC_PIN_GROUP(audio_clka), 3445 SH_PFC_PIN_GROUP(audio_clka_b), 3446 SH_PFC_PIN_GROUP(audio_clka_c), 3447 SH_PFC_PIN_GROUP(audio_clka_d), 3448 SH_PFC_PIN_GROUP(audio_clkb), 3449 SH_PFC_PIN_GROUP(audio_clkb_b), 3450 SH_PFC_PIN_GROUP(audio_clkb_c), 3451 SH_PFC_PIN_GROUP(audio_clkc), 3452 SH_PFC_PIN_GROUP(audio_clkc_b), 3453 SH_PFC_PIN_GROUP(audio_clkc_c), 3454 SH_PFC_PIN_GROUP(audio_clkout), 3455 SH_PFC_PIN_GROUP(audio_clkout_b), 3456 SH_PFC_PIN_GROUP(audio_clkout_c), 3457 SH_PFC_PIN_GROUP(avb_link), 3458 SH_PFC_PIN_GROUP(avb_magic), 3459 SH_PFC_PIN_GROUP(avb_phy_int), 3460 SH_PFC_PIN_GROUP(avb_mdio), 3461 SH_PFC_PIN_GROUP(avb_mii), 3462 SH_PFC_PIN_GROUP(avb_gmii), 3463 SH_PFC_PIN_GROUP(du0_rgb666), 3464 SH_PFC_PIN_GROUP(du0_rgb888), 3465 SH_PFC_PIN_GROUP(du0_clk0_out), 3466 SH_PFC_PIN_GROUP(du0_clk1_out), 3467 SH_PFC_PIN_GROUP(du0_clk_in), 3468 SH_PFC_PIN_GROUP(du0_sync), 3469 SH_PFC_PIN_GROUP(du0_oddf), 3470 SH_PFC_PIN_GROUP(du0_cde), 3471 SH_PFC_PIN_GROUP(du0_disp), 3472 SH_PFC_PIN_GROUP(du1_rgb666), 3473 SH_PFC_PIN_GROUP(du1_rgb888), 3474 SH_PFC_PIN_GROUP(du1_clk0_out), 3475 SH_PFC_PIN_GROUP(du1_clk1_out), 3476 SH_PFC_PIN_GROUP(du1_clk_in), 3477 SH_PFC_PIN_GROUP(du1_sync), 3478 SH_PFC_PIN_GROUP(du1_oddf), 3479 SH_PFC_PIN_GROUP(du1_cde), 3480 SH_PFC_PIN_GROUP(du1_disp), 3481 SH_PFC_PIN_GROUP(eth_link), 3482 SH_PFC_PIN_GROUP(eth_magic), 3483 SH_PFC_PIN_GROUP(eth_mdio), 3484 SH_PFC_PIN_GROUP(eth_rmii), 3485 SH_PFC_PIN_GROUP(eth_link_b), 3486 SH_PFC_PIN_GROUP(eth_magic_b), 3487 SH_PFC_PIN_GROUP(eth_mdio_b), 3488 SH_PFC_PIN_GROUP(eth_rmii_b), 3489 SH_PFC_PIN_GROUP(hscif0_data), 3490 SH_PFC_PIN_GROUP(hscif0_clk), 3491 SH_PFC_PIN_GROUP(hscif0_ctrl), 3492 SH_PFC_PIN_GROUP(hscif0_data_b), 3493 SH_PFC_PIN_GROUP(hscif0_clk_b), 3494 SH_PFC_PIN_GROUP(hscif1_data), 3495 SH_PFC_PIN_GROUP(hscif1_clk), 3496 SH_PFC_PIN_GROUP(hscif1_ctrl), 3497 SH_PFC_PIN_GROUP(hscif1_data_b), 3498 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3499 SH_PFC_PIN_GROUP(hscif2_data), 3500 SH_PFC_PIN_GROUP(hscif2_clk), 3501 SH_PFC_PIN_GROUP(hscif2_ctrl), 3502 SH_PFC_PIN_GROUP(i2c0), 3503 SH_PFC_PIN_GROUP(i2c0_b), 3504 SH_PFC_PIN_GROUP(i2c0_c), 3505 SH_PFC_PIN_GROUP(i2c0_d), 3506 SH_PFC_PIN_GROUP(i2c0_e), 3507 SH_PFC_PIN_GROUP(i2c1), 3508 SH_PFC_PIN_GROUP(i2c1_b), 3509 SH_PFC_PIN_GROUP(i2c1_c), 3510 SH_PFC_PIN_GROUP(i2c1_d), 3511 SH_PFC_PIN_GROUP(i2c1_e), 3512 SH_PFC_PIN_GROUP(i2c2), 3513 SH_PFC_PIN_GROUP(i2c2_b), 3514 SH_PFC_PIN_GROUP(i2c2_c), 3515 SH_PFC_PIN_GROUP(i2c2_d), 3516 SH_PFC_PIN_GROUP(i2c2_e), 3517 SH_PFC_PIN_GROUP(i2c3), 3518 SH_PFC_PIN_GROUP(i2c3_b), 3519 SH_PFC_PIN_GROUP(i2c3_c), 3520 SH_PFC_PIN_GROUP(i2c3_d), 3521 SH_PFC_PIN_GROUP(i2c3_e), 3522 SH_PFC_PIN_GROUP(i2c4), 3523 SH_PFC_PIN_GROUP(i2c4_b), 3524 SH_PFC_PIN_GROUP(i2c4_c), 3525 SH_PFC_PIN_GROUP(i2c4_d), 3526 SH_PFC_PIN_GROUP(i2c4_e), 3527 SH_PFC_PIN_GROUP(intc_irq0), 3528 SH_PFC_PIN_GROUP(intc_irq1), 3529 SH_PFC_PIN_GROUP(intc_irq2), 3530 SH_PFC_PIN_GROUP(intc_irq3), 3531 SH_PFC_PIN_GROUP(intc_irq4), 3532 SH_PFC_PIN_GROUP(intc_irq5), 3533 SH_PFC_PIN_GROUP(intc_irq6), 3534 SH_PFC_PIN_GROUP(intc_irq7), 3535 SH_PFC_PIN_GROUP(intc_irq8), 3536 SH_PFC_PIN_GROUP(intc_irq9), 3537 SH_PFC_PIN_GROUP(mmc_data1), 3538 SH_PFC_PIN_GROUP(mmc_data4), 3539 SH_PFC_PIN_GROUP(mmc_data8), 3540 SH_PFC_PIN_GROUP(mmc_ctrl), 3541 SH_PFC_PIN_GROUP(msiof0_clk), 3542 SH_PFC_PIN_GROUP(msiof0_sync), 3543 SH_PFC_PIN_GROUP(msiof0_ss1), 3544 SH_PFC_PIN_GROUP(msiof0_ss2), 3545 SH_PFC_PIN_GROUP(msiof0_rx), 3546 SH_PFC_PIN_GROUP(msiof0_tx), 3547 SH_PFC_PIN_GROUP(msiof1_clk), 3548 SH_PFC_PIN_GROUP(msiof1_sync), 3549 SH_PFC_PIN_GROUP(msiof1_ss1), 3550 SH_PFC_PIN_GROUP(msiof1_ss2), 3551 SH_PFC_PIN_GROUP(msiof1_rx), 3552 SH_PFC_PIN_GROUP(msiof1_tx), 3553 SH_PFC_PIN_GROUP(msiof1_clk_b), 3554 SH_PFC_PIN_GROUP(msiof1_sync_b), 3555 SH_PFC_PIN_GROUP(msiof1_ss1_b), 3556 SH_PFC_PIN_GROUP(msiof1_ss2_b), 3557 SH_PFC_PIN_GROUP(msiof1_rx_b), 3558 SH_PFC_PIN_GROUP(msiof1_tx_b), 3559 SH_PFC_PIN_GROUP(msiof2_clk), 3560 SH_PFC_PIN_GROUP(msiof2_sync), 3561 SH_PFC_PIN_GROUP(msiof2_ss1), 3562 SH_PFC_PIN_GROUP(msiof2_ss2), 3563 SH_PFC_PIN_GROUP(msiof2_rx), 3564 SH_PFC_PIN_GROUP(msiof2_tx), 3565 SH_PFC_PIN_GROUP(msiof2_clk_b), 3566 SH_PFC_PIN_GROUP(msiof2_sync_b), 3567 SH_PFC_PIN_GROUP(msiof2_ss1_b), 3568 SH_PFC_PIN_GROUP(msiof2_ss2_b), 3569 SH_PFC_PIN_GROUP(msiof2_rx_b), 3570 SH_PFC_PIN_GROUP(msiof2_tx_b), 3571 SH_PFC_PIN_GROUP(qspi_ctrl), 3572 SH_PFC_PIN_GROUP(qspi_data2), 3573 SH_PFC_PIN_GROUP(qspi_data4), 3574 SH_PFC_PIN_GROUP(scif0_data), 3575 SH_PFC_PIN_GROUP(scif0_data_b), 3576 SH_PFC_PIN_GROUP(scif0_data_c), 3577 SH_PFC_PIN_GROUP(scif0_data_d), 3578 SH_PFC_PIN_GROUP(scif1_data), 3579 SH_PFC_PIN_GROUP(scif1_clk), 3580 SH_PFC_PIN_GROUP(scif1_data_b), 3581 SH_PFC_PIN_GROUP(scif1_clk_b), 3582 SH_PFC_PIN_GROUP(scif1_data_c), 3583 SH_PFC_PIN_GROUP(scif1_clk_c), 3584 SH_PFC_PIN_GROUP(scif2_data), 3585 SH_PFC_PIN_GROUP(scif2_clk), 3586 SH_PFC_PIN_GROUP(scif2_data_b), 3587 SH_PFC_PIN_GROUP(scif2_clk_b), 3588 SH_PFC_PIN_GROUP(scif2_data_c), 3589 SH_PFC_PIN_GROUP(scif2_clk_c), 3590 SH_PFC_PIN_GROUP(scif3_data), 3591 SH_PFC_PIN_GROUP(scif3_clk), 3592 SH_PFC_PIN_GROUP(scif3_data_b), 3593 SH_PFC_PIN_GROUP(scif3_clk_b), 3594 SH_PFC_PIN_GROUP(scif4_data), 3595 SH_PFC_PIN_GROUP(scif4_data_b), 3596 SH_PFC_PIN_GROUP(scif4_data_c), 3597 SH_PFC_PIN_GROUP(scif4_data_d), 3598 SH_PFC_PIN_GROUP(scif4_data_e), 3599 SH_PFC_PIN_GROUP(scif5_data), 3600 SH_PFC_PIN_GROUP(scif5_data_b), 3601 SH_PFC_PIN_GROUP(scif5_data_c), 3602 SH_PFC_PIN_GROUP(scif5_data_d), 3603 SH_PFC_PIN_GROUP(scifa0_data), 3604 SH_PFC_PIN_GROUP(scifa0_data_b), 3605 SH_PFC_PIN_GROUP(scifa0_data_c), 3606 SH_PFC_PIN_GROUP(scifa0_data_d), 3607 SH_PFC_PIN_GROUP(scifa1_data), 3608 SH_PFC_PIN_GROUP(scifa1_clk), 3609 SH_PFC_PIN_GROUP(scifa1_data_b), 3610 SH_PFC_PIN_GROUP(scifa1_clk_b), 3611 SH_PFC_PIN_GROUP(scifa1_data_c), 3612 SH_PFC_PIN_GROUP(scifa1_clk_c), 3613 SH_PFC_PIN_GROUP(scifa2_data), 3614 SH_PFC_PIN_GROUP(scifa2_clk), 3615 SH_PFC_PIN_GROUP(scifa2_data_b), 3616 SH_PFC_PIN_GROUP(scifa2_clk_b), 3617 SH_PFC_PIN_GROUP(scifa3_data), 3618 SH_PFC_PIN_GROUP(scifa3_clk), 3619 SH_PFC_PIN_GROUP(scifa3_data_b), 3620 SH_PFC_PIN_GROUP(scifa3_clk_b), 3621 SH_PFC_PIN_GROUP(scifa4_data), 3622 SH_PFC_PIN_GROUP(scifa4_data_b), 3623 SH_PFC_PIN_GROUP(scifa4_data_c), 3624 SH_PFC_PIN_GROUP(scifa4_data_d), 3625 SH_PFC_PIN_GROUP(scifa5_data), 3626 SH_PFC_PIN_GROUP(scifa5_data_b), 3627 SH_PFC_PIN_GROUP(scifa5_data_c), 3628 SH_PFC_PIN_GROUP(scifa5_data_d), 3629 SH_PFC_PIN_GROUP(scifb0_data), 3630 SH_PFC_PIN_GROUP(scifb0_clk), 3631 SH_PFC_PIN_GROUP(scifb0_ctrl), 3632 SH_PFC_PIN_GROUP(scifb1_data), 3633 SH_PFC_PIN_GROUP(scifb1_clk), 3634 SH_PFC_PIN_GROUP(scifb2_data), 3635 SH_PFC_PIN_GROUP(scifb2_clk), 3636 SH_PFC_PIN_GROUP(scifb2_ctrl), 3637 SH_PFC_PIN_GROUP(scif_clk), 3638 SH_PFC_PIN_GROUP(scif_clk_b), 3639 SH_PFC_PIN_GROUP(sdhi0_data1), 3640 SH_PFC_PIN_GROUP(sdhi0_data4), 3641 SH_PFC_PIN_GROUP(sdhi0_ctrl), 3642 SH_PFC_PIN_GROUP(sdhi0_cd), 3643 SH_PFC_PIN_GROUP(sdhi0_wp), 3644 SH_PFC_PIN_GROUP(sdhi1_data1), 3645 SH_PFC_PIN_GROUP(sdhi1_data4), 3646 SH_PFC_PIN_GROUP(sdhi1_ctrl), 3647 SH_PFC_PIN_GROUP(sdhi1_cd), 3648 SH_PFC_PIN_GROUP(sdhi1_wp), 3649 SH_PFC_PIN_GROUP(sdhi2_data1), 3650 SH_PFC_PIN_GROUP(sdhi2_data4), 3651 SH_PFC_PIN_GROUP(sdhi2_ctrl), 3652 SH_PFC_PIN_GROUP(sdhi2_cd), 3653 SH_PFC_PIN_GROUP(sdhi2_wp), 3654 SH_PFC_PIN_GROUP(ssi0_data), 3655 SH_PFC_PIN_GROUP(ssi0129_ctrl), 3656 SH_PFC_PIN_GROUP(ssi1_data), 3657 SH_PFC_PIN_GROUP(ssi1_ctrl), 3658 SH_PFC_PIN_GROUP(ssi1_data_b), 3659 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 3660 SH_PFC_PIN_GROUP(ssi2_data), 3661 SH_PFC_PIN_GROUP(ssi2_ctrl), 3662 SH_PFC_PIN_GROUP(ssi2_data_b), 3663 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 3664 SH_PFC_PIN_GROUP(ssi3_data), 3665 SH_PFC_PIN_GROUP(ssi34_ctrl), 3666 SH_PFC_PIN_GROUP(ssi4_data), 3667 SH_PFC_PIN_GROUP(ssi4_ctrl), 3668 SH_PFC_PIN_GROUP(ssi4_data_b), 3669 SH_PFC_PIN_GROUP(ssi4_ctrl_b), 3670 SH_PFC_PIN_GROUP(ssi5_data), 3671 SH_PFC_PIN_GROUP(ssi5_ctrl), 3672 SH_PFC_PIN_GROUP(ssi5_data_b), 3673 SH_PFC_PIN_GROUP(ssi5_ctrl_b), 3674 SH_PFC_PIN_GROUP(ssi6_data), 3675 SH_PFC_PIN_GROUP(ssi6_ctrl), 3676 SH_PFC_PIN_GROUP(ssi6_data_b), 3677 SH_PFC_PIN_GROUP(ssi6_ctrl_b), 3678 SH_PFC_PIN_GROUP(ssi7_data), 3679 SH_PFC_PIN_GROUP(ssi78_ctrl), 3680 SH_PFC_PIN_GROUP(ssi7_data_b), 3681 SH_PFC_PIN_GROUP(ssi78_ctrl_b), 3682 SH_PFC_PIN_GROUP(ssi8_data), 3683 SH_PFC_PIN_GROUP(ssi8_data_b), 3684 SH_PFC_PIN_GROUP(ssi9_data), 3685 SH_PFC_PIN_GROUP(ssi9_ctrl), 3686 SH_PFC_PIN_GROUP(ssi9_data_b), 3687 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 3688 SH_PFC_PIN_GROUP(usb0), 3689 SH_PFC_PIN_GROUP(usb1), 3690 VIN_DATA_PIN_GROUP(vin0_data, 24), 3691 VIN_DATA_PIN_GROUP(vin0_data, 20), 3692 SH_PFC_PIN_GROUP(vin0_data18), 3693 VIN_DATA_PIN_GROUP(vin0_data, 16), 3694 VIN_DATA_PIN_GROUP(vin0_data, 12), 3695 VIN_DATA_PIN_GROUP(vin0_data, 10), 3696 VIN_DATA_PIN_GROUP(vin0_data, 8), 3697 SH_PFC_PIN_GROUP(vin0_sync), 3698 SH_PFC_PIN_GROUP(vin0_field), 3699 SH_PFC_PIN_GROUP(vin0_clkenb), 3700 SH_PFC_PIN_GROUP(vin0_clk), 3701 VIN_DATA_PIN_GROUP(vin1_data, 12), 3702 VIN_DATA_PIN_GROUP(vin1_data, 10), 3703 VIN_DATA_PIN_GROUP(vin1_data, 8), 3704 SH_PFC_PIN_GROUP(vin1_sync), 3705 SH_PFC_PIN_GROUP(vin1_field), 3706 SH_PFC_PIN_GROUP(vin1_clkenb), 3707 SH_PFC_PIN_GROUP(vin1_clk), 3708 }; 3709 3710 static const char * const audio_clk_groups[] = { 3711 "audio_clka", 3712 "audio_clka_b", 3713 "audio_clka_c", 3714 "audio_clka_d", 3715 "audio_clkb", 3716 "audio_clkb_b", 3717 "audio_clkb_c", 3718 "audio_clkc", 3719 "audio_clkc_b", 3720 "audio_clkc_c", 3721 "audio_clkout", 3722 "audio_clkout_b", 3723 "audio_clkout_c", 3724 }; 3725 3726 static const char * const avb_groups[] = { 3727 "avb_link", 3728 "avb_magic", 3729 "avb_phy_int", 3730 "avb_mdio", 3731 "avb_mii", 3732 "avb_gmii", 3733 }; 3734 3735 static const char * const du0_groups[] = { 3736 "du0_rgb666", 3737 "du0_rgb888", 3738 "du0_clk0_out", 3739 "du0_clk1_out", 3740 "du0_clk_in", 3741 "du0_sync", 3742 "du0_oddf", 3743 "du0_cde", 3744 "du0_disp", 3745 }; 3746 3747 static const char * const du1_groups[] = { 3748 "du1_rgb666", 3749 "du1_rgb888", 3750 "du1_clk0_out", 3751 "du1_clk1_out", 3752 "du1_clk_in", 3753 "du1_sync", 3754 "du1_oddf", 3755 "du1_cde", 3756 "du1_disp", 3757 }; 3758 3759 static const char * const eth_groups[] = { 3760 "eth_link", 3761 "eth_magic", 3762 "eth_mdio", 3763 "eth_rmii", 3764 "eth_link_b", 3765 "eth_magic_b", 3766 "eth_mdio_b", 3767 "eth_rmii_b", 3768 }; 3769 3770 static const char * const hscif0_groups[] = { 3771 "hscif0_data", 3772 "hscif0_clk", 3773 "hscif0_ctrl", 3774 "hscif0_data_b", 3775 "hscif0_clk_b", 3776 }; 3777 3778 static const char * const hscif1_groups[] = { 3779 "hscif1_data", 3780 "hscif1_clk", 3781 "hscif1_ctrl", 3782 "hscif1_data_b", 3783 "hscif1_ctrl_b", 3784 }; 3785 3786 static const char * const hscif2_groups[] = { 3787 "hscif2_data", 3788 "hscif2_clk", 3789 "hscif2_ctrl", 3790 }; 3791 3792 static const char * const i2c0_groups[] = { 3793 "i2c0", 3794 "i2c0_b", 3795 "i2c0_c", 3796 "i2c0_d", 3797 "i2c0_e", 3798 }; 3799 3800 static const char * const i2c1_groups[] = { 3801 "i2c1", 3802 "i2c1_b", 3803 "i2c1_c", 3804 "i2c1_d", 3805 "i2c1_e", 3806 }; 3807 3808 static const char * const i2c2_groups[] = { 3809 "i2c2", 3810 "i2c2_b", 3811 "i2c2_c", 3812 "i2c2_d", 3813 "i2c2_e", 3814 }; 3815 3816 static const char * const i2c3_groups[] = { 3817 "i2c3", 3818 "i2c3_b", 3819 "i2c3_c", 3820 "i2c3_d", 3821 "i2c3_e", 3822 }; 3823 3824 static const char * const i2c4_groups[] = { 3825 "i2c4", 3826 "i2c4_b", 3827 "i2c4_c", 3828 "i2c4_d", 3829 "i2c4_e", 3830 }; 3831 3832 static const char * const intc_groups[] = { 3833 "intc_irq0", 3834 "intc_irq1", 3835 "intc_irq2", 3836 "intc_irq3", 3837 "intc_irq4", 3838 "intc_irq5", 3839 "intc_irq6", 3840 "intc_irq7", 3841 "intc_irq8", 3842 "intc_irq9", 3843 }; 3844 3845 static const char * const mmc_groups[] = { 3846 "mmc_data1", 3847 "mmc_data4", 3848 "mmc_data8", 3849 "mmc_ctrl", 3850 }; 3851 3852 static const char * const msiof0_groups[] = { 3853 "msiof0_clk", 3854 "msiof0_sync", 3855 "msiof0_ss1", 3856 "msiof0_ss2", 3857 "msiof0_rx", 3858 "msiof0_tx", 3859 }; 3860 3861 static const char * const msiof1_groups[] = { 3862 "msiof1_clk", 3863 "msiof1_sync", 3864 "msiof1_ss1", 3865 "msiof1_ss2", 3866 "msiof1_rx", 3867 "msiof1_tx", 3868 "msiof1_clk_b", 3869 "msiof1_sync_b", 3870 "msiof1_ss1_b", 3871 "msiof1_ss2_b", 3872 "msiof1_rx_b", 3873 "msiof1_tx_b", 3874 }; 3875 3876 static const char * const msiof2_groups[] = { 3877 "msiof2_clk", 3878 "msiof2_sync", 3879 "msiof2_ss1", 3880 "msiof2_ss2", 3881 "msiof2_rx", 3882 "msiof2_tx", 3883 "msiof2_clk_b", 3884 "msiof2_sync_b", 3885 "msiof2_ss1_b", 3886 "msiof2_ss2_b", 3887 "msiof2_rx_b", 3888 "msiof2_tx_b", 3889 }; 3890 3891 static const char * const qspi_groups[] = { 3892 "qspi_ctrl", 3893 "qspi_data2", 3894 "qspi_data4", 3895 }; 3896 3897 static const char * const scif0_groups[] = { 3898 "scif0_data", 3899 "scif0_data_b", 3900 "scif0_data_c", 3901 "scif0_data_d", 3902 }; 3903 3904 static const char * const scif1_groups[] = { 3905 "scif1_data", 3906 "scif1_clk", 3907 "scif1_data_b", 3908 "scif1_clk_b", 3909 "scif1_data_c", 3910 "scif1_clk_c", 3911 }; 3912 3913 static const char * const scif2_groups[] = { 3914 "scif2_data", 3915 "scif2_clk", 3916 "scif2_data_b", 3917 "scif2_clk_b", 3918 "scif2_data_c", 3919 "scif2_clk_c", 3920 }; 3921 3922 static const char * const scif3_groups[] = { 3923 "scif3_data", 3924 "scif3_clk", 3925 "scif3_data_b", 3926 "scif3_clk_b", 3927 }; 3928 3929 static const char * const scif4_groups[] = { 3930 "scif4_data", 3931 "scif4_data_b", 3932 "scif4_data_c", 3933 "scif4_data_d", 3934 "scif4_data_e", 3935 }; 3936 3937 static const char * const scif5_groups[] = { 3938 "scif5_data", 3939 "scif5_data_b", 3940 "scif5_data_c", 3941 "scif5_data_d", 3942 }; 3943 3944 static const char * const scifa0_groups[] = { 3945 "scifa0_data", 3946 "scifa0_data_b", 3947 "scifa0_data_c", 3948 "scifa0_data_d", 3949 }; 3950 3951 static const char * const scifa1_groups[] = { 3952 "scifa1_data", 3953 "scifa1_clk", 3954 "scifa1_data_b", 3955 "scifa1_clk_b", 3956 "scifa1_data_c", 3957 "scifa1_clk_c", 3958 }; 3959 3960 static const char * const scifa2_groups[] = { 3961 "scifa2_data", 3962 "scifa2_clk", 3963 "scifa2_data_b", 3964 "scifa2_clk_b", 3965 }; 3966 3967 static const char * const scifa3_groups[] = { 3968 "scifa3_data", 3969 "scifa3_clk", 3970 "scifa3_data_b", 3971 "scifa3_clk_b", 3972 }; 3973 3974 static const char * const scifa4_groups[] = { 3975 "scifa4_data", 3976 "scifa4_data_b", 3977 "scifa4_data_c", 3978 "scifa4_data_d", 3979 }; 3980 3981 static const char * const scifa5_groups[] = { 3982 "scifa5_data", 3983 "scifa5_data_b", 3984 "scifa5_data_c", 3985 "scifa5_data_d", 3986 }; 3987 3988 static const char * const scifb0_groups[] = { 3989 "scifb0_data", 3990 "scifb0_clk", 3991 "scifb0_ctrl", 3992 }; 3993 3994 static const char * const scifb1_groups[] = { 3995 "scifb1_data", 3996 "scifb1_clk", 3997 }; 3998 3999 static const char * const scifb2_groups[] = { 4000 "scifb2_data", 4001 "scifb2_clk", 4002 "scifb2_ctrl", 4003 }; 4004 4005 static const char * const scif_clk_groups[] = { 4006 "scif_clk", 4007 "scif_clk_b", 4008 }; 4009 4010 static const char * const sdhi0_groups[] = { 4011 "sdhi0_data1", 4012 "sdhi0_data4", 4013 "sdhi0_ctrl", 4014 "sdhi0_cd", 4015 "sdhi0_wp", 4016 }; 4017 4018 static const char * const sdhi1_groups[] = { 4019 "sdhi1_data1", 4020 "sdhi1_data4", 4021 "sdhi1_ctrl", 4022 "sdhi1_cd", 4023 "sdhi1_wp", 4024 }; 4025 4026 static const char * const sdhi2_groups[] = { 4027 "sdhi2_data1", 4028 "sdhi2_data4", 4029 "sdhi2_ctrl", 4030 "sdhi2_cd", 4031 "sdhi2_wp", 4032 }; 4033 4034 static const char * const ssi_groups[] = { 4035 "ssi0_data", 4036 "ssi0129_ctrl", 4037 "ssi1_data", 4038 "ssi1_ctrl", 4039 "ssi1_data_b", 4040 "ssi1_ctrl_b", 4041 "ssi2_data", 4042 "ssi2_ctrl", 4043 "ssi2_data_b", 4044 "ssi2_ctrl_b", 4045 "ssi3_data", 4046 "ssi34_ctrl", 4047 "ssi4_data", 4048 "ssi4_ctrl", 4049 "ssi4_data_b", 4050 "ssi4_ctrl_b", 4051 "ssi5_data", 4052 "ssi5_ctrl", 4053 "ssi5_data_b", 4054 "ssi5_ctrl_b", 4055 "ssi6_data", 4056 "ssi6_ctrl", 4057 "ssi6_data_b", 4058 "ssi6_ctrl_b", 4059 "ssi7_data", 4060 "ssi78_ctrl", 4061 "ssi7_data_b", 4062 "ssi78_ctrl_b", 4063 "ssi8_data", 4064 "ssi8_data_b", 4065 "ssi9_data", 4066 "ssi9_ctrl", 4067 "ssi9_data_b", 4068 "ssi9_ctrl_b", 4069 }; 4070 4071 static const char * const usb0_groups[] = { 4072 "usb0", 4073 }; 4074 4075 static const char * const usb1_groups[] = { 4076 "usb1", 4077 }; 4078 4079 static const char * const vin0_groups[] = { 4080 "vin0_data24", 4081 "vin0_data20", 4082 "vin0_data18", 4083 "vin0_data16", 4084 "vin0_data12", 4085 "vin0_data10", 4086 "vin0_data8", 4087 "vin0_sync", 4088 "vin0_field", 4089 "vin0_clkenb", 4090 "vin0_clk", 4091 }; 4092 4093 static const char * const vin1_groups[] = { 4094 "vin1_data12", 4095 "vin1_data10", 4096 "vin1_data8", 4097 "vin1_sync", 4098 "vin1_field", 4099 "vin1_clkenb", 4100 "vin1_clk", 4101 }; 4102 4103 static const struct sh_pfc_function pinmux_functions[] = { 4104 SH_PFC_FUNCTION(audio_clk), 4105 SH_PFC_FUNCTION(avb), 4106 SH_PFC_FUNCTION(du0), 4107 SH_PFC_FUNCTION(du1), 4108 SH_PFC_FUNCTION(eth), 4109 SH_PFC_FUNCTION(hscif0), 4110 SH_PFC_FUNCTION(hscif1), 4111 SH_PFC_FUNCTION(hscif2), 4112 SH_PFC_FUNCTION(i2c0), 4113 SH_PFC_FUNCTION(i2c1), 4114 SH_PFC_FUNCTION(i2c2), 4115 SH_PFC_FUNCTION(i2c3), 4116 SH_PFC_FUNCTION(i2c4), 4117 SH_PFC_FUNCTION(intc), 4118 SH_PFC_FUNCTION(mmc), 4119 SH_PFC_FUNCTION(msiof0), 4120 SH_PFC_FUNCTION(msiof1), 4121 SH_PFC_FUNCTION(msiof2), 4122 SH_PFC_FUNCTION(qspi), 4123 SH_PFC_FUNCTION(scif0), 4124 SH_PFC_FUNCTION(scif1), 4125 SH_PFC_FUNCTION(scif2), 4126 SH_PFC_FUNCTION(scif3), 4127 SH_PFC_FUNCTION(scif4), 4128 SH_PFC_FUNCTION(scif5), 4129 SH_PFC_FUNCTION(scifa0), 4130 SH_PFC_FUNCTION(scifa1), 4131 SH_PFC_FUNCTION(scifa2), 4132 SH_PFC_FUNCTION(scifa3), 4133 SH_PFC_FUNCTION(scifa4), 4134 SH_PFC_FUNCTION(scifa5), 4135 SH_PFC_FUNCTION(scifb0), 4136 SH_PFC_FUNCTION(scifb1), 4137 SH_PFC_FUNCTION(scifb2), 4138 SH_PFC_FUNCTION(scif_clk), 4139 SH_PFC_FUNCTION(sdhi0), 4140 SH_PFC_FUNCTION(sdhi1), 4141 SH_PFC_FUNCTION(sdhi2), 4142 SH_PFC_FUNCTION(ssi), 4143 SH_PFC_FUNCTION(usb0), 4144 SH_PFC_FUNCTION(usb1), 4145 SH_PFC_FUNCTION(vin0), 4146 SH_PFC_FUNCTION(vin1), 4147 }; 4148 4149 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4150 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 4151 GP_0_31_FN, FN_IP2_17_16, 4152 GP_0_30_FN, FN_IP2_15_14, 4153 GP_0_29_FN, FN_IP2_13_12, 4154 GP_0_28_FN, FN_IP2_11_10, 4155 GP_0_27_FN, FN_IP2_9_8, 4156 GP_0_26_FN, FN_IP2_7_6, 4157 GP_0_25_FN, FN_IP2_5_4, 4158 GP_0_24_FN, FN_IP2_3_2, 4159 GP_0_23_FN, FN_IP2_1_0, 4160 GP_0_22_FN, FN_IP1_31_30, 4161 GP_0_21_FN, FN_IP1_29_28, 4162 GP_0_20_FN, FN_IP1_27, 4163 GP_0_19_FN, FN_IP1_26, 4164 GP_0_18_FN, FN_A2, 4165 GP_0_17_FN, FN_IP1_24, 4166 GP_0_16_FN, FN_IP1_23_22, 4167 GP_0_15_FN, FN_IP1_21_20, 4168 GP_0_14_FN, FN_IP1_19_18, 4169 GP_0_13_FN, FN_IP1_17_15, 4170 GP_0_12_FN, FN_IP1_14_13, 4171 GP_0_11_FN, FN_IP1_12_11, 4172 GP_0_10_FN, FN_IP1_10_8, 4173 GP_0_9_FN, FN_IP1_7_6, 4174 GP_0_8_FN, FN_IP1_5_4, 4175 GP_0_7_FN, FN_IP1_3_2, 4176 GP_0_6_FN, FN_IP1_1_0, 4177 GP_0_5_FN, FN_IP0_31_30, 4178 GP_0_4_FN, FN_IP0_29_28, 4179 GP_0_3_FN, FN_IP0_27_26, 4180 GP_0_2_FN, FN_IP0_25, 4181 GP_0_1_FN, FN_IP0_24, 4182 GP_0_0_FN, FN_IP0_23_22, } 4183 }, 4184 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 4185 0, 0, 4186 0, 0, 4187 0, 0, 4188 0, 0, 4189 0, 0, 4190 0, 0, 4191 GP_1_25_FN, FN_DACK0, 4192 GP_1_24_FN, FN_IP7_31, 4193 GP_1_23_FN, FN_IP4_1_0, 4194 GP_1_22_FN, FN_WE1_N, 4195 GP_1_21_FN, FN_WE0_N, 4196 GP_1_20_FN, FN_IP3_31, 4197 GP_1_19_FN, FN_IP3_30, 4198 GP_1_18_FN, FN_IP3_29_27, 4199 GP_1_17_FN, FN_IP3_26_24, 4200 GP_1_16_FN, FN_IP3_23_21, 4201 GP_1_15_FN, FN_IP3_20_18, 4202 GP_1_14_FN, FN_IP3_17_15, 4203 GP_1_13_FN, FN_IP3_14_13, 4204 GP_1_12_FN, FN_IP3_12, 4205 GP_1_11_FN, FN_IP3_11, 4206 GP_1_10_FN, FN_IP3_10, 4207 GP_1_9_FN, FN_IP3_9_8, 4208 GP_1_8_FN, FN_IP3_7_6, 4209 GP_1_7_FN, FN_IP3_5_4, 4210 GP_1_6_FN, FN_IP3_3_2, 4211 GP_1_5_FN, FN_IP3_1_0, 4212 GP_1_4_FN, FN_IP2_31_30, 4213 GP_1_3_FN, FN_IP2_29_27, 4214 GP_1_2_FN, FN_IP2_26_24, 4215 GP_1_1_FN, FN_IP2_23_21, 4216 GP_1_0_FN, FN_IP2_20_18, } 4217 }, 4218 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 4219 GP_2_31_FN, FN_IP6_7_6, 4220 GP_2_30_FN, FN_IP6_5_4, 4221 GP_2_29_FN, FN_IP6_3_2, 4222 GP_2_28_FN, FN_IP6_1_0, 4223 GP_2_27_FN, FN_IP5_31_30, 4224 GP_2_26_FN, FN_IP5_29_28, 4225 GP_2_25_FN, FN_IP5_27_26, 4226 GP_2_24_FN, FN_IP5_25_24, 4227 GP_2_23_FN, FN_IP5_23_22, 4228 GP_2_22_FN, FN_IP5_21_20, 4229 GP_2_21_FN, FN_IP5_19_18, 4230 GP_2_20_FN, FN_IP5_17_16, 4231 GP_2_19_FN, FN_IP5_15_14, 4232 GP_2_18_FN, FN_IP5_13_12, 4233 GP_2_17_FN, FN_IP5_11_9, 4234 GP_2_16_FN, FN_IP5_8_6, 4235 GP_2_15_FN, FN_IP5_5_4, 4236 GP_2_14_FN, FN_IP5_3_2, 4237 GP_2_13_FN, FN_IP5_1_0, 4238 GP_2_12_FN, FN_IP4_31_30, 4239 GP_2_11_FN, FN_IP4_29_28, 4240 GP_2_10_FN, FN_IP4_27_26, 4241 GP_2_9_FN, FN_IP4_25_23, 4242 GP_2_8_FN, FN_IP4_22_20, 4243 GP_2_7_FN, FN_IP4_19_18, 4244 GP_2_6_FN, FN_IP4_17_16, 4245 GP_2_5_FN, FN_IP4_15_14, 4246 GP_2_4_FN, FN_IP4_13_12, 4247 GP_2_3_FN, FN_IP4_11_10, 4248 GP_2_2_FN, FN_IP4_9_8, 4249 GP_2_1_FN, FN_IP4_7_5, 4250 GP_2_0_FN, FN_IP4_4_2 } 4251 }, 4252 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 4253 GP_3_31_FN, FN_IP8_22_20, 4254 GP_3_30_FN, FN_IP8_19_17, 4255 GP_3_29_FN, FN_IP8_16_15, 4256 GP_3_28_FN, FN_IP8_14_12, 4257 GP_3_27_FN, FN_IP8_11_9, 4258 GP_3_26_FN, FN_IP8_8_6, 4259 GP_3_25_FN, FN_IP8_5_3, 4260 GP_3_24_FN, FN_IP8_2_0, 4261 GP_3_23_FN, FN_IP7_29_27, 4262 GP_3_22_FN, FN_IP7_26_24, 4263 GP_3_21_FN, FN_IP7_23_21, 4264 GP_3_20_FN, FN_IP7_20_18, 4265 GP_3_19_FN, FN_IP7_17_15, 4266 GP_3_18_FN, FN_IP7_14_12, 4267 GP_3_17_FN, FN_IP7_11_9, 4268 GP_3_16_FN, FN_IP7_8_6, 4269 GP_3_15_FN, FN_IP7_5_3, 4270 GP_3_14_FN, FN_IP7_2_0, 4271 GP_3_13_FN, FN_IP6_31_29, 4272 GP_3_12_FN, FN_IP6_28_26, 4273 GP_3_11_FN, FN_IP6_25_23, 4274 GP_3_10_FN, FN_IP6_22_20, 4275 GP_3_9_FN, FN_IP6_19_17, 4276 GP_3_8_FN, FN_IP6_16, 4277 GP_3_7_FN, FN_IP6_15, 4278 GP_3_6_FN, FN_IP6_14, 4279 GP_3_5_FN, FN_IP6_13, 4280 GP_3_4_FN, FN_IP6_12, 4281 GP_3_3_FN, FN_IP6_11, 4282 GP_3_2_FN, FN_IP6_10, 4283 GP_3_1_FN, FN_IP6_9, 4284 GP_3_0_FN, FN_IP6_8 } 4285 }, 4286 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 4287 GP_4_31_FN, FN_IP11_17_16, 4288 GP_4_30_FN, FN_IP11_15_14, 4289 GP_4_29_FN, FN_IP11_13_11, 4290 GP_4_28_FN, FN_IP11_10_8, 4291 GP_4_27_FN, FN_IP11_7_6, 4292 GP_4_26_FN, FN_IP11_5_3, 4293 GP_4_25_FN, FN_IP11_2_0, 4294 GP_4_24_FN, FN_IP10_31_30, 4295 GP_4_23_FN, FN_IP10_29_27, 4296 GP_4_22_FN, FN_IP10_26_24, 4297 GP_4_21_FN, FN_IP10_23_21, 4298 GP_4_20_FN, FN_IP10_20_18, 4299 GP_4_19_FN, FN_IP10_17_15, 4300 GP_4_18_FN, FN_IP10_14_12, 4301 GP_4_17_FN, FN_IP10_11_9, 4302 GP_4_16_FN, FN_IP10_8_6, 4303 GP_4_15_FN, FN_IP10_5_3, 4304 GP_4_14_FN, FN_IP10_2_0, 4305 GP_4_13_FN, FN_IP9_30_28, 4306 GP_4_12_FN, FN_IP9_27_25, 4307 GP_4_11_FN, FN_IP9_24_22, 4308 GP_4_10_FN, FN_IP9_21_19, 4309 GP_4_9_FN, FN_IP9_18_17, 4310 GP_4_8_FN, FN_IP9_16_15, 4311 GP_4_7_FN, FN_IP9_14_12, 4312 GP_4_6_FN, FN_IP9_11_9, 4313 GP_4_5_FN, FN_IP9_8_6, 4314 GP_4_4_FN, FN_IP9_5_3, 4315 GP_4_3_FN, FN_IP9_2_0, 4316 GP_4_2_FN, FN_IP8_31_29, 4317 GP_4_1_FN, FN_IP8_28_26, 4318 GP_4_0_FN, FN_IP8_25_23 } 4319 }, 4320 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 4321 0, 0, 4322 0, 0, 4323 0, 0, 4324 0, 0, 4325 GP_5_27_FN, FN_USB1_OVC, 4326 GP_5_26_FN, FN_USB1_PWEN, 4327 GP_5_25_FN, FN_USB0_OVC, 4328 GP_5_24_FN, FN_USB0_PWEN, 4329 GP_5_23_FN, FN_IP13_26_24, 4330 GP_5_22_FN, FN_IP13_23_21, 4331 GP_5_21_FN, FN_IP13_20_18, 4332 GP_5_20_FN, FN_IP13_17_15, 4333 GP_5_19_FN, FN_IP13_14_12, 4334 GP_5_18_FN, FN_IP13_11_9, 4335 GP_5_17_FN, FN_IP13_8_6, 4336 GP_5_16_FN, FN_IP13_5_3, 4337 GP_5_15_FN, FN_IP13_2_0, 4338 GP_5_14_FN, FN_IP12_29_27, 4339 GP_5_13_FN, FN_IP12_26_24, 4340 GP_5_12_FN, FN_IP12_23_21, 4341 GP_5_11_FN, FN_IP12_20_18, 4342 GP_5_10_FN, FN_IP12_17_15, 4343 GP_5_9_FN, FN_IP12_14_13, 4344 GP_5_8_FN, FN_IP12_12_11, 4345 GP_5_7_FN, FN_IP12_10_9, 4346 GP_5_6_FN, FN_IP12_8_6, 4347 GP_5_5_FN, FN_IP12_5_3, 4348 GP_5_4_FN, FN_IP12_2_0, 4349 GP_5_3_FN, FN_IP11_29_27, 4350 GP_5_2_FN, FN_IP11_26_24, 4351 GP_5_1_FN, FN_IP11_23_21, 4352 GP_5_0_FN, FN_IP11_20_18 } 4353 }, 4354 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { 4355 0, 0, 4356 0, 0, 4357 0, 0, 4358 0, 0, 4359 0, 0, 4360 0, 0, 4361 GP_6_25_FN, FN_IP0_21_20, 4362 GP_6_24_FN, FN_IP0_19_18, 4363 GP_6_23_FN, FN_IP0_17, 4364 GP_6_22_FN, FN_IP0_16, 4365 GP_6_21_FN, FN_IP0_15, 4366 GP_6_20_FN, FN_IP0_14, 4367 GP_6_19_FN, FN_IP0_13, 4368 GP_6_18_FN, FN_IP0_12, 4369 GP_6_17_FN, FN_IP0_11, 4370 GP_6_16_FN, FN_IP0_10, 4371 GP_6_15_FN, FN_IP0_9_8, 4372 GP_6_14_FN, FN_IP0_0, 4373 GP_6_13_FN, FN_SD1_DATA3, 4374 GP_6_12_FN, FN_SD1_DATA2, 4375 GP_6_11_FN, FN_SD1_DATA1, 4376 GP_6_10_FN, FN_SD1_DATA0, 4377 GP_6_9_FN, FN_SD1_CMD, 4378 GP_6_8_FN, FN_SD1_CLK, 4379 GP_6_7_FN, FN_SD0_WP, 4380 GP_6_6_FN, FN_SD0_CD, 4381 GP_6_5_FN, FN_SD0_DATA3, 4382 GP_6_4_FN, FN_SD0_DATA2, 4383 GP_6_3_FN, FN_SD0_DATA1, 4384 GP_6_2_FN, FN_SD0_DATA0, 4385 GP_6_1_FN, FN_SD0_CMD, 4386 GP_6_0_FN, FN_SD0_CLK } 4387 }, 4388 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 4389 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 4390 2, 1, 1, 1, 1, 1, 1, 1, 1) { 4391 /* IP0_31_30 [2] */ 4392 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, 4393 /* IP0_29_28 [2] */ 4394 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0, 4395 /* IP0_27_26 [2] */ 4396 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0, 4397 /* IP0_25 [1] */ 4398 FN_D2, FN_SCIFA3_TXD_B, 4399 /* IP0_24 [1] */ 4400 FN_D1, FN_SCIFA3_RXD_B, 4401 /* IP0_23_22 [2] */ 4402 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0, 4403 /* IP0_21_20 [2] */ 4404 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX, 4405 /* IP0_19_18 [2] */ 4406 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX, 4407 /* IP0_17 [1] */ 4408 FN_MMC_D5, FN_SD2_WP, 4409 /* IP0_16 [1] */ 4410 FN_MMC_D4, FN_SD2_CD, 4411 /* IP0_15 [1] */ 4412 FN_MMC_D3, FN_SD2_DATA3, 4413 /* IP0_14 [1] */ 4414 FN_MMC_D2, FN_SD2_DATA2, 4415 /* IP0_13 [1] */ 4416 FN_MMC_D1, FN_SD2_DATA1, 4417 /* IP0_12 [1] */ 4418 FN_MMC_D0, FN_SD2_DATA0, 4419 /* IP0_11 [1] */ 4420 FN_MMC_CMD, FN_SD2_CMD, 4421 /* IP0_10 [1] */ 4422 FN_MMC_CLK, FN_SD2_CLK, 4423 /* IP0_9_8 [2] */ 4424 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0, 4425 /* IP0_7 [1] */ 4426 0, 0, 4427 /* IP0_6 [1] */ 4428 0, 0, 4429 /* IP0_5 [1] */ 4430 0, 0, 4431 /* IP0_4 [1] */ 4432 0, 0, 4433 /* IP0_3 [1] */ 4434 0, 0, 4435 /* IP0_2 [1] */ 4436 0, 0, 4437 /* IP0_1 [1] */ 4438 0, 0, 4439 /* IP0_0 [1] */ 4440 FN_SD1_CD, FN_CAN0_RX, } 4441 }, 4442 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 4443 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, 4444 2, 2) { 4445 /* IP1_31_30 [2] */ 4446 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, 4447 /* IP1_29_28 [2] */ 4448 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, 4449 /* IP1_27 [1] */ 4450 FN_A4, FN_SCIFB0_TXD, 4451 /* IP1_26 [1] */ 4452 FN_A3, FN_SCIFB0_SCK, 4453 /* IP1_25 [1] */ 4454 0, 0, 4455 /* IP1_24 [1] */ 4456 FN_A1, FN_SCIFB1_TXD, 4457 /* IP1_23_22 [2] */ 4458 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0, 4459 /* IP1_21_20 [2] */ 4460 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0, 4461 /* IP1_19_18 [2] */ 4462 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0, 4463 /* IP1_17_15 [3] */ 4464 FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B, 4465 0, 0, 0, 4466 /* IP1_14_13 [2] */ 4467 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, 4468 /* IP1_12_11 [2] */ 4469 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, 4470 /* IP1_10_8 [3] */ 4471 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, 4472 0, 0, 0, 4473 /* IP1_7_6 [2] */ 4474 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0, 4475 /* IP1_5_4 [2] */ 4476 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0, 4477 /* IP1_3_2 [2] */ 4478 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, 4479 /* IP1_1_0 [2] */ 4480 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, } 4481 }, 4482 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 4483 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { 4484 /* IP2_31_30 [2] */ 4485 FN_A20, FN_SPCLK, 0, 0, 4486 /* IP2_29_27 [3] */ 4487 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, 4488 0, 0, 0, 0, 4489 /* IP2_26_24 [3] */ 4490 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, 4491 0, 0, 0, 0, 4492 /* IP2_23_21 [3] */ 4493 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, 4494 0, 0, 0, 0, 4495 /* IP2_20_18 [3] */ 4496 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, 4497 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0, 4498 /* IP2_17_16 [2] */ 4499 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, 4500 /* IP2_15_14 [2] */ 4501 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, 4502 /* IP2_13_12 [2] */ 4503 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0, 4504 /* IP2_11_10 [2] */ 4505 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0, 4506 /* IP2_9_8 [2] */ 4507 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0, 4508 /* IP2_7_6 [2] */ 4509 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0, 4510 /* IP2_5_4 [2] */ 4511 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0, 4512 /* IP2_3_2 [2] */ 4513 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, 4514 /* IP2_1_0 [2] */ 4515 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, } 4516 }, 4517 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 4518 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) { 4519 /* IP3_31 [1] */ 4520 FN_RD_WR_N, FN_ATAG1_N, 4521 /* IP3_30 [1] */ 4522 FN_RD_N, FN_ATACS11_N, 4523 /* IP3_29_27 [3] */ 4524 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, 4525 0, 0, 0, 4526 /* IP3_26_24 [3] */ 4527 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, 4528 0, FN_FMIN, FN_SCIFB2_RTS_N, 0, 4529 /* IP3_23_21 [3] */ 4530 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, 4531 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0, 4532 /* IP3_20_18 [3] */ 4533 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, 4534 0, FN_BPFCLK, FN_SCIFB2_SCK, 0, 4535 /* IP3_17_15 [3] */ 4536 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, 4537 0, FN_TPUTO3, FN_SCIFB2_TXD, 0, 4538 /* IP3_14_13 [2] */ 4539 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, 4540 /* IP3_12 [1] */ 4541 FN_EX_CS0_N, FN_VI1_DATA10, 4542 /* IP3_11 [1] */ 4543 FN_CS1_N_A26, FN_VI1_DATA9, 4544 /* IP3_10 [1] */ 4545 FN_CS0_N, FN_VI1_DATA8, 4546 /* IP3_9_8 [2] */ 4547 FN_A25, FN_SSL, FN_ATARD1_N, 0, 4548 /* IP3_7_6 [2] */ 4549 FN_A24, FN_IO3, FN_EX_WAIT2, 0, 4550 /* IP3_5_4 [2] */ 4551 FN_A23, FN_IO2, 0, FN_ATAWR1_N, 4552 /* IP3_3_2 [2] */ 4553 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N, 4554 /* IP3_1_0 [2] */ 4555 FN_A21, FN_MOSI_IO0, 0, 0, } 4556 }, 4557 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 4558 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { 4559 /* IP4_31_30 [2] */ 4560 FN_DU0_DG4, FN_LCDOUT12, 0, 0, 4561 /* IP4_29_28 [2] */ 4562 FN_DU0_DG3, FN_LCDOUT11, 0, 0, 4563 /* IP4_27_26 [2] */ 4564 FN_DU0_DG2, FN_LCDOUT10, 0, 0, 4565 /* IP4_25_23 [3] */ 4566 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, 4567 0, 0, 0, 0, 4568 /* IP4_22_20 [3] */ 4569 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, 4570 0, 0, 0, 0, 4571 /* IP4_19_18 [2] */ 4572 FN_DU0_DR7, FN_LCDOUT23, 0, 0, 4573 /* IP4_17_16 [2] */ 4574 FN_DU0_DR6, FN_LCDOUT22, 0, 0, 4575 /* IP4_15_14 [2] */ 4576 FN_DU0_DR5, FN_LCDOUT21, 0, 0, 4577 /* IP4_13_12 [2] */ 4578 FN_DU0_DR4, FN_LCDOUT20, 0, 0, 4579 /* IP4_11_10 [2] */ 4580 FN_DU0_DR3, FN_LCDOUT19, 0, 0, 4581 /* IP4_9_8 [2] */ 4582 FN_DU0_DR2, FN_LCDOUT18, 0, 0, 4583 /* IP4_7_5 [3] */ 4584 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, 4585 0, 0, 0, 0, 4586 /* IP4_4_2 [3] */ 4587 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, 4588 0, 0, 0, 0, 4589 /* IP4_1_0 [2] */ 4590 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, } 4591 }, 4592 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 4593 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { 4594 /* IP5_31_30 [2] */ 4595 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0, 4596 /* IP5_29_28 [2] */ 4597 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0, 4598 /* IP5_27_26 [2] */ 4599 FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0, 4600 /* IP5_25_24 [2] */ 4601 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0, 4602 /* IP5_23_22 [2] */ 4603 FN_DU0_DB7, FN_LCDOUT7, 0, 0, 4604 /* IP5_21_20 [2] */ 4605 FN_DU0_DB6, FN_LCDOUT6, 0, 0, 4606 /* IP5_19_18 [2] */ 4607 FN_DU0_DB5, FN_LCDOUT5, 0, 0, 4608 /* IP5_17_16 [2] */ 4609 FN_DU0_DB4, FN_LCDOUT4, 0, 0, 4610 /* IP5_15_14 [2] */ 4611 FN_DU0_DB3, FN_LCDOUT3, 0, 0, 4612 /* IP5_13_12 [2] */ 4613 FN_DU0_DB2, FN_LCDOUT2, 0, 0, 4614 /* IP5_11_9 [3] */ 4615 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, 4616 FN_CAN0_TX_C, 0, 0, 0, 4617 /* IP5_8_6 [3] */ 4618 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, 4619 FN_CAN0_RX_C, 0, 0, 0, 4620 /* IP5_5_4 [2] */ 4621 FN_DU0_DG7, FN_LCDOUT15, 0, 0, 4622 /* IP5_3_2 [2] */ 4623 FN_DU0_DG6, FN_LCDOUT14, 0, 0, 4624 /* IP5_1_0 [2] */ 4625 FN_DU0_DG5, FN_LCDOUT13, 0, 0, } 4626 }, 4627 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 4628 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 4629 2, 2) { 4630 /* IP6_31_29 [3] */ 4631 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, 4632 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0, 4633 /* IP6_28_26 [3] */ 4634 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, 4635 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, 4636 /* IP6_25_23 [3] */ 4637 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, 4638 FN_AVB_COL, 0, 0, 0, 4639 /* IP6_22_20 [3] */ 4640 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, 4641 FN_AVB_RX_ER, 0, 0, 0, 4642 /* IP6_19_17 [3] */ 4643 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, 4644 FN_AVB_RXD7, 0, 0, 0, 4645 /* IP6_16 [1] */ 4646 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, 4647 /* IP6_15 [1] */ 4648 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, 4649 /* IP6_14 [1] */ 4650 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, 4651 /* IP6_13 [1] */ 4652 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, 4653 /* IP6_12 [1] */ 4654 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, 4655 /* IP6_11 [1] */ 4656 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, 4657 /* IP6_10 [1] */ 4658 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, 4659 /* IP6_9 [1] */ 4660 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, 4661 /* IP6_8 [1] */ 4662 FN_VI0_CLK, FN_AVB_RX_CLK, 4663 /* IP6_7_6 [2] */ 4664 FN_DU0_CDE, FN_QPOLB, 0, 0, 4665 /* IP6_5_4 [2] */ 4666 FN_DU0_DISP, FN_QPOLA, 0, 0, 4667 /* IP6_3_2 [2] */ 4668 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 4669 0, 4670 /* IP6_1_0 [2] */ 4671 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, } 4672 }, 4673 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 4674 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 4675 /* IP7_31 [1] */ 4676 FN_DREQ0_N, FN_SCIFB1_RXD, 4677 /* IP7_30 [1] */ 4678 0, 0, 4679 /* IP7_29_27 [3] */ 4680 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, 4681 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, 4682 /* IP7_26_24 [3] */ 4683 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, 4684 FN_SSI_SCK6_B, 0, 0, 0, 4685 /* IP7_23_21 [3] */ 4686 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, 4687 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, 4688 /* IP7_20_18 [3] */ 4689 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, 4690 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, 4691 /* IP7_17_15 [3] */ 4692 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, 4693 FN_SSI_SCK5_B, 0, 0, 0, 4694 /* IP7_14_12 [3] */ 4695 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, 4696 FN_AVB_TXD4, FN_ADICHS2, 0, 0, 4697 /* IP7_11_9 [3] */ 4698 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, 4699 FN_AVB_TXD3, FN_ADICHS1, 0, 0, 4700 /* IP7_8_6 [3] */ 4701 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, 4702 FN_AVB_TXD2, FN_ADICHS0, 0, 0, 4703 /* IP7_5_3 [3] */ 4704 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, 4705 FN_AVB_TXD1, FN_ADICLK, 0, 0, 4706 /* IP7_2_0 [3] */ 4707 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, 4708 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, } 4709 }, 4710 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 4711 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { 4712 /* IP8_31_29 [3] */ 4713 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, 4714 0, FN_TS_SDEN_D, FN_FMCLK_C, 0, 4715 /* IP8_28_26 [3] */ 4716 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, 4717 0, FN_TS_SCK_D, FN_BPFCLK_C, 0, 4718 /* IP8_25_23 [3] */ 4719 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, 4720 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0, 4721 /* IP8_22_20 [3] */ 4722 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, 4723 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, 4724 /* IP8_19_17 [3] */ 4725 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, 4726 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, 4727 /* IP8_16_15 [2] */ 4728 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, 4729 /* IP8_14_12 [3] */ 4730 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, 4731 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, 4732 /* IP8_11_9 [3] */ 4733 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, 4734 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, 4735 /* IP8_8_6 [3] */ 4736 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, 4737 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, 4738 /* IP8_5_3 [3] */ 4739 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, 4740 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, 4741 /* IP8_2_0 [3] */ 4742 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, 4743 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } 4744 }, 4745 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 4746 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) { 4747 /* IP9_31 [1] */ 4748 0, 0, 4749 /* IP9_30_28 [3] */ 4750 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, 4751 FN_SSI_SDATA1_B, 0, 0, 0, 4752 /* IP9_27_25 [3] */ 4753 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, 4754 FN_SSI_WS1_B, 0, 0, 0, 4755 /* IP9_24_22 [3] */ 4756 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, 4757 FN_SSI_SCK1_B, 0, 0, 0, 4758 /* IP9_21_19 [3] */ 4759 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, 4760 FN_REMOCON_B, FN_SPEEDIN_B, 0, 0, 4761 /* IP9_18_17 [2] */ 4762 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, 4763 /* IP9_16_15 [2] */ 4764 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, 4765 /* IP9_14_12 [3] */ 4766 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, 4767 0, FN_FMIN_B, 0, 0, 4768 /* IP9_11_9 [3] */ 4769 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, 4770 0, FN_FMCLK_B, 0, 0, 4771 /* IP9_8_6 [3] */ 4772 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, 4773 0, FN_BPFCLK_B, 0, 0, 4774 /* IP9_5_3 [3] */ 4775 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, 4776 0, FN_TPUTO1_C, 0, 0, 4777 /* IP9_2_0 [3] */ 4778 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, 4779 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, } 4780 }, 4781 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 4782 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 4783 /* IP10_31_30 [2] */ 4784 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0, 4785 /* IP10_29_27 [3] */ 4786 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, 4787 0, 0, 0, 0, 4788 /* IP10_26_24 [3] */ 4789 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, 4790 FN_SSI_SDATA4_B, 0, 0, 0, 4791 /* IP10_23_21 [3] */ 4792 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, 4793 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 4794 /* IP10_20_18 [3] */ 4795 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, 4796 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0, 4797 /* IP10_17_15 [3] */ 4798 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, 4799 FN_SSI_SDATA9_B, 0, 0, 0, 4800 /* IP10_14_12 [3] */ 4801 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, 4802 0, 0, 0, 0, 4803 /* IP10_11_9 [3] */ 4804 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, 4805 0, 0, 0, 0, 4806 /* IP10_8_6 [3] */ 4807 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, 4808 0, 0, 0, 0, 4809 /* IP10_5_3 [3] */ 4810 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B, 4811 0, 0, 0, 0, 4812 /* IP10_2_0 [3] */ 4813 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, 4814 0, 0, 0, 0, } 4815 }, 4816 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 4817 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { 4818 /* IP11_31_30 [2] */ 4819 0, 0, 0, 0, 4820 /* IP11_29_27 [3] */ 4821 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, 4822 0, 0, 0, 0, 4823 /* IP11_26_24 [3] */ 4824 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, 4825 0, 0, 0, 0, 4826 /* IP11_23_21 [3] */ 4827 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, 4828 0, 0, 0, 0, 4829 /* IP11_20_18 [3] */ 4830 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, 4831 FN_CAN_CLK_D, 0, 0, 0, 4832 /* IP11_17_16 [2] */ 4833 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, 4834 /* IP11_15_14 [2] */ 4835 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, 4836 /* IP11_13_11 [3] */ 4837 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, 4838 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0, 4839 /* IP11_10_8 [3] */ 4840 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, 4841 FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0, 4842 /* IP11_7_6 [2] */ 4843 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 4844 /* IP11_5_3 [3] */ 4845 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, 4846 0, 0, 0, 0, 4847 /* IP11_2_0 [3] */ 4848 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, 4849 0, 0, 0, 0, } 4850 }, 4851 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 4852 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { 4853 /* IP12_31_30 [2] */ 4854 0, 0, 0, 0, 4855 /* IP12_29_27 [3] */ 4856 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0, 4857 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0, 4858 /* IP12_26_24 [3] */ 4859 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0, 4860 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0, 4861 /* IP12_23_21 [3] */ 4862 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, 4863 FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0, 4864 /* IP12_20_18 [3] */ 4865 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, 4866 FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0, 4867 /* IP12_17_15 [3] */ 4868 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, 4869 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0, 4870 /* IP12_14_13 [2] */ 4871 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0, 4872 /* IP12_12_11 [2] */ 4873 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0, 4874 /* IP12_10_9 [2] */ 4875 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0, 4876 /* IP12_8_6 [3] */ 4877 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, 4878 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0, 4879 /* IP12_5_3 [3] */ 4880 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, 4881 FN_CAN1_RX_C, FN_DACK1_B, 0, 0, 4882 /* IP12_2_0 [3] */ 4883 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, 4884 0, FN_DREQ1_N_B, 0, 0, } 4885 }, 4886 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 4887 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 4888 /* IP13_31 [1] */ 4889 0, 0, 4890 /* IP13_30 [1] */ 4891 0, 0, 4892 /* IP13_29 [1] */ 4893 0, 0, 4894 /* IP13_28 [1] */ 4895 0, 0, 4896 /* IP13_27 [1] */ 4897 0, 0, 4898 /* IP13_26_24 [3] */ 4899 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, 4900 FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0, 4901 /* IP13_23_21 [3] */ 4902 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, 4903 FN_TS_SDEN_C, 0, FN_FMCLK_E, 0, 4904 /* IP13_20_18 [3] */ 4905 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, 4906 FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B, 4907 /* IP13_17_15 [3] */ 4908 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, 4909 FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0, 4910 /* IP13_14_12 [3] */ 4911 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, 4912 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0, 4913 /* IP13_11_9 [3] */ 4914 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, 4915 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0, 4916 /* IP13_8_6 [3] */ 4917 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, 4918 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0, 4919 /* IP13_5_3 [2] */ 4920 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, 4921 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, 4922 /* IP13_2_0 [3] */ 4923 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, 4924 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, } 4925 }, 4926 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 4927 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 4928 2, 1) { 4929 /* SEL_ADG [2] */ 4930 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, 4931 /* RESERVED [1] */ 4932 0, 0, 4933 /* SEL_CAN [2] */ 4934 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, 4935 /* SEL_DARC [3] */ 4936 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, 4937 FN_SEL_DARC_4, 0, 0, 0, 4938 /* RESERVED [4] */ 4939 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4940 /* SEL_ETH [1] */ 4941 FN_SEL_ETH_0, FN_SEL_ETH_1, 4942 /* RESERVED [1] */ 4943 0, 0, 4944 /* SEL_IC200 [3] */ 4945 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, 4946 FN_SEL_I2C00_4, 0, 0, 0, 4947 /* SEL_I2C01 [3] */ 4948 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, 4949 FN_SEL_I2C01_4, 0, 0, 0, 4950 /* SEL_I2C02 [3] */ 4951 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, 4952 FN_SEL_I2C02_4, 0, 0, 0, 4953 /* SEL_I2C03 [3] */ 4954 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, 4955 FN_SEL_I2C03_4, 0, 0, 0, 4956 /* SEL_I2C04 [3] */ 4957 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, 4958 FN_SEL_I2C04_4, 0, 0, 0, 4959 /* SEL_I2C05 [2] */ 4960 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, 4961 /* RESERVED [1] */ 4962 0, 0, } 4963 }, 4964 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 4965 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 4966 2, 2, 2, 1, 1, 2) { 4967 /* SEL_IEB [2] */ 4968 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 4969 /* SEL_IIC0 [2] */ 4970 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, 4971 /* SEL_LBS [1] */ 4972 FN_SEL_LBS_0, FN_SEL_LBS_1, 4973 /* SEL_MSI1 [1] */ 4974 FN_SEL_MSI1_0, FN_SEL_MSI1_1, 4975 /* SEL_MSI2 [1] */ 4976 FN_SEL_MSI2_0, FN_SEL_MSI2_1, 4977 /* SEL_RAD [1] */ 4978 FN_SEL_RAD_0, FN_SEL_RAD_1, 4979 /* SEL_RCN [1] */ 4980 FN_SEL_RCN_0, FN_SEL_RCN_1, 4981 /* SEL_RSP [1] */ 4982 FN_SEL_RSP_0, FN_SEL_RSP_1, 4983 /* SEL_SCIFA0 [2] */ 4984 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, 4985 FN_SEL_SCIFA0_3, 4986 /* SEL_SCIFA1 [2] */ 4987 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, 4988 /* SEL_SCIFA2 [1] */ 4989 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 4990 /* SEL_SCIFA3 [1] */ 4991 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, 4992 /* SEL_SCIFA4 [2] */ 4993 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 4994 FN_SEL_SCIFA4_3, 4995 /* SEL_SCIFA5 [2] */ 4996 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 4997 FN_SEL_SCIFA5_3, 4998 /* RESERVED [1] */ 4999 0, 0, 5000 /* SEL_TMU [1] */ 5001 FN_SEL_TMU_0, FN_SEL_TMU_1, 5002 /* SEL_TSIF0 [2] */ 5003 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 5004 /* SEL_CAN0 [2] */ 5005 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 5006 /* SEL_CAN1 [2] */ 5007 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 5008 /* SEL_HSCIF0 [1] */ 5009 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, 5010 /* SEL_HSCIF1 [1] */ 5011 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 5012 /* RESERVED [2] */ 5013 0, 0, 0, 0, } 5014 }, 5015 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5016 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 5017 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { 5018 /* SEL_SCIF0 [2] */ 5019 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 5020 /* SEL_SCIF1 [2] */ 5021 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, 5022 /* SEL_SCIF2 [2] */ 5023 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, 5024 /* SEL_SCIF3 [1] */ 5025 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, 5026 /* SEL_SCIF4 [3] */ 5027 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 5028 FN_SEL_SCIF4_4, 0, 0, 0, 5029 /* SEL_SCIF5 [2] */ 5030 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 5031 /* SEL_SSI1 [1] */ 5032 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 5033 /* SEL_SSI2 [1] */ 5034 FN_SEL_SSI2_0, FN_SEL_SSI2_1, 5035 /* SEL_SSI4 [1] */ 5036 FN_SEL_SSI4_0, FN_SEL_SSI4_1, 5037 /* SEL_SSI5 [1] */ 5038 FN_SEL_SSI5_0, FN_SEL_SSI5_1, 5039 /* SEL_SSI6 [1] */ 5040 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 5041 /* SEL_SSI7 [1] */ 5042 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 5043 /* SEL_SSI8 [1] */ 5044 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 5045 /* SEL_SSI9 [1] */ 5046 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 5047 /* RESERVED [1] */ 5048 0, 0, 5049 /* RESERVED [1] */ 5050 0, 0, 5051 /* RESERVED [1] */ 5052 0, 0, 5053 /* RESERVED [1] */ 5054 0, 0, 5055 /* RESERVED [1] */ 5056 0, 0, 5057 /* RESERVED [1] */ 5058 0, 0, 5059 /* RESERVED [1] */ 5060 0, 0, 5061 /* RESERVED [1] */ 5062 0, 0, 5063 /* RESERVED [1] */ 5064 0, 0, 5065 /* RESERVED [1] */ 5066 0, 0, 5067 /* RESERVED [1] */ 5068 0, 0, 5069 /* RESERVED [1] */ 5070 0, 0, } 5071 }, 5072 { }, 5073 }; 5074 5075 static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5076 { 5077 *pocctrl = 0xe606006c; 5078 5079 switch (pin & 0x1f) { 5080 case 6: return 23; 5081 case 7: return 16; 5082 case 14: return 15; 5083 case 15: return 8; 5084 case 0 ... 5: 5085 case 8 ... 13: 5086 return 22 - (pin & 0x1f); 5087 case 16 ... 23: 5088 return 47 - (pin & 0x1f); 5089 } 5090 5091 return -EINVAL; 5092 } 5093 5094 static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { 5095 .pin_to_pocctrl = r8a7794_pin_to_pocctrl, 5096 }; 5097 5098 #ifdef CONFIG_PINCTRL_PFC_R8A7745 5099 const struct sh_pfc_soc_info r8a7745_pinmux_info = { 5100 .name = "r8a77450_pfc", 5101 .ops = &r8a7794_pinmux_ops, 5102 .unlock_reg = 0xe6060000, /* PMMR */ 5103 5104 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5105 5106 .pins = pinmux_pins, 5107 .nr_pins = ARRAY_SIZE(pinmux_pins), 5108 .groups = pinmux_groups, 5109 .nr_groups = ARRAY_SIZE(pinmux_groups), 5110 .functions = pinmux_functions, 5111 .nr_functions = ARRAY_SIZE(pinmux_functions), 5112 5113 .cfg_regs = pinmux_config_regs, 5114 5115 .pinmux_data = pinmux_data, 5116 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5117 }; 5118 #endif 5119 5120 #ifdef CONFIG_PINCTRL_PFC_R8A7794 5121 const struct sh_pfc_soc_info r8a7794_pinmux_info = { 5122 .name = "r8a77940_pfc", 5123 .ops = &r8a7794_pinmux_ops, 5124 .unlock_reg = 0xe6060000, /* PMMR */ 5125 5126 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5127 5128 .pins = pinmux_pins, 5129 .nr_pins = ARRAY_SIZE(pinmux_pins), 5130 .groups = pinmux_groups, 5131 .nr_groups = ARRAY_SIZE(pinmux_groups), 5132 .functions = pinmux_functions, 5133 .nr_functions = ARRAY_SIZE(pinmux_functions), 5134 5135 .cfg_regs = pinmux_config_regs, 5136 5137 .pinmux_data = pinmux_data, 5138 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5139 }; 5140 #endif 5141