1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * r8a7791/r8a7743 processor support - PFC hardware block.
4  *
5  * Copyright (C) 2013 Renesas Electronics Corporation
6  * Copyright (C) 2014-2017 Cogent Embedded, Inc.
7  */
8 
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <dm/pinctrl.h>
13 #include <linux/kernel.h>
14 
15 #include "sh_pfc.h"
16 
17 /*
18  * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
19  * which case they support both 3.3V and 1.8V signalling.
20  */
21 #define CPU_ALL_PORT(fn, sfx)						\
22 	PORT_GP_32(0, fn, sfx),						\
23 	PORT_GP_26(1, fn, sfx),						\
24 	PORT_GP_32(2, fn, sfx),						\
25 	PORT_GP_32(3, fn, sfx),						\
26 	PORT_GP_32(4, fn, sfx),						\
27 	PORT_GP_32(5, fn, sfx),						\
28 	PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
29 	PORT_GP_1(6, 24, fn, sfx),					\
30 	PORT_GP_1(6, 25, fn, sfx),					\
31 	PORT_GP_1(6, 26, fn, sfx),					\
32 	PORT_GP_1(6, 27, fn, sfx),					\
33 	PORT_GP_1(6, 28, fn, sfx),					\
34 	PORT_GP_1(6, 29, fn, sfx),					\
35 	PORT_GP_1(6, 30, fn, sfx),					\
36 	PORT_GP_1(6, 31, fn, sfx),					\
37 	PORT_GP_26(7, fn, sfx)
38 
39 enum {
40 	PINMUX_RESERVED = 0,
41 
42 	PINMUX_DATA_BEGIN,
43 	GP_ALL(DATA),
44 	PINMUX_DATA_END,
45 
46 	PINMUX_FUNCTION_BEGIN,
47 	GP_ALL(FN),
48 
49 	/* GPSR0 */
50 	FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
51 	FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
52 	FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
53 	FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
54 	FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
55 	FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
56 
57 	/* GPSR1 */
58 	FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
59 	FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
60 	FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
61 	FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
62 	FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
63 	FN_IP3_21_20,
64 
65 	/* GPSR2 */
66 	FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
67 	FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
68 	FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
69 	FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
70 	FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
71 	FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
72 	FN_IP6_5_3, FN_IP6_7_6,
73 
74 	/* GPSR3 */
75 	FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
76 	FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
77 	FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
78 	FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
79 	FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
80 	FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
81 	FN_IP9_18_17,
82 
83 	/* GPSR4 */
84 	FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
85 	FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
86 	FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
87 	FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
88 	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
89 	FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
90 	FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
91 	FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
92 
93 	/* GPSR5 */
94 	FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
95 	FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
96 	FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
97 	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
98 	FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
99 	FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
100 	FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
101 
102 	/* GPSR6 */
103 	FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
104 	FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
105 	FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
106 	FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
107 	FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
108 	FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
109 	FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
110 	FN_USB1_OVC, FN_DU0_DOTCLKIN,
111 
112 	/* GPSR7 */
113 	FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
114 	FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
115 	FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
116 	FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
117 	FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
118 	FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
119 
120 	/* IPSR0 */
121 	FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
122 	FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
123 	FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
124 	FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
125 	FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
126 	FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
127 
128 	/* IPSR1 */
129 	FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
130 	FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
131 	FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
132 	FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
133 	FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
134 	FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
135 	FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
136 	FN_A15, FN_BPFCLK_C,
137 	FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
138 	FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
139 	FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
140 
141 	/* IPSR2 */
142 	FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
143 	FN_A20, FN_SPCLK,
144 	FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
145 	FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
146 	FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
147 	FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
148 	FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
149 	FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
150 	FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
151 	FN_EX_CS1_N, FN_MSIOF2_SCK,
152 	FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
153 	FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
154 
155 	/* IPSR3 */
156 	FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
157 	FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
158 	FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
159 	FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
160 	FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
161 	FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
162 	FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
163 	FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
164 	FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
165 	FN_DREQ0, FN_PWM3, FN_TPU_TO3,
166 	FN_DACK0, FN_DRACK0, FN_REMOCON,
167 	FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
168 	FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
169 	FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
170 	FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
171 
172 	/* IPSR4 */
173 	FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
174 	FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
175 	FN_GLO_I0_D,
176 	FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
177 	FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
178 	FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
179 	FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
180 	FN_GLO_Q1_D, FN_HCTS1_N_E,
181 	FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
182 	FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
183 	FN_SSI_SCK4, FN_GLO_SS_D,
184 	FN_SSI_WS4, FN_GLO_RFON_D,
185 	FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
186 	FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
187 	FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
188 
189 	/* IPSR5 */
190 	FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
191 	FN_MSIOF2_TXD_D, FN_VI1_R3_B,
192 	FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
193 	FN_MSIOF2_SS1_D, FN_VI1_R4_B,
194 	FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
195 	FN_MSIOF2_RXD_D, FN_VI1_R5_B,
196 	FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
197 	FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
198 	FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
199 	FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
200 	FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
201 	FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
202 	FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
203 	FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
204 	FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
205 
206 	/* IPSR6 */
207 	FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
208 	FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
209 	FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
210 	FN_SCIFA2_RXD, FN_FMIN_E,
211 	FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
212 	FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
213 	FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
214 	FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
215 	FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
216 	FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
217 	FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
218 	FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
219 	FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
220 	FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
221 
222 	/* IPSR7 */
223 	FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
224 	FN_SCIF_CLK_B, FN_GPS_MAG_D,
225 	FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
226 	FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
227 	FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
228 	FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
229 	FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
230 	FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
231 	FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
232 	FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
233 	FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
234 	FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
235 	FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
236 	FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
237 	FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
238 	FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
239 	FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
240 	FN_SCIFA1_SCK, FN_SSI_SCK78_B,
241 
242 	/* IPSR8 */
243 	FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
244 	FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
245 	FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
246 	FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
247 	FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
248 	FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
249 	FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
250 	FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
251 	FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
252 	FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
253 	FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
254 	FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
255 	FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
256 	FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
257 	FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
258 	FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
259 	FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
260 
261 	/* IPSR9 */
262 	FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
263 	FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
264 	FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
265 	FN_DU1_DOTCLKOUT0, FN_QCLK,
266 	FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
267 	FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
268 	FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
269 	FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
270 	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
271 	FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
272 	FN_DU1_DISP, FN_QPOLA,
273 	FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
274 	FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
275 	FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
276 	FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
277 	FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
278 	FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
279 	FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
280 	FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
281 
282 	/* IPSR10 */
283 	FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
284 	FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
285 	FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
286 	FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
287 	FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
288 	FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
289 	FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
290 	FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
291 	FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
292 	FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
293 	FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
294 	FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
295 	FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
296 	FN_TS_SDATA0_C, FN_ATACS11_N,
297 	FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
298 	FN_TS_SCK0_C, FN_ATAG1_N,
299 	FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
300 	FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
301 	FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
302 
303 	/* IPSR11 */
304 	FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
305 	FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
306 	FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
307 	FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
308 	FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
309 	FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
310 	FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
311 	FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
312 	FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
313 	FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
314 	FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
315 	FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
316 	FN_VI1_DATA7, FN_AVB_MDC,
317 	FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
318 	FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
319 
320 	/* IPSR12 */
321 	FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
322 	FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
323 	FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
324 	FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
325 	FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
326 	FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
327 	FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
328 	FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
329 	FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
330 	FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
331 	FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
332 	FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
333 	FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
334 	FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
335 	FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
336 	FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
337 	FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
338 
339 	/* IPSR13 */
340 	FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
341 	FN_ADICLK_B, FN_MSIOF0_SS1_C,
342 	FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
343 	FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
344 	FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
345 	FN_ADICHS2_B, FN_MSIOF0_TXD_C,
346 	FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
347 	FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
348 	FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
349 	FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
350 	FN_SCIFA5_TXD_B, FN_TX3_C,
351 	FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
352 	FN_SCIFA5_RXD_B, FN_RX3_C,
353 	FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
354 	FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
355 	FN_SD1_DATA3, FN_IERX_B,
356 	FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
357 
358 	/* IPSR14 */
359 	FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
360 	FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
361 	FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
362 	FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
363 	FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
364 	FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
365 	FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
366 	FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
367 	FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
368 	FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
369 	FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
370 	FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
371 	FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
372 	FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
373 
374 	/* IPSR15 */
375 	FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
376 	FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
377 	FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
378 	FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
379 	FN_PWM5_B, FN_SCIFA3_TXD_C,
380 	FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
381 	FN_VI1_G6_B, FN_SCIFA3_RXD_C,
382 	FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
383 	FN_VI1_G7_B, FN_SCIFA3_SCK_C,
384 	FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
385 	FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
386 	FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
387 	FN_TCLK2, FN_VI1_DATA3_C,
388 	FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
389 	FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
390 
391 	/* IPSR16 */
392 	FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
393 	FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
394 	FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
395 	FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
396 	FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
397 
398 	/* MOD_SEL */
399 	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
400 	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
401 	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
402 	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
403 	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
404 	FN_SEL_SSI9_0, FN_SEL_SSI9_1,
405 	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
406 	FN_SEL_QSP_0, FN_SEL_QSP_1,
407 	FN_SEL_SSI7_0, FN_SEL_SSI7_1,
408 	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
409 	FN_SEL_HSCIF1_4,
410 	FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
411 	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
412 	FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
413 	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
414 	FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
415 
416 	/* MOD_SEL2 */
417 	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
418 	FN_SEL_SCIF0_4,
419 	FN_SEL_SCIF_0, FN_SEL_SCIF_1,
420 	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
421 	FN_SEL_CAN0_4, FN_SEL_CAN0_5,
422 	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
423 	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
424 	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
425 	FN_SEL_ADG_0, FN_SEL_ADG_1,
426 	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
427 	FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
428 	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
429 	FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
430 	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
431 	FN_SEL_SIM_0, FN_SEL_SIM_1,
432 	FN_SEL_SSI8_0, FN_SEL_SSI8_1,
433 
434 	/* MOD_SEL3 */
435 	FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
436 	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
437 	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
438 	FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
439 	FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
440 	FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
441 	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
442 	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
443 	FN_SEL_MMC_0, FN_SEL_MMC_1,
444 	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
445 	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
446 	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
447 	FN_SEL_I2C1_4,
448 	FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
449 
450 	/* MOD_SEL4 */
451 	FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
452 	FN_SEL_SOF1_4,
453 	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
454 	FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
455 	FN_SEL_RAD_0, FN_SEL_RAD_1,
456 	FN_SEL_RCN_0, FN_SEL_RCN_1,
457 	FN_SEL_RSP_0, FN_SEL_RSP_1,
458 	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
459 	FN_SEL_SCIF2_4,
460 	FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
461 	FN_SEL_SOF2_4,
462 	FN_SEL_SSI1_0, FN_SEL_SSI1_1,
463 	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
464 	FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
465 	PINMUX_FUNCTION_END,
466 
467 	PINMUX_MARK_BEGIN,
468 
469 	EX_CS0_N_MARK, RD_N_MARK,
470 
471 	AUDIO_CLKA_MARK,
472 
473 	VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
474 	VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
475 	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
476 
477 	SD1_CLK_MARK,
478 
479 	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
480 	DU0_DOTCLKIN_MARK,
481 
482 	/* IPSR0 */
483 	D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
484 	D6_MARK, D7_MARK, D8_MARK,
485 	D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
486 	A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
487 	PWM2_B_MARK,
488 	A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
489 	A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
490 	A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
491 
492 	/* IPSR1 */
493 	A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
494 	A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
495 	A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
496 	A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
497 	A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
498 	A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
499 	A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
500 	A15_MARK, BPFCLK_C_MARK,
501 	A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
502 	A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
503 	A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
504 
505 	/* IPSR2 */
506 	A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
507 	SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
508 	A20_MARK, SPCLK_MARK,
509 	A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
510 	A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
511 	A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
512 	A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
513 	A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
514 	RX1_MARK, SCIFA1_RXD_MARK,
515 	CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
516 	CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
517 	EX_CS1_N_MARK, MSIOF2_SCK_MARK,
518 	EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
519 	EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
520 	ATAG0_N_MARK, EX_WAIT1_MARK,
521 
522 	/* IPSR3 */
523 	EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
524 	EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
525 	SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
526 	BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
527 	SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
528 	RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
529 	SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
530 	WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
531 	WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
532 	EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
533 	DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
534 	DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
535 	SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
536 	SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
537 	SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
538 	SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
539 	SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
540 	SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
541 
542 	/* IPSR4 */
543 	SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
544 	SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
545 	MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
546 	SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
547 	MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
548 	SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
549 	SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
550 	HSCK1_E_MARK,
551 	SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
552 	GLO_Q1_D_MARK, HCTS1_N_E_MARK,
553 	SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
554 	SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
555 	SSI_SCK4_MARK, GLO_SS_D_MARK,
556 	SSI_WS4_MARK, GLO_RFON_D_MARK,
557 	SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
558 	SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
559 	MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
560 
561 	/* IPSR5 */
562 	SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
563 	MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
564 	SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
565 	MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
566 	SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
567 	MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
568 	SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
569 	SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
570 	SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
571 	SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
572 	SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
573 	SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
574 	SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
575 	SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
576 	SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
577 
578 	/* IPSR6 */
579 	AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
580 	SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
581 	AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
582 	SCIFA2_RXD_MARK, FMIN_E_MARK,
583 	AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
584 	IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
585 	IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
586 	IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
587 	IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
588 	IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
589 	MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
590 	IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
591 	IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
592 	I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
593 	IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
594 	GPS_CLK_C_MARK, GPS_CLK_D_MARK,
595 	IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
596 	GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
597 
598 	/* IPSR7 */
599 	IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
600 	SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
601 	DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
602 	SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
603 	DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
604 	SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
605 	DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
606 	DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
607 	DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
608 	DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
609 	DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
610 	DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
611 	DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
612 	SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
613 	DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
614 	SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
615 	DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
616 	SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
617 
618 	/* IPSR8 */
619 	DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
620 	DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
621 	SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
622 	DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
623 	SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
624 	DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
625 	SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
626 	DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
627 	SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
628 	DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
629 	SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
630 	DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
631 	SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
632 	DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
633 	SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
634 	DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
635 	DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
636 	DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
637 
638 	/* IPSR9 */
639 	DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
640 	DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
641 	SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
642 	DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
643 	DU1_DOTCLKOUT0_MARK, QCLK_MARK,
644 	DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
645 	TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
646 	DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
647 	DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
648 	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
649 	CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
650 	DU1_DISP_MARK, QPOLA_MARK,
651 	DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
652 	VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
653 	VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
654 	VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
655 	VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
656 	VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
657 	VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
658 	HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
659 
660 	/* IPSR10 */
661 	VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
662 	HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
663 	VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
664 	HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
665 	VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
666 	HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
667 	VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
668 	HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
669 	VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
670 	CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
671 	VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
672 	VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
673 	VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
674 	TS_SDATA0_C_MARK, ATACS11_N_MARK,
675 	VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
676 	TS_SCK0_C_MARK, ATAG1_N_MARK,
677 	VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
678 	VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
679 	VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
680 	I2C1_SCL_D_MARK,
681 
682 	/* IPSR11 */
683 	VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
684 	I2C1_SDA_D_MARK,
685 	VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
686 	VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
687 	I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
688 	VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
689 	TX4_B_MARK, SCIFA4_TXD_B_MARK,
690 	VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
691 	RX4_B_MARK, SCIFA4_RXD_B_MARK,
692 	VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
693 	VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
694 	VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
695 	VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
696 	VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
697 	VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
698 	VI1_DATA7_MARK, AVB_MDC_MARK,
699 	ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
700 	ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
701 
702 	/* IPSR12 */
703 	ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
704 	ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
705 	ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
706 	I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
707 	ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
708 	I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
709 	ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
710 	CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
711 	ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
712 	CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
713 	ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
714 	ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
715 	ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
716 	ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
717 	STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
718 	ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
719 	STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
720 	ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
721 
722 	/* IPSR13 */
723 	STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
724 	ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
725 	STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
726 	STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
727 	STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
728 	ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
729 	SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
730 	SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
731 	SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
732 	SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
733 	SCIFA5_TXD_B_MARK, TX3_C_MARK,
734 	SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
735 	SCIFA5_RXD_B_MARK, RX3_C_MARK,
736 	SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
737 	SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
738 	SD1_DATA3_MARK, IERX_B_MARK,
739 	SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
740 
741 	/* IPSR14 */
742 	SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
743 	SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
744 	SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
745 	SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
746 	SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
747 	SCIFA5_TXD_C_MARK,
748 	SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
749 	SCIFA5_RXD_C_MARK,
750 	MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
751 	VI1_CLK_C_MARK, VI1_G0_B_MARK,
752 	MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
753 	VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
754 	MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
755 	MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
756 	MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
757 	VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
758 	MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
759 	VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
760 
761 	/* IPSR15 */
762 	SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
763 	SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
764 	SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
765 	GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
766 	PWM5_B_MARK, SCIFA3_TXD_C_MARK,
767 	GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
768 	VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
769 	GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
770 	VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
771 	HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
772 	TCLK1_MARK, VI1_DATA1_C_MARK,
773 	HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
774 	HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
775 	TCLK2_MARK, VI1_DATA3_C_MARK,
776 	HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
777 	CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
778 	HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
779 	CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
780 
781 	/* IPSR16 */
782 	HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
783 	GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
784 	HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
785 	GLO_SS_C_MARK, VI1_DATA7_C_MARK,
786 	HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
787 	HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
788 	HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
789 	PINMUX_MARK_END,
790 };
791 
792 static const u16 pinmux_data[] = {
793 	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
794 
795 	PINMUX_SINGLE(EX_CS0_N),
796 	PINMUX_SINGLE(RD_N),
797 	PINMUX_SINGLE(AUDIO_CLKA),
798 	PINMUX_SINGLE(VI0_CLK),
799 	PINMUX_SINGLE(VI0_DATA0_VI0_B0),
800 	PINMUX_SINGLE(VI0_DATA1_VI0_B1),
801 	PINMUX_SINGLE(VI0_DATA2_VI0_B2),
802 	PINMUX_SINGLE(VI0_DATA4_VI0_B4),
803 	PINMUX_SINGLE(VI0_DATA5_VI0_B5),
804 	PINMUX_SINGLE(VI0_DATA6_VI0_B6),
805 	PINMUX_SINGLE(VI0_DATA7_VI0_B7),
806 	PINMUX_SINGLE(USB0_PWEN),
807 	PINMUX_SINGLE(USB0_OVC),
808 	PINMUX_SINGLE(USB1_PWEN),
809 	PINMUX_SINGLE(USB1_OVC),
810 	PINMUX_SINGLE(DU0_DOTCLKIN),
811 	PINMUX_SINGLE(SD1_CLK),
812 
813 	/* IPSR0 */
814 	PINMUX_IPSR_GPSR(IP0_0, D0),
815 	PINMUX_IPSR_GPSR(IP0_1, D1),
816 	PINMUX_IPSR_GPSR(IP0_2, D2),
817 	PINMUX_IPSR_GPSR(IP0_3, D3),
818 	PINMUX_IPSR_GPSR(IP0_4, D4),
819 	PINMUX_IPSR_GPSR(IP0_5, D5),
820 	PINMUX_IPSR_GPSR(IP0_6, D6),
821 	PINMUX_IPSR_GPSR(IP0_7, D7),
822 	PINMUX_IPSR_GPSR(IP0_8, D8),
823 	PINMUX_IPSR_GPSR(IP0_9, D9),
824 	PINMUX_IPSR_GPSR(IP0_10, D10),
825 	PINMUX_IPSR_GPSR(IP0_11, D11),
826 	PINMUX_IPSR_GPSR(IP0_12, D12),
827 	PINMUX_IPSR_GPSR(IP0_13, D13),
828 	PINMUX_IPSR_GPSR(IP0_14, D14),
829 	PINMUX_IPSR_GPSR(IP0_15, D15),
830 	PINMUX_IPSR_GPSR(IP0_18_16, A0),
831 	PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
832 	PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
833 	PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
834 	PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
835 	PINMUX_IPSR_GPSR(IP0_20_19, A1),
836 	PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
837 	PINMUX_IPSR_GPSR(IP0_22_21, A2),
838 	PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
839 	PINMUX_IPSR_GPSR(IP0_24_23, A3),
840 	PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
841 	PINMUX_IPSR_GPSR(IP0_26_25, A4),
842 	PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
843 	PINMUX_IPSR_GPSR(IP0_28_27, A5),
844 	PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
845 	PINMUX_IPSR_GPSR(IP0_30_29, A6),
846 	PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
847 
848 	/* IPSR1 */
849 	PINMUX_IPSR_GPSR(IP1_1_0, A7),
850 	PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
851 	PINMUX_IPSR_GPSR(IP1_3_2, A8),
852 	PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
853 	PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
854 	PINMUX_IPSR_GPSR(IP1_5_4, A9),
855 	PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
856 	PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
857 	PINMUX_IPSR_GPSR(IP1_7_6, A10),
858 	PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
859 	PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
860 	PINMUX_IPSR_GPSR(IP1_10_8, A11),
861 	PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
862 	PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
863 	PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
864 	PINMUX_IPSR_GPSR(IP1_13_11, A12),
865 	PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
866 	PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
867 	PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
868 	PINMUX_IPSR_GPSR(IP1_16_14, A13),
869 	PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
870 	PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
871 	PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
872 	PINMUX_IPSR_GPSR(IP1_19_17, A14),
873 	PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
874 	PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
875 	PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
876 	PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
877 	PINMUX_IPSR_GPSR(IP1_22_20, A15),
878 	PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
879 	PINMUX_IPSR_GPSR(IP1_25_23, A16),
880 	PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
881 	PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
882 	PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
883 	PINMUX_IPSR_GPSR(IP1_28_26, A17),
884 	PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
885 	PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
886 	PINMUX_IPSR_GPSR(IP1_31_29, A18),
887 	PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
888 	PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
889 	PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
890 
891 	/* IPSR2 */
892 	PINMUX_IPSR_GPSR(IP2_2_0, A19),
893 	PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
894 	PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
895 	PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
896 	PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
897 	PINMUX_IPSR_GPSR(IP2_2_0, A20),
898 	PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
899 	PINMUX_IPSR_GPSR(IP2_6_5, A21),
900 	PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
901 	PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
902 	PINMUX_IPSR_GPSR(IP2_9_7, A22),
903 	PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
904 	PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
905 	PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
906 	PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
907 	PINMUX_IPSR_GPSR(IP2_12_10, A23),
908 	PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
909 	PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
910 	PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
911 	PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
912 	PINMUX_IPSR_GPSR(IP2_15_13, A24),
913 	PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
914 	PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
915 	PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
916 	PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
917 	PINMUX_IPSR_GPSR(IP2_18_16, A25),
918 	PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
919 	PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
920 	PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
921 	PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
922 	PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
923 	PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
924 	PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
925 	PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
926 	PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
927 	PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
928 	PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
929 	PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
930 	PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
931 	PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
932 	PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
933 	PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
934 	PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
935 	PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
936 	PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
937 	PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
938 	PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
939 
940 	/* IPSR3 */
941 	PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
942 	PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
943 	PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
944 	PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
945 	PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
946 	PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
947 	PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
948 	PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
949 	PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
950 	PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
951 	PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
952 	PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
953 	PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
954 	PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
955 	PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
956 	PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
957 	PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
958 	PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
959 	PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
960 	PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
961 	PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
962 	PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
963 	PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
964 	PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
965 	PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
966 	PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
967 	PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
968 	PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
969 	PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
970 	PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
971 	PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
972 	PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
973 	PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
974 	PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
975 	PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
976 	PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
977 	PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
978 	PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
979 	PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
980 	PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
981 	PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
982 	PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
983 	PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
984 	PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
985 	PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
986 	PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
987 	PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
988 	PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
989 	PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
990 	PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
991 	PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
992 	PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
993 	PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
994 	PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
995 	PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
996 	PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
997 
998 	/* IPSR4 */
999 	PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
1000 	PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
1001 	PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
1002 	PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
1003 	PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
1004 	PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
1005 	PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
1006 	PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1007 	PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1008 	PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1009 	PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
1010 	PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
1011 	PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1012 	PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1013 	PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1014 	PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
1015 	PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
1016 	PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1017 	PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1018 	PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
1019 	PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1020 	PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1021 	PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
1022 	PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1023 	PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
1024 	PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1025 	PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1026 	PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1027 	PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
1028 	PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1029 	PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1030 	PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1031 	PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
1032 	PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1033 	PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1034 	PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1035 	PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1036 	PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1037 	PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1038 	PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1039 	PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1040 	PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1041 	PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1042 	PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1043 	PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1044 	PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1045 	PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1046 	PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1047 
1048 	/* IPSR5 */
1049 	PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1050 	PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1051 	PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1052 	PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1053 	PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1054 	PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1055 	PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1056 	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1057 	PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1058 	PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1059 	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1060 	PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1061 	PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1062 	PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1063 	PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1064 	PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1065 	PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1066 	PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1067 	PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1068 	PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1069 	PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1070 	PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1071 	PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1072 	PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1073 	PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1074 	PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1075 	PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1076 	PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1077 	PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1078 	PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1079 	PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1080 	PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1081 	PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1082 	PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1083 	PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1084 	PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1085 	PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1086 	PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1087 	PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1088 	PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1089 	PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1090 	PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1091 	PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1092 	PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1093 	PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1094 	PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1095 	PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1096 	PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1097 	PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1098 
1099 	/* IPSR6 */
1100 	PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1101 	PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1102 	PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1103 	PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1104 	PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
1105 	PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1106 	PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1107 	PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1108 	PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1109 	PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1110 	PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1111 	PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1112 	PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1113 	PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1114 	PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
1115 	PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1116 	PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1117 	PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1118 	PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
1119 	PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1120 	PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1121 	PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
1122 	PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1123 	PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1124 	PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
1125 	PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1126 	PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
1127 	PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1128 	PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
1129 	PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1130 	PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1131 	PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
1132 	PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1133 	PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
1134 	PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1135 	PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1136 	PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
1137 	PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1138 	PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1139 	PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1140 	PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1141 	PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
1142 	PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1143 	PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1144 	PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1145 	PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1146 	PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1147 	PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1148 	PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1149 	PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1150 	PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1151 	PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1152 	PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1153 
1154 	/* IPSR7 */
1155 	PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1156 	PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1157 	PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1158 	PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1159 	PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1160 	PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1161 	PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1162 	PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1163 	PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1164 	PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1165 	PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1166 	PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1167 	PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1168 	PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1169 	PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1170 	PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1171 	PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1172 	PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1173 	PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1174 	PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1175 	PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1176 	PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1177 	PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1178 	PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1179 	PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1180 	PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1181 	PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1182 	PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1183 	PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1184 	PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1185 	PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1186 	PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1187 	PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1188 	PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1189 	PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1190 	PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1191 	PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1192 	PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1193 	PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1194 	PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1195 	PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1196 	PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1197 	PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1198 	PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1199 	PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1200 	PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1201 	PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1202 	PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1203 	PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1204 	PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1205 	PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1206 	PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1207 	PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1208 	PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1209 
1210 	/* IPSR8 */
1211 	PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1212 	PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1213 	PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1214 	PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1215 	PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1216 	PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1217 	PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1218 	PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1219 	PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1220 	PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1221 	PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1222 	PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1223 	PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1224 	PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1225 	PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1226 	PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1227 	PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1228 	PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1229 	PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1230 	PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1231 	PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1232 	PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1233 	PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1234 	PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1235 	PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1236 	PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1237 	PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1238 	PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1239 	PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1240 	PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1241 	PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1242 	PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1243 	PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1244 	PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1245 	PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1246 	PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1247 	PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1248 	PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1249 	PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1250 	PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1251 	PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1252 	PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1253 	PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1254 	PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1255 	PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1256 	PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1257 	PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1258 	PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1259 	PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1260 	PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1261 	PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1262 	PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1263 	PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1264 	PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1265 	PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1266 	PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1267 
1268 	/* IPSR9 */
1269 	PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1270 	PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1271 	PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
1272 	PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1273 	PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1274 	PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1275 	PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1276 	PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
1277 	PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1278 	PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1279 	PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1280 	PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1281 	PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1282 	PINMUX_IPSR_GPSR(IP9_7, QCLK),
1283 	PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1284 	PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1285 	PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1286 	PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1287 	PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
1288 	PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1289 	PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1290 	PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1291 	PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1292 	PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1293 	PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1294 	PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1295 	PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1296 	PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1297 	PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
1298 	PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1299 	PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1300 	PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1301 	PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1302 	PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1303 	PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1304 	PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1305 	PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1306 	PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1307 	PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1308 	PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1309 	PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1310 	PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1311 	PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1312 	PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1313 	PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1314 	PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1315 	PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1316 	PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1317 	PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1318 	PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1319 	PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1320 	PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1321 	PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1322 	PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1323 	PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
1324 	PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1325 	PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
1326 	PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1327 	PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1328 	PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1329 
1330 	/* IPSR10 */
1331 	PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1332 	PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
1333 	PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1334 	PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
1335 	PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1336 	PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1337 	PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1338 	PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1339 	PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1340 	PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1341 	PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
1342 	PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1343 	PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1344 	PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1345 	PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1346 	PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1347 	PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1348 	PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
1349 	PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1350 	PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1351 	PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1352 	PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1353 	PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1354 	PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1355 	PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1356 	PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1357 	PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1358 	PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1359 	PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1360 	PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1361 	PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1362 	PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1363 	PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1364 	PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1365 	PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1366 	PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1367 	PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1368 	PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1369 	PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1370 	PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1371 	PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1372 	PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1373 	PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1374 	PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1375 	PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1376 	PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1377 	PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1378 	PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1379 	PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1380 	PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1381 	PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1382 	PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1383 	PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1384 	PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1385 	PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1386 	PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1387 	PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1388 	PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1389 	PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1390 	PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1391 	PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1392 	PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1393 	PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
1394 
1395 	/* IPSR11 */
1396 	PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1397 	PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1398 	PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1399 	PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1400 	PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
1401 	PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1402 	PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1403 	PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1404 	PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1405 	PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
1406 	PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1407 	PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1408 	PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1409 	PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1410 	PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
1411 	PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1412 	PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1413 	PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1414 	PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1415 	PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1416 	PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1417 	PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1418 	PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1419 	PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1420 	PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1421 	PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1422 	PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1423 	PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1424 	PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1425 	PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1426 	PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1427 	PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1428 	PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1429 	PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1430 	PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1431 	PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1432 	PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1433 	PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1434 	PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1435 	PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1436 	PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1437 	PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1438 	PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1439 	PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1440 	PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1441 	PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1442 	PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1443 	PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1444 	PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1445 	PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1446 	PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1447 	PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1448 	PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1449 	PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
1450 	PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1451 	PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1452 	PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
1453 
1454 	/* IPSR12 */
1455 	PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1456 	PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1457 	PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
1458 	PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
1459 	PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1460 	PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1461 	PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
1462 	PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
1463 	PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1464 	PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1465 	PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1466 	PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
1467 	PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1468 	PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1469 	PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1470 	PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1471 	PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
1472 	PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1473 	PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1474 	PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1475 	PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1476 	PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1477 	PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1478 	PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1479 	PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1480 	PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1481 	PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1482 	PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1483 	PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1484 	PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1485 	PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1486 	PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1487 	PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1488 	PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1489 	PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1490 	PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1491 	PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1492 	PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1493 	PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1494 	PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1495 	PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1496 	PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1497 	PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1498 	PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1499 	PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1500 	PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1501 	PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1502 	PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1503 	PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1504 	PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1505 	PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1506 
1507 	/* IPSR13 */
1508 	PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1509 	PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1510 	PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1511 	PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1512 	PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1513 	PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1514 	PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1515 	PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1516 	PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1517 	PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1518 	PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1519 	PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1520 	PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1521 	PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1522 	PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1523 	PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1524 	PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1525 	PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1526 	PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1527 	PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1528 	PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1529 	PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1530 	PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1531 	PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1532 	PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1533 	PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1534 	PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1535 	PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1536 	PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1537 	PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1538 	PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1539 	PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1540 	PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1541 	PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1542 	PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1543 	PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1544 	PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1545 	PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1546 	PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1547 	PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1548 	PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1549 	PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1550 	PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1551 	PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1552 	PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1553 	PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1554 	PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1555 	PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1556 	PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1557 	PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1558 	PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1559 	PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1560 	PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1561 	PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1562 	PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1563 	PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
1564 
1565 	/* IPSR14 */
1566 	PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1567 	PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1568 	PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
1569 	PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1570 	PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1571 	PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1572 	PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1573 	PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1574 	PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1575 	PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1576 	PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1577 	PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1578 	PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1579 	PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1580 	PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1581 	PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1582 	PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1583 	PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
1584 	PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1585 	PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1586 	PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1587 	PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1588 	PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
1589 	PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1590 	PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1591 	PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1592 	PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1593 	PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1594 	PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1595 	PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1596 	PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1597 	PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1598 	PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1599 	PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1600 	PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1601 	PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1602 	PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1603 	PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1604 	PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1605 	PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1606 	PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1607 	PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1608 	PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1609 	PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1610 	PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1611 	PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1612 	PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1613 	PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1614 	PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
1615 	PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1616 	PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1617 	PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1618 	PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1619 	PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1620 	PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1621 	PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
1622 	PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1623 
1624 	/* IPSR15 */
1625 	PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1626 	PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1627 	PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1628 	PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1629 	PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1630 	PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1631 	PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1632 	PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1633 	PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1634 	PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1635 	PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1636 	PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1637 	PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1638 	PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1639 	PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1640 	PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1641 	PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1642 	PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1643 	PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1644 	PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1645 	PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1646 	PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1647 	PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1648 	PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1649 	PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1650 	PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1651 	PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1652 	PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1653 	PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1654 	PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1655 	PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1656 	PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1657 	PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1658 	PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1659 	PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1660 	PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1661 	PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1662 	PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1663 	PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1664 	PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1665 	PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1666 	PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1667 	PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1668 	PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1669 	PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1670 	PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1671 	PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1672 	PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1673 	PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1674 	PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1675 	PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1676 
1677 	/* IPSR16 */
1678 	PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1679 	PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1680 	PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1681 	PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1682 	PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1683 	PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1684 	PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1685 	PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1686 	PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1687 	PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1688 	PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1689 	PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1690 	PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1691 	PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1692 	PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1693 	PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1694 	PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1695 	PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1696 	PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1697 	PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1698 	PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1699 	PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1700 };
1701 
1702 static const struct sh_pfc_pin pinmux_pins[] = {
1703 	PINMUX_GPIO_GP_ALL(),
1704 };
1705 
1706 /* - ADI -------------------------------------------------------------------- */
1707 static const unsigned int adi_common_pins[] = {
1708 	/* ADIDATA, ADICS/SAMP, ADICLK */
1709 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1710 };
1711 static const unsigned int adi_common_mux[] = {
1712 	/* ADIDATA, ADICS/SAMP, ADICLK */
1713 	ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
1714 };
1715 static const unsigned int adi_chsel0_pins[] = {
1716 	/* ADICHS 0 */
1717 	RCAR_GP_PIN(6, 27),
1718 };
1719 static const unsigned int adi_chsel0_mux[] = {
1720 	/* ADICHS 0 */
1721 	ADICHS0_MARK,
1722 };
1723 static const unsigned int adi_chsel1_pins[] = {
1724 	/* ADICHS 1 */
1725 	RCAR_GP_PIN(6, 28),
1726 };
1727 static const unsigned int adi_chsel1_mux[] = {
1728 	/* ADICHS 1 */
1729 	ADICHS1_MARK,
1730 };
1731 static const unsigned int adi_chsel2_pins[] = {
1732 	/* ADICHS 2 */
1733 	RCAR_GP_PIN(6, 29),
1734 };
1735 static const unsigned int adi_chsel2_mux[] = {
1736 	/* ADICHS 2 */
1737 	ADICHS2_MARK,
1738 };
1739 static const unsigned int adi_common_b_pins[] = {
1740 	/* ADIDATA B, ADICS/SAMP B, ADICLK B */
1741 	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1742 };
1743 static const unsigned int adi_common_b_mux[] = {
1744 	/* ADIDATA B, ADICS/SAMP B, ADICLK B */
1745 	ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
1746 };
1747 static const unsigned int adi_chsel0_b_pins[] = {
1748 	/* ADICHS B 0 */
1749 	RCAR_GP_PIN(5, 28),
1750 };
1751 static const unsigned int adi_chsel0_b_mux[] = {
1752 	/* ADICHS B 0 */
1753 	ADICHS0_B_MARK,
1754 };
1755 static const unsigned int adi_chsel1_b_pins[] = {
1756 	/* ADICHS B 1 */
1757 	RCAR_GP_PIN(5, 29),
1758 };
1759 static const unsigned int adi_chsel1_b_mux[] = {
1760 	/* ADICHS B 1 */
1761 	ADICHS1_B_MARK,
1762 };
1763 static const unsigned int adi_chsel2_b_pins[] = {
1764 	/* ADICHS B 2 */
1765 	RCAR_GP_PIN(5, 30),
1766 };
1767 static const unsigned int adi_chsel2_b_mux[] = {
1768 	/* ADICHS B 2 */
1769 	ADICHS2_B_MARK,
1770 };
1771 
1772 /* - Audio Clock ------------------------------------------------------------ */
1773 static const unsigned int audio_clk_a_pins[] = {
1774 	/* CLK */
1775 	RCAR_GP_PIN(2, 28),
1776 };
1777 
1778 static const unsigned int audio_clk_a_mux[] = {
1779 	AUDIO_CLKA_MARK,
1780 };
1781 
1782 static const unsigned int audio_clk_b_pins[] = {
1783 	/* CLK */
1784 	RCAR_GP_PIN(2, 29),
1785 };
1786 
1787 static const unsigned int audio_clk_b_mux[] = {
1788 	AUDIO_CLKB_MARK,
1789 };
1790 
1791 static const unsigned int audio_clk_b_b_pins[] = {
1792 	/* CLK */
1793 	RCAR_GP_PIN(7, 20),
1794 };
1795 
1796 static const unsigned int audio_clk_b_b_mux[] = {
1797 	AUDIO_CLKB_B_MARK,
1798 };
1799 
1800 static const unsigned int audio_clk_c_pins[] = {
1801 	/* CLK */
1802 	RCAR_GP_PIN(2, 30),
1803 };
1804 
1805 static const unsigned int audio_clk_c_mux[] = {
1806 	AUDIO_CLKC_MARK,
1807 };
1808 
1809 static const unsigned int audio_clkout_pins[] = {
1810 	/* CLK */
1811 	RCAR_GP_PIN(2, 31),
1812 };
1813 
1814 static const unsigned int audio_clkout_mux[] = {
1815 	AUDIO_CLKOUT_MARK,
1816 };
1817 
1818 /* - AVB -------------------------------------------------------------------- */
1819 static const unsigned int avb_link_pins[] = {
1820 	RCAR_GP_PIN(5, 14),
1821 };
1822 static const unsigned int avb_link_mux[] = {
1823 	AVB_LINK_MARK,
1824 };
1825 static const unsigned int avb_magic_pins[] = {
1826 	RCAR_GP_PIN(5, 11),
1827 };
1828 static const unsigned int avb_magic_mux[] = {
1829 	AVB_MAGIC_MARK,
1830 };
1831 static const unsigned int avb_phy_int_pins[] = {
1832 	RCAR_GP_PIN(5, 16),
1833 };
1834 static const unsigned int avb_phy_int_mux[] = {
1835 	AVB_PHY_INT_MARK,
1836 };
1837 static const unsigned int avb_mdio_pins[] = {
1838 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1839 };
1840 static const unsigned int avb_mdio_mux[] = {
1841 	AVB_MDC_MARK, AVB_MDIO_MARK,
1842 };
1843 static const unsigned int avb_mii_pins[] = {
1844 	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1845 	RCAR_GP_PIN(5, 21),
1846 
1847 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1848 	RCAR_GP_PIN(5, 3),
1849 
1850 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1851 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1852 	RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1853 };
1854 static const unsigned int avb_mii_mux[] = {
1855 	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1856 	AVB_TXD3_MARK,
1857 
1858 	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1859 	AVB_RXD3_MARK,
1860 
1861 	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1862 	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1863 	AVB_TX_CLK_MARK, AVB_COL_MARK,
1864 };
1865 static const unsigned int avb_gmii_pins[] = {
1866 	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1867 	RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1868 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1869 
1870 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1871 	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1872 	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1873 
1874 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1875 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1876 	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1877 	RCAR_GP_PIN(5, 29),
1878 };
1879 static const unsigned int avb_gmii_mux[] = {
1880 	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1881 	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1882 	AVB_TXD6_MARK, AVB_TXD7_MARK,
1883 
1884 	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1885 	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1886 	AVB_RXD6_MARK, AVB_RXD7_MARK,
1887 
1888 	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1889 	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1890 	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1891 	AVB_COL_MARK,
1892 };
1893 
1894 /* - CAN -------------------------------------------------------------------- */
1895 
1896 static const unsigned int can0_data_pins[] = {
1897 	/* TX, RX */
1898 	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1899 };
1900 
1901 static const unsigned int can0_data_mux[] = {
1902 	CAN0_TX_MARK, CAN0_RX_MARK,
1903 };
1904 
1905 static const unsigned int can0_data_b_pins[] = {
1906 	/* TX, RX */
1907 	RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1908 };
1909 
1910 static const unsigned int can0_data_b_mux[] = {
1911 	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1912 };
1913 
1914 static const unsigned int can0_data_c_pins[] = {
1915 	/* TX, RX */
1916 	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1917 };
1918 
1919 static const unsigned int can0_data_c_mux[] = {
1920 	CAN0_TX_C_MARK,	CAN0_RX_C_MARK,
1921 };
1922 
1923 static const unsigned int can0_data_d_pins[] = {
1924 	/* TX, RX */
1925 	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1926 };
1927 
1928 static const unsigned int can0_data_d_mux[] = {
1929 	CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1930 };
1931 
1932 static const unsigned int can0_data_e_pins[] = {
1933 	/* TX, RX */
1934 	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1935 };
1936 
1937 static const unsigned int can0_data_e_mux[] = {
1938 	CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1939 };
1940 
1941 static const unsigned int can0_data_f_pins[] = {
1942 	/* TX, RX */
1943 	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1944 };
1945 
1946 static const unsigned int can0_data_f_mux[] = {
1947 	CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1948 };
1949 
1950 static const unsigned int can1_data_pins[] = {
1951 	/* TX, RX */
1952 	 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1953 };
1954 
1955 static const unsigned int can1_data_mux[] = {
1956 	CAN1_TX_MARK, CAN1_RX_MARK,
1957 };
1958 
1959 static const unsigned int can1_data_b_pins[] = {
1960 	/* TX, RX */
1961 	RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1962 };
1963 
1964 static const unsigned int can1_data_b_mux[] = {
1965 	CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1966 };
1967 
1968 static const unsigned int can1_data_c_pins[] = {
1969 	/* TX, RX */
1970 	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1971 };
1972 
1973 static const unsigned int can1_data_c_mux[] = {
1974 	CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1975 };
1976 
1977 static const unsigned int can1_data_d_pins[] = {
1978 	/* TX, RX */
1979 	 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1980 };
1981 
1982 static const unsigned int can1_data_d_mux[] = {
1983 	CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1984 };
1985 
1986 static const unsigned int can_clk_pins[] = {
1987 	/* CLK */
1988 	RCAR_GP_PIN(7, 2),
1989 };
1990 
1991 static const unsigned int can_clk_mux[] = {
1992 	CAN_CLK_MARK,
1993 };
1994 
1995 static const unsigned int can_clk_b_pins[] = {
1996 	/* CLK */
1997 	RCAR_GP_PIN(5, 21),
1998 };
1999 
2000 static const unsigned int can_clk_b_mux[] = {
2001 	CAN_CLK_B_MARK,
2002 };
2003 
2004 static const unsigned int can_clk_c_pins[] = {
2005 	/* CLK */
2006 	RCAR_GP_PIN(4, 30),
2007 };
2008 
2009 static const unsigned int can_clk_c_mux[] = {
2010 	CAN_CLK_C_MARK,
2011 };
2012 
2013 static const unsigned int can_clk_d_pins[] = {
2014 	/* CLK */
2015 	RCAR_GP_PIN(7, 19),
2016 };
2017 
2018 static const unsigned int can_clk_d_mux[] = {
2019 	CAN_CLK_D_MARK,
2020 };
2021 
2022 /* - DU --------------------------------------------------------------------- */
2023 static const unsigned int du_rgb666_pins[] = {
2024 	/* R[7:2], G[7:2], B[7:2] */
2025 	RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2026 	RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2027 	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2028 	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2029 	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2030 	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2031 };
2032 static const unsigned int du_rgb666_mux[] = {
2033 	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2034 	DU1_DR3_MARK, DU1_DR2_MARK,
2035 	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2036 	DU1_DG3_MARK, DU1_DG2_MARK,
2037 	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2038 	DU1_DB3_MARK, DU1_DB2_MARK,
2039 };
2040 static const unsigned int du_rgb888_pins[] = {
2041 	/* R[7:0], G[7:0], B[7:0] */
2042 	RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2043 	RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2044 	RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
2045 	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2046 	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2047 	RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
2048 	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2049 	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2050 	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2051 };
2052 static const unsigned int du_rgb888_mux[] = {
2053 	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2054 	DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
2055 	DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2056 	DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
2057 	DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2058 	DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
2059 };
2060 static const unsigned int du_clk_out_0_pins[] = {
2061 	/* CLKOUT */
2062 	RCAR_GP_PIN(3, 25),
2063 };
2064 static const unsigned int du_clk_out_0_mux[] = {
2065 	DU1_DOTCLKOUT0_MARK
2066 };
2067 static const unsigned int du_clk_out_1_pins[] = {
2068 	/* CLKOUT */
2069 	RCAR_GP_PIN(3, 26),
2070 };
2071 static const unsigned int du_clk_out_1_mux[] = {
2072 	DU1_DOTCLKOUT1_MARK
2073 };
2074 static const unsigned int du_sync_pins[] = {
2075 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2076 	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2077 };
2078 static const unsigned int du_sync_mux[] = {
2079 	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2080 };
2081 static const unsigned int du_oddf_pins[] = {
2082 	/* EXDISP/EXODDF/EXCDE */
2083 	RCAR_GP_PIN(3, 29),
2084 };
2085 static const unsigned int du_oddf_mux[] = {
2086 	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2087 };
2088 static const unsigned int du_cde_pins[] = {
2089 	/* CDE */
2090 	RCAR_GP_PIN(3, 31),
2091 };
2092 static const unsigned int du_cde_mux[] = {
2093 	DU1_CDE_MARK,
2094 };
2095 static const unsigned int du_disp_pins[] = {
2096 	/* DISP */
2097 	RCAR_GP_PIN(3, 30),
2098 };
2099 static const unsigned int du_disp_mux[] = {
2100 	DU1_DISP_MARK,
2101 };
2102 static const unsigned int du0_clk_in_pins[] = {
2103 	/* CLKIN */
2104 	RCAR_GP_PIN(6, 31),
2105 };
2106 static const unsigned int du0_clk_in_mux[] = {
2107 	DU0_DOTCLKIN_MARK
2108 };
2109 static const unsigned int du1_clk_in_pins[] = {
2110 	/* CLKIN */
2111 	RCAR_GP_PIN(3, 24),
2112 };
2113 static const unsigned int du1_clk_in_mux[] = {
2114 	DU1_DOTCLKIN_MARK
2115 };
2116 static const unsigned int du1_clk_in_b_pins[] = {
2117 	/* CLKIN */
2118 	RCAR_GP_PIN(7, 19),
2119 };
2120 static const unsigned int du1_clk_in_b_mux[] = {
2121 	DU1_DOTCLKIN_B_MARK,
2122 };
2123 static const unsigned int du1_clk_in_c_pins[] = {
2124 	/* CLKIN */
2125 	RCAR_GP_PIN(7, 20),
2126 };
2127 static const unsigned int du1_clk_in_c_mux[] = {
2128 	DU1_DOTCLKIN_C_MARK,
2129 };
2130 /* - ETH -------------------------------------------------------------------- */
2131 static const unsigned int eth_link_pins[] = {
2132 	/* LINK */
2133 	RCAR_GP_PIN(5, 18),
2134 };
2135 static const unsigned int eth_link_mux[] = {
2136 	ETH_LINK_MARK,
2137 };
2138 static const unsigned int eth_magic_pins[] = {
2139 	/* MAGIC */
2140 	RCAR_GP_PIN(5, 22),
2141 };
2142 static const unsigned int eth_magic_mux[] = {
2143 	ETH_MAGIC_MARK,
2144 };
2145 static const unsigned int eth_mdio_pins[] = {
2146 	/* MDC, MDIO */
2147 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2148 };
2149 static const unsigned int eth_mdio_mux[] = {
2150 	ETH_MDC_MARK, ETH_MDIO_MARK,
2151 };
2152 static const unsigned int eth_rmii_pins[] = {
2153 	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2154 	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2155 	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2156 	RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2157 };
2158 static const unsigned int eth_rmii_mux[] = {
2159 	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2160 	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2161 };
2162 
2163 /* - HSCIF0 ----------------------------------------------------------------- */
2164 static const unsigned int hscif0_data_pins[] = {
2165 	/* RX, TX */
2166 	RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2167 };
2168 static const unsigned int hscif0_data_mux[] = {
2169 	HRX0_MARK, HTX0_MARK,
2170 };
2171 static const unsigned int hscif0_clk_pins[] = {
2172 	/* SCK */
2173 	RCAR_GP_PIN(7, 2),
2174 };
2175 static const unsigned int hscif0_clk_mux[] = {
2176 	HSCK0_MARK,
2177 };
2178 static const unsigned int hscif0_ctrl_pins[] = {
2179 	/* RTS, CTS */
2180 	RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2181 };
2182 static const unsigned int hscif0_ctrl_mux[] = {
2183 	HRTS0_N_MARK, HCTS0_N_MARK,
2184 };
2185 static const unsigned int hscif0_data_b_pins[] = {
2186 	/* RX, TX */
2187 	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2188 };
2189 static const unsigned int hscif0_data_b_mux[] = {
2190 	HRX0_B_MARK, HTX0_B_MARK,
2191 };
2192 static const unsigned int hscif0_ctrl_b_pins[] = {
2193 	/* RTS, CTS */
2194 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2195 };
2196 static const unsigned int hscif0_ctrl_b_mux[] = {
2197 	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2198 };
2199 static const unsigned int hscif0_data_c_pins[] = {
2200 	/* RX, TX */
2201 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2202 };
2203 static const unsigned int hscif0_data_c_mux[] = {
2204 	HRX0_C_MARK, HTX0_C_MARK,
2205 };
2206 static const unsigned int hscif0_clk_c_pins[] = {
2207 	/* SCK */
2208 	RCAR_GP_PIN(5, 31),
2209 };
2210 static const unsigned int hscif0_clk_c_mux[] = {
2211 	HSCK0_C_MARK,
2212 };
2213 /* - HSCIF1 ----------------------------------------------------------------- */
2214 static const unsigned int hscif1_data_pins[] = {
2215 	/* RX, TX */
2216 	RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2217 };
2218 static const unsigned int hscif1_data_mux[] = {
2219 	HRX1_MARK, HTX1_MARK,
2220 };
2221 static const unsigned int hscif1_clk_pins[] = {
2222 	/* SCK */
2223 	RCAR_GP_PIN(7, 7),
2224 };
2225 static const unsigned int hscif1_clk_mux[] = {
2226 	HSCK1_MARK,
2227 };
2228 static const unsigned int hscif1_ctrl_pins[] = {
2229 	/* RTS, CTS */
2230 	RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2231 };
2232 static const unsigned int hscif1_ctrl_mux[] = {
2233 	HRTS1_N_MARK, HCTS1_N_MARK,
2234 };
2235 static const unsigned int hscif1_data_b_pins[] = {
2236 	/* RX, TX */
2237 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2238 };
2239 static const unsigned int hscif1_data_b_mux[] = {
2240 	HRX1_B_MARK, HTX1_B_MARK,
2241 };
2242 static const unsigned int hscif1_data_c_pins[] = {
2243 	/* RX, TX */
2244 	RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2245 };
2246 static const unsigned int hscif1_data_c_mux[] = {
2247 	HRX1_C_MARK, HTX1_C_MARK,
2248 };
2249 static const unsigned int hscif1_clk_c_pins[] = {
2250 	/* SCK */
2251 	RCAR_GP_PIN(7, 16),
2252 };
2253 static const unsigned int hscif1_clk_c_mux[] = {
2254 	HSCK1_C_MARK,
2255 };
2256 static const unsigned int hscif1_ctrl_c_pins[] = {
2257 	/* RTS, CTS */
2258 	RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2259 };
2260 static const unsigned int hscif1_ctrl_c_mux[] = {
2261 	HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2262 };
2263 static const unsigned int hscif1_data_d_pins[] = {
2264 	/* RX, TX */
2265 	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2266 };
2267 static const unsigned int hscif1_data_d_mux[] = {
2268 	HRX1_D_MARK, HTX1_D_MARK,
2269 };
2270 static const unsigned int hscif1_data_e_pins[] = {
2271 	/* RX, TX */
2272 	RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2273 };
2274 static const unsigned int hscif1_data_e_mux[] = {
2275 	HRX1_C_MARK, HTX1_C_MARK,
2276 };
2277 static const unsigned int hscif1_clk_e_pins[] = {
2278 	/* SCK */
2279 	RCAR_GP_PIN(2, 6),
2280 };
2281 static const unsigned int hscif1_clk_e_mux[] = {
2282 	HSCK1_E_MARK,
2283 };
2284 static const unsigned int hscif1_ctrl_e_pins[] = {
2285 	/* RTS, CTS */
2286 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2287 };
2288 static const unsigned int hscif1_ctrl_e_mux[] = {
2289 	HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2290 };
2291 /* - HSCIF2 ----------------------------------------------------------------- */
2292 static const unsigned int hscif2_data_pins[] = {
2293 	/* RX, TX */
2294 	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2295 };
2296 static const unsigned int hscif2_data_mux[] = {
2297 	HRX2_MARK, HTX2_MARK,
2298 };
2299 static const unsigned int hscif2_clk_pins[] = {
2300 	/* SCK */
2301 	RCAR_GP_PIN(4, 15),
2302 };
2303 static const unsigned int hscif2_clk_mux[] = {
2304 	HSCK2_MARK,
2305 };
2306 static const unsigned int hscif2_ctrl_pins[] = {
2307 	/* RTS, CTS */
2308 	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2309 };
2310 static const unsigned int hscif2_ctrl_mux[] = {
2311 	HRTS2_N_MARK, HCTS2_N_MARK,
2312 };
2313 static const unsigned int hscif2_data_b_pins[] = {
2314 	/* RX, TX */
2315 	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2316 };
2317 static const unsigned int hscif2_data_b_mux[] = {
2318 	HRX2_B_MARK, HTX2_B_MARK,
2319 };
2320 static const unsigned int hscif2_ctrl_b_pins[] = {
2321 	/* RTS, CTS */
2322 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2323 };
2324 static const unsigned int hscif2_ctrl_b_mux[] = {
2325 	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2326 };
2327 static const unsigned int hscif2_data_c_pins[] = {
2328 	/* RX, TX */
2329 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2330 };
2331 static const unsigned int hscif2_data_c_mux[] = {
2332 	HRX2_C_MARK, HTX2_C_MARK,
2333 };
2334 static const unsigned int hscif2_clk_c_pins[] = {
2335 	/* SCK */
2336 	RCAR_GP_PIN(5, 31),
2337 };
2338 static const unsigned int hscif2_clk_c_mux[] = {
2339 	HSCK2_C_MARK,
2340 };
2341 static const unsigned int hscif2_data_d_pins[] = {
2342 	/* RX, TX */
2343 	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2344 };
2345 static const unsigned int hscif2_data_d_mux[] = {
2346 	HRX2_B_MARK, HTX2_D_MARK,
2347 };
2348 /* - I2C0 ------------------------------------------------------------------- */
2349 static const unsigned int i2c0_pins[] = {
2350 	/* SCL, SDA */
2351 	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2352 };
2353 static const unsigned int i2c0_mux[] = {
2354 	I2C0_SCL_MARK, I2C0_SDA_MARK,
2355 };
2356 static const unsigned int i2c0_b_pins[] = {
2357 	/* SCL, SDA */
2358 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2359 };
2360 static const unsigned int i2c0_b_mux[] = {
2361 	I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2362 };
2363 static const unsigned int i2c0_c_pins[] = {
2364 	/* SCL, SDA */
2365 	RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2366 };
2367 static const unsigned int i2c0_c_mux[] = {
2368 	I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2369 };
2370 /* - I2C1 ------------------------------------------------------------------- */
2371 static const unsigned int i2c1_pins[] = {
2372 	/* SCL, SDA */
2373 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2374 };
2375 static const unsigned int i2c1_mux[] = {
2376 	I2C1_SCL_MARK, I2C1_SDA_MARK,
2377 };
2378 static const unsigned int i2c1_b_pins[] = {
2379 	/* SCL, SDA */
2380 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2381 };
2382 static const unsigned int i2c1_b_mux[] = {
2383 	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2384 };
2385 static const unsigned int i2c1_c_pins[] = {
2386 	/* SCL, SDA */
2387 	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2388 };
2389 static const unsigned int i2c1_c_mux[] = {
2390 	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2391 };
2392 static const unsigned int i2c1_d_pins[] = {
2393 	/* SCL, SDA */
2394 	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2395 };
2396 static const unsigned int i2c1_d_mux[] = {
2397 	I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2398 };
2399 static const unsigned int i2c1_e_pins[] = {
2400 	/* SCL, SDA */
2401 	RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2402 };
2403 static const unsigned int i2c1_e_mux[] = {
2404 	I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2405 };
2406 /* - I2C2 ------------------------------------------------------------------- */
2407 static const unsigned int i2c2_pins[] = {
2408 	/* SCL, SDA */
2409 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2410 };
2411 static const unsigned int i2c2_mux[] = {
2412 	I2C2_SCL_MARK, I2C2_SDA_MARK,
2413 };
2414 static const unsigned int i2c2_b_pins[] = {
2415 	/* SCL, SDA */
2416 	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2417 };
2418 static const unsigned int i2c2_b_mux[] = {
2419 	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2420 };
2421 static const unsigned int i2c2_c_pins[] = {
2422 	/* SCL, SDA */
2423 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2424 };
2425 static const unsigned int i2c2_c_mux[] = {
2426 	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2427 };
2428 static const unsigned int i2c2_d_pins[] = {
2429 	/* SCL, SDA */
2430 	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2431 };
2432 static const unsigned int i2c2_d_mux[] = {
2433 	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2434 };
2435 /* - I2C3 ------------------------------------------------------------------- */
2436 static const unsigned int i2c3_pins[] = {
2437 	/* SCL, SDA */
2438 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2439 };
2440 static const unsigned int i2c3_mux[] = {
2441 	I2C3_SCL_MARK, I2C3_SDA_MARK,
2442 };
2443 static const unsigned int i2c3_b_pins[] = {
2444 	/* SCL, SDA */
2445 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2446 };
2447 static const unsigned int i2c3_b_mux[] = {
2448 	I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2449 };
2450 static const unsigned int i2c3_c_pins[] = {
2451 	/* SCL, SDA */
2452 	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2453 };
2454 static const unsigned int i2c3_c_mux[] = {
2455 	I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2456 };
2457 static const unsigned int i2c3_d_pins[] = {
2458 	/* SCL, SDA */
2459 	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2460 };
2461 static const unsigned int i2c3_d_mux[] = {
2462 	I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2463 };
2464 /* - I2C4 ------------------------------------------------------------------- */
2465 static const unsigned int i2c4_pins[] = {
2466 	/* SCL, SDA */
2467 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2468 };
2469 static const unsigned int i2c4_mux[] = {
2470 	I2C4_SCL_MARK, I2C4_SDA_MARK,
2471 };
2472 static const unsigned int i2c4_b_pins[] = {
2473 	/* SCL, SDA */
2474 	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2475 };
2476 static const unsigned int i2c4_b_mux[] = {
2477 	I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2478 };
2479 static const unsigned int i2c4_c_pins[] = {
2480 	/* SCL, SDA */
2481 	RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2482 };
2483 static const unsigned int i2c4_c_mux[] = {
2484 	I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2485 };
2486 /* - I2C7 ------------------------------------------------------------------- */
2487 static const unsigned int i2c7_pins[] = {
2488 	/* SCL, SDA */
2489 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2490 };
2491 static const unsigned int i2c7_mux[] = {
2492 	IIC0_SCL_MARK, IIC0_SDA_MARK,
2493 };
2494 static const unsigned int i2c7_b_pins[] = {
2495 	/* SCL, SDA */
2496 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2497 };
2498 static const unsigned int i2c7_b_mux[] = {
2499 	IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
2500 };
2501 static const unsigned int i2c7_c_pins[] = {
2502 	/* SCL, SDA */
2503 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2504 };
2505 static const unsigned int i2c7_c_mux[] = {
2506 	IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
2507 };
2508 /* - I2C8 ------------------------------------------------------------------- */
2509 static const unsigned int i2c8_pins[] = {
2510 	/* SCL, SDA */
2511 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2512 };
2513 static const unsigned int i2c8_mux[] = {
2514 	IIC1_SCL_MARK, IIC1_SDA_MARK,
2515 };
2516 static const unsigned int i2c8_b_pins[] = {
2517 	/* SCL, SDA */
2518 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2519 };
2520 static const unsigned int i2c8_b_mux[] = {
2521 	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2522 };
2523 static const unsigned int i2c8_c_pins[] = {
2524 	/* SCL, SDA */
2525 	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2526 };
2527 static const unsigned int i2c8_c_mux[] = {
2528 	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2529 };
2530 /* - INTC ------------------------------------------------------------------- */
2531 static const unsigned int intc_irq0_pins[] = {
2532 	/* IRQ */
2533 	RCAR_GP_PIN(7, 10),
2534 };
2535 static const unsigned int intc_irq0_mux[] = {
2536 	IRQ0_MARK,
2537 };
2538 static const unsigned int intc_irq1_pins[] = {
2539 	/* IRQ */
2540 	RCAR_GP_PIN(7, 11),
2541 };
2542 static const unsigned int intc_irq1_mux[] = {
2543 	IRQ1_MARK,
2544 };
2545 static const unsigned int intc_irq2_pins[] = {
2546 	/* IRQ */
2547 	RCAR_GP_PIN(7, 12),
2548 };
2549 static const unsigned int intc_irq2_mux[] = {
2550 	IRQ2_MARK,
2551 };
2552 static const unsigned int intc_irq3_pins[] = {
2553 	/* IRQ */
2554 	RCAR_GP_PIN(7, 13),
2555 };
2556 static const unsigned int intc_irq3_mux[] = {
2557 	IRQ3_MARK,
2558 };
2559 /* - MLB+ ------------------------------------------------------------------- */
2560 static const unsigned int mlb_3pin_pins[] = {
2561 	RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2562 };
2563 static const unsigned int mlb_3pin_mux[] = {
2564 	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2565 };
2566 /* - MMCIF ------------------------------------------------------------------ */
2567 static const unsigned int mmc_data1_pins[] = {
2568 	/* D[0] */
2569 	RCAR_GP_PIN(6, 18),
2570 };
2571 static const unsigned int mmc_data1_mux[] = {
2572 	MMC_D0_MARK,
2573 };
2574 static const unsigned int mmc_data4_pins[] = {
2575 	/* D[0:3] */
2576 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2577 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2578 };
2579 static const unsigned int mmc_data4_mux[] = {
2580 	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2581 };
2582 static const unsigned int mmc_data8_pins[] = {
2583 	/* D[0:7] */
2584 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2585 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2586 	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2587 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2588 };
2589 static const unsigned int mmc_data8_mux[] = {
2590 	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2591 	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2592 };
2593 static const unsigned int mmc_data8_b_pins[] = {
2594 	/* D[0:7] */
2595 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2596 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2597 	RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2598 	RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
2599 };
2600 static const unsigned int mmc_data8_b_mux[] = {
2601 	MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2602 	MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
2603 };
2604 static const unsigned int mmc_ctrl_pins[] = {
2605 	/* CLK, CMD */
2606 	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2607 };
2608 static const unsigned int mmc_ctrl_mux[] = {
2609 	MMC_CLK_MARK, MMC_CMD_MARK,
2610 };
2611 /* - MSIOF0 ----------------------------------------------------------------- */
2612 static const unsigned int msiof0_clk_pins[] = {
2613 	/* SCK */
2614 	RCAR_GP_PIN(6, 24),
2615 };
2616 static const unsigned int msiof0_clk_mux[] = {
2617 	MSIOF0_SCK_MARK,
2618 };
2619 static const unsigned int msiof0_sync_pins[] = {
2620 	/* SYNC */
2621 	RCAR_GP_PIN(6, 25),
2622 };
2623 static const unsigned int msiof0_sync_mux[] = {
2624 	MSIOF0_SYNC_MARK,
2625 };
2626 static const unsigned int msiof0_ss1_pins[] = {
2627 	/* SS1 */
2628 	RCAR_GP_PIN(6, 28),
2629 };
2630 static const unsigned int msiof0_ss1_mux[] = {
2631 	MSIOF0_SS1_MARK,
2632 };
2633 static const unsigned int msiof0_ss2_pins[] = {
2634 	/* SS2 */
2635 	RCAR_GP_PIN(6, 29),
2636 };
2637 static const unsigned int msiof0_ss2_mux[] = {
2638 	MSIOF0_SS2_MARK,
2639 };
2640 static const unsigned int msiof0_rx_pins[] = {
2641 	/* RXD */
2642 	RCAR_GP_PIN(6, 27),
2643 };
2644 static const unsigned int msiof0_rx_mux[] = {
2645 	MSIOF0_RXD_MARK,
2646 };
2647 static const unsigned int msiof0_tx_pins[] = {
2648 	/* TXD */
2649 	RCAR_GP_PIN(6, 26),
2650 };
2651 static const unsigned int msiof0_tx_mux[] = {
2652 	MSIOF0_TXD_MARK,
2653 };
2654 
2655 static const unsigned int msiof0_clk_b_pins[] = {
2656 	/* SCK */
2657 	RCAR_GP_PIN(0, 16),
2658 };
2659 static const unsigned int msiof0_clk_b_mux[] = {
2660 	MSIOF0_SCK_B_MARK,
2661 };
2662 static const unsigned int msiof0_sync_b_pins[] = {
2663 	/* SYNC */
2664 	RCAR_GP_PIN(0, 17),
2665 };
2666 static const unsigned int msiof0_sync_b_mux[] = {
2667 	MSIOF0_SYNC_B_MARK,
2668 };
2669 static const unsigned int msiof0_ss1_b_pins[] = {
2670 	/* SS1 */
2671 	RCAR_GP_PIN(0, 18),
2672 };
2673 static const unsigned int msiof0_ss1_b_mux[] = {
2674 	MSIOF0_SS1_B_MARK,
2675 };
2676 static const unsigned int msiof0_ss2_b_pins[] = {
2677 	/* SS2 */
2678 	RCAR_GP_PIN(0, 19),
2679 };
2680 static const unsigned int msiof0_ss2_b_mux[] = {
2681 	MSIOF0_SS2_B_MARK,
2682 };
2683 static const unsigned int msiof0_rx_b_pins[] = {
2684 	/* RXD */
2685 	RCAR_GP_PIN(0, 21),
2686 };
2687 static const unsigned int msiof0_rx_b_mux[] = {
2688 	MSIOF0_RXD_B_MARK,
2689 };
2690 static const unsigned int msiof0_tx_b_pins[] = {
2691 	/* TXD */
2692 	RCAR_GP_PIN(0, 20),
2693 };
2694 static const unsigned int msiof0_tx_b_mux[] = {
2695 	MSIOF0_TXD_B_MARK,
2696 };
2697 
2698 static const unsigned int msiof0_clk_c_pins[] = {
2699 	/* SCK */
2700 	RCAR_GP_PIN(5, 26),
2701 };
2702 static const unsigned int msiof0_clk_c_mux[] = {
2703 	MSIOF0_SCK_C_MARK,
2704 };
2705 static const unsigned int msiof0_sync_c_pins[] = {
2706 	/* SYNC */
2707 	RCAR_GP_PIN(5, 25),
2708 };
2709 static const unsigned int msiof0_sync_c_mux[] = {
2710 	MSIOF0_SYNC_C_MARK,
2711 };
2712 static const unsigned int msiof0_ss1_c_pins[] = {
2713 	/* SS1 */
2714 	RCAR_GP_PIN(5, 27),
2715 };
2716 static const unsigned int msiof0_ss1_c_mux[] = {
2717 	MSIOF0_SS1_C_MARK,
2718 };
2719 static const unsigned int msiof0_ss2_c_pins[] = {
2720 	/* SS2 */
2721 	RCAR_GP_PIN(5, 28),
2722 };
2723 static const unsigned int msiof0_ss2_c_mux[] = {
2724 	MSIOF0_SS2_C_MARK,
2725 };
2726 static const unsigned int msiof0_rx_c_pins[] = {
2727 	/* RXD */
2728 	RCAR_GP_PIN(5, 29),
2729 };
2730 static const unsigned int msiof0_rx_c_mux[] = {
2731 	MSIOF0_RXD_C_MARK,
2732 };
2733 static const unsigned int msiof0_tx_c_pins[] = {
2734 	/* TXD */
2735 	RCAR_GP_PIN(5, 30),
2736 };
2737 static const unsigned int msiof0_tx_c_mux[] = {
2738 	MSIOF0_TXD_C_MARK,
2739 };
2740 /* - MSIOF1 ----------------------------------------------------------------- */
2741 static const unsigned int msiof1_clk_pins[] = {
2742 	/* SCK */
2743 	RCAR_GP_PIN(0, 22),
2744 };
2745 static const unsigned int msiof1_clk_mux[] = {
2746 	MSIOF1_SCK_MARK,
2747 };
2748 static const unsigned int msiof1_sync_pins[] = {
2749 	/* SYNC */
2750 	RCAR_GP_PIN(0, 23),
2751 };
2752 static const unsigned int msiof1_sync_mux[] = {
2753 	MSIOF1_SYNC_MARK,
2754 };
2755 static const unsigned int msiof1_ss1_pins[] = {
2756 	/* SS1 */
2757 	RCAR_GP_PIN(0, 24),
2758 };
2759 static const unsigned int msiof1_ss1_mux[] = {
2760 	MSIOF1_SS1_MARK,
2761 };
2762 static const unsigned int msiof1_ss2_pins[] = {
2763 	/* SS2 */
2764 	RCAR_GP_PIN(0, 25),
2765 };
2766 static const unsigned int msiof1_ss2_mux[] = {
2767 	MSIOF1_SS2_MARK,
2768 };
2769 static const unsigned int msiof1_rx_pins[] = {
2770 	/* RXD */
2771 	RCAR_GP_PIN(0, 27),
2772 };
2773 static const unsigned int msiof1_rx_mux[] = {
2774 	MSIOF1_RXD_MARK,
2775 };
2776 static const unsigned int msiof1_tx_pins[] = {
2777 	/* TXD */
2778 	RCAR_GP_PIN(0, 26),
2779 };
2780 static const unsigned int msiof1_tx_mux[] = {
2781 	MSIOF1_TXD_MARK,
2782 };
2783 
2784 static const unsigned int msiof1_clk_b_pins[] = {
2785 	/* SCK */
2786 	RCAR_GP_PIN(2, 29),
2787 };
2788 static const unsigned int msiof1_clk_b_mux[] = {
2789 	MSIOF1_SCK_B_MARK,
2790 };
2791 static const unsigned int msiof1_sync_b_pins[] = {
2792 	/* SYNC */
2793 	RCAR_GP_PIN(2, 30),
2794 };
2795 static const unsigned int msiof1_sync_b_mux[] = {
2796 	MSIOF1_SYNC_B_MARK,
2797 };
2798 static const unsigned int msiof1_ss1_b_pins[] = {
2799 	/* SS1 */
2800 	RCAR_GP_PIN(2, 31),
2801 };
2802 static const unsigned int msiof1_ss1_b_mux[] = {
2803 	MSIOF1_SS1_B_MARK,
2804 };
2805 static const unsigned int msiof1_ss2_b_pins[] = {
2806 	/* SS2 */
2807 	RCAR_GP_PIN(7, 16),
2808 };
2809 static const unsigned int msiof1_ss2_b_mux[] = {
2810 	MSIOF1_SS2_B_MARK,
2811 };
2812 static const unsigned int msiof1_rx_b_pins[] = {
2813 	/* RXD */
2814 	RCAR_GP_PIN(7, 18),
2815 };
2816 static const unsigned int msiof1_rx_b_mux[] = {
2817 	MSIOF1_RXD_B_MARK,
2818 };
2819 static const unsigned int msiof1_tx_b_pins[] = {
2820 	/* TXD */
2821 	RCAR_GP_PIN(7, 17),
2822 };
2823 static const unsigned int msiof1_tx_b_mux[] = {
2824 	MSIOF1_TXD_B_MARK,
2825 };
2826 
2827 static const unsigned int msiof1_clk_c_pins[] = {
2828 	/* SCK */
2829 	RCAR_GP_PIN(2, 15),
2830 };
2831 static const unsigned int msiof1_clk_c_mux[] = {
2832 	MSIOF1_SCK_C_MARK,
2833 };
2834 static const unsigned int msiof1_sync_c_pins[] = {
2835 	/* SYNC */
2836 	RCAR_GP_PIN(2, 16),
2837 };
2838 static const unsigned int msiof1_sync_c_mux[] = {
2839 	MSIOF1_SYNC_C_MARK,
2840 };
2841 static const unsigned int msiof1_rx_c_pins[] = {
2842 	/* RXD */
2843 	RCAR_GP_PIN(2, 18),
2844 };
2845 static const unsigned int msiof1_rx_c_mux[] = {
2846 	MSIOF1_RXD_C_MARK,
2847 };
2848 static const unsigned int msiof1_tx_c_pins[] = {
2849 	/* TXD */
2850 	RCAR_GP_PIN(2, 17),
2851 };
2852 static const unsigned int msiof1_tx_c_mux[] = {
2853 	MSIOF1_TXD_C_MARK,
2854 };
2855 
2856 static const unsigned int msiof1_clk_d_pins[] = {
2857 	/* SCK */
2858 	RCAR_GP_PIN(0, 28),
2859 };
2860 static const unsigned int msiof1_clk_d_mux[] = {
2861 	MSIOF1_SCK_D_MARK,
2862 };
2863 static const unsigned int msiof1_sync_d_pins[] = {
2864 	/* SYNC */
2865 	RCAR_GP_PIN(0, 30),
2866 };
2867 static const unsigned int msiof1_sync_d_mux[] = {
2868 	MSIOF1_SYNC_D_MARK,
2869 };
2870 static const unsigned int msiof1_ss1_d_pins[] = {
2871 	/* SS1 */
2872 	RCAR_GP_PIN(0, 29),
2873 };
2874 static const unsigned int msiof1_ss1_d_mux[] = {
2875 	MSIOF1_SS1_D_MARK,
2876 };
2877 static const unsigned int msiof1_rx_d_pins[] = {
2878 	/* RXD */
2879 	RCAR_GP_PIN(0, 27),
2880 };
2881 static const unsigned int msiof1_rx_d_mux[] = {
2882 	MSIOF1_RXD_D_MARK,
2883 };
2884 static const unsigned int msiof1_tx_d_pins[] = {
2885 	/* TXD */
2886 	RCAR_GP_PIN(0, 26),
2887 };
2888 static const unsigned int msiof1_tx_d_mux[] = {
2889 	MSIOF1_TXD_D_MARK,
2890 };
2891 
2892 static const unsigned int msiof1_clk_e_pins[] = {
2893 	/* SCK */
2894 	RCAR_GP_PIN(5, 18),
2895 };
2896 static const unsigned int msiof1_clk_e_mux[] = {
2897 	MSIOF1_SCK_E_MARK,
2898 };
2899 static const unsigned int msiof1_sync_e_pins[] = {
2900 	/* SYNC */
2901 	RCAR_GP_PIN(5, 19),
2902 };
2903 static const unsigned int msiof1_sync_e_mux[] = {
2904 	MSIOF1_SYNC_E_MARK,
2905 };
2906 static const unsigned int msiof1_rx_e_pins[] = {
2907 	/* RXD */
2908 	RCAR_GP_PIN(5, 17),
2909 };
2910 static const unsigned int msiof1_rx_e_mux[] = {
2911 	MSIOF1_RXD_E_MARK,
2912 };
2913 static const unsigned int msiof1_tx_e_pins[] = {
2914 	/* TXD */
2915 	RCAR_GP_PIN(5, 20),
2916 };
2917 static const unsigned int msiof1_tx_e_mux[] = {
2918 	MSIOF1_TXD_E_MARK,
2919 };
2920 /* - MSIOF2 ----------------------------------------------------------------- */
2921 static const unsigned int msiof2_clk_pins[] = {
2922 	/* SCK */
2923 	RCAR_GP_PIN(1, 13),
2924 };
2925 static const unsigned int msiof2_clk_mux[] = {
2926 	MSIOF2_SCK_MARK,
2927 };
2928 static const unsigned int msiof2_sync_pins[] = {
2929 	/* SYNC */
2930 	RCAR_GP_PIN(1, 14),
2931 };
2932 static const unsigned int msiof2_sync_mux[] = {
2933 	MSIOF2_SYNC_MARK,
2934 };
2935 static const unsigned int msiof2_ss1_pins[] = {
2936 	/* SS1 */
2937 	RCAR_GP_PIN(1, 17),
2938 };
2939 static const unsigned int msiof2_ss1_mux[] = {
2940 	MSIOF2_SS1_MARK,
2941 };
2942 static const unsigned int msiof2_ss2_pins[] = {
2943 	/* SS2 */
2944 	RCAR_GP_PIN(1, 18),
2945 };
2946 static const unsigned int msiof2_ss2_mux[] = {
2947 	MSIOF2_SS2_MARK,
2948 };
2949 static const unsigned int msiof2_rx_pins[] = {
2950 	/* RXD */
2951 	RCAR_GP_PIN(1, 16),
2952 };
2953 static const unsigned int msiof2_rx_mux[] = {
2954 	MSIOF2_RXD_MARK,
2955 };
2956 static const unsigned int msiof2_tx_pins[] = {
2957 	/* TXD */
2958 	RCAR_GP_PIN(1, 15),
2959 };
2960 static const unsigned int msiof2_tx_mux[] = {
2961 	MSIOF2_TXD_MARK,
2962 };
2963 
2964 static const unsigned int msiof2_clk_b_pins[] = {
2965 	/* SCK */
2966 	RCAR_GP_PIN(3, 0),
2967 };
2968 static const unsigned int msiof2_clk_b_mux[] = {
2969 	MSIOF2_SCK_B_MARK,
2970 };
2971 static const unsigned int msiof2_sync_b_pins[] = {
2972 	/* SYNC */
2973 	RCAR_GP_PIN(3, 1),
2974 };
2975 static const unsigned int msiof2_sync_b_mux[] = {
2976 	MSIOF2_SYNC_B_MARK,
2977 };
2978 static const unsigned int msiof2_ss1_b_pins[] = {
2979 	/* SS1 */
2980 	RCAR_GP_PIN(3, 8),
2981 };
2982 static const unsigned int msiof2_ss1_b_mux[] = {
2983 	MSIOF2_SS1_B_MARK,
2984 };
2985 static const unsigned int msiof2_ss2_b_pins[] = {
2986 	/* SS2 */
2987 	RCAR_GP_PIN(3, 9),
2988 };
2989 static const unsigned int msiof2_ss2_b_mux[] = {
2990 	MSIOF2_SS2_B_MARK,
2991 };
2992 static const unsigned int msiof2_rx_b_pins[] = {
2993 	/* RXD */
2994 	RCAR_GP_PIN(3, 17),
2995 };
2996 static const unsigned int msiof2_rx_b_mux[] = {
2997 	MSIOF2_RXD_B_MARK,
2998 };
2999 static const unsigned int msiof2_tx_b_pins[] = {
3000 	/* TXD */
3001 	RCAR_GP_PIN(3, 16),
3002 };
3003 static const unsigned int msiof2_tx_b_mux[] = {
3004 	MSIOF2_TXD_B_MARK,
3005 };
3006 
3007 static const unsigned int msiof2_clk_c_pins[] = {
3008 	/* SCK */
3009 	RCAR_GP_PIN(2, 2),
3010 };
3011 static const unsigned int msiof2_clk_c_mux[] = {
3012 	MSIOF2_SCK_C_MARK,
3013 };
3014 static const unsigned int msiof2_sync_c_pins[] = {
3015 	/* SYNC */
3016 	RCAR_GP_PIN(2, 3),
3017 };
3018 static const unsigned int msiof2_sync_c_mux[] = {
3019 	MSIOF2_SYNC_C_MARK,
3020 };
3021 static const unsigned int msiof2_rx_c_pins[] = {
3022 	/* RXD */
3023 	RCAR_GP_PIN(2, 5),
3024 };
3025 static const unsigned int msiof2_rx_c_mux[] = {
3026 	MSIOF2_RXD_C_MARK,
3027 };
3028 static const unsigned int msiof2_tx_c_pins[] = {
3029 	/* TXD */
3030 	RCAR_GP_PIN(2, 4),
3031 };
3032 static const unsigned int msiof2_tx_c_mux[] = {
3033 	MSIOF2_TXD_C_MARK,
3034 };
3035 
3036 static const unsigned int msiof2_clk_d_pins[] = {
3037 	/* SCK */
3038 	RCAR_GP_PIN(2, 14),
3039 };
3040 static const unsigned int msiof2_clk_d_mux[] = {
3041 	MSIOF2_SCK_D_MARK,
3042 };
3043 static const unsigned int msiof2_sync_d_pins[] = {
3044 	/* SYNC */
3045 	RCAR_GP_PIN(2, 15),
3046 };
3047 static const unsigned int msiof2_sync_d_mux[] = {
3048 	MSIOF2_SYNC_D_MARK,
3049 };
3050 static const unsigned int msiof2_ss1_d_pins[] = {
3051 	/* SS1 */
3052 	RCAR_GP_PIN(2, 17),
3053 };
3054 static const unsigned int msiof2_ss1_d_mux[] = {
3055 	MSIOF2_SS1_D_MARK,
3056 };
3057 static const unsigned int msiof2_ss2_d_pins[] = {
3058 	/* SS2 */
3059 	RCAR_GP_PIN(2, 19),
3060 };
3061 static const unsigned int msiof2_ss2_d_mux[] = {
3062 	MSIOF2_SS2_D_MARK,
3063 };
3064 static const unsigned int msiof2_rx_d_pins[] = {
3065 	/* RXD */
3066 	RCAR_GP_PIN(2, 18),
3067 };
3068 static const unsigned int msiof2_rx_d_mux[] = {
3069 	MSIOF2_RXD_D_MARK,
3070 };
3071 static const unsigned int msiof2_tx_d_pins[] = {
3072 	/* TXD */
3073 	RCAR_GP_PIN(2, 16),
3074 };
3075 static const unsigned int msiof2_tx_d_mux[] = {
3076 	MSIOF2_TXD_D_MARK,
3077 };
3078 
3079 static const unsigned int msiof2_clk_e_pins[] = {
3080 	/* SCK */
3081 	RCAR_GP_PIN(7, 15),
3082 };
3083 static const unsigned int msiof2_clk_e_mux[] = {
3084 	MSIOF2_SCK_E_MARK,
3085 };
3086 static const unsigned int msiof2_sync_e_pins[] = {
3087 	/* SYNC */
3088 	RCAR_GP_PIN(7, 16),
3089 };
3090 static const unsigned int msiof2_sync_e_mux[] = {
3091 	MSIOF2_SYNC_E_MARK,
3092 };
3093 static const unsigned int msiof2_rx_e_pins[] = {
3094 	/* RXD */
3095 	RCAR_GP_PIN(7, 14),
3096 };
3097 static const unsigned int msiof2_rx_e_mux[] = {
3098 	MSIOF2_RXD_E_MARK,
3099 };
3100 static const unsigned int msiof2_tx_e_pins[] = {
3101 	/* TXD */
3102 	RCAR_GP_PIN(7, 13),
3103 };
3104 static const unsigned int msiof2_tx_e_mux[] = {
3105 	MSIOF2_TXD_E_MARK,
3106 };
3107 /* - PWM -------------------------------------------------------------------- */
3108 static const unsigned int pwm0_pins[] = {
3109 	RCAR_GP_PIN(6, 14),
3110 };
3111 static const unsigned int pwm0_mux[] = {
3112 	PWM0_MARK,
3113 };
3114 static const unsigned int pwm0_b_pins[] = {
3115 	RCAR_GP_PIN(5, 30),
3116 };
3117 static const unsigned int pwm0_b_mux[] = {
3118 	PWM0_B_MARK,
3119 };
3120 static const unsigned int pwm1_pins[] = {
3121 	RCAR_GP_PIN(1, 17),
3122 };
3123 static const unsigned int pwm1_mux[] = {
3124 	PWM1_MARK,
3125 };
3126 static const unsigned int pwm1_b_pins[] = {
3127 	RCAR_GP_PIN(6, 15),
3128 };
3129 static const unsigned int pwm1_b_mux[] = {
3130 	PWM1_B_MARK,
3131 };
3132 static const unsigned int pwm2_pins[] = {
3133 	RCAR_GP_PIN(1, 18),
3134 };
3135 static const unsigned int pwm2_mux[] = {
3136 	PWM2_MARK,
3137 };
3138 static const unsigned int pwm2_b_pins[] = {
3139 	RCAR_GP_PIN(0, 16),
3140 };
3141 static const unsigned int pwm2_b_mux[] = {
3142 	PWM2_B_MARK,
3143 };
3144 static const unsigned int pwm3_pins[] = {
3145 	RCAR_GP_PIN(1, 24),
3146 };
3147 static const unsigned int pwm3_mux[] = {
3148 	PWM3_MARK,
3149 };
3150 static const unsigned int pwm4_pins[] = {
3151 	RCAR_GP_PIN(3, 26),
3152 };
3153 static const unsigned int pwm4_mux[] = {
3154 	PWM4_MARK,
3155 };
3156 static const unsigned int pwm4_b_pins[] = {
3157 	RCAR_GP_PIN(3, 31),
3158 };
3159 static const unsigned int pwm4_b_mux[] = {
3160 	PWM4_B_MARK,
3161 };
3162 static const unsigned int pwm5_pins[] = {
3163 	RCAR_GP_PIN(7, 21),
3164 };
3165 static const unsigned int pwm5_mux[] = {
3166 	PWM5_MARK,
3167 };
3168 static const unsigned int pwm5_b_pins[] = {
3169 	RCAR_GP_PIN(7, 20),
3170 };
3171 static const unsigned int pwm5_b_mux[] = {
3172 	PWM5_B_MARK,
3173 };
3174 static const unsigned int pwm6_pins[] = {
3175 	RCAR_GP_PIN(7, 22),
3176 };
3177 static const unsigned int pwm6_mux[] = {
3178 	PWM6_MARK,
3179 };
3180 /* - QSPI ------------------------------------------------------------------- */
3181 static const unsigned int qspi_ctrl_pins[] = {
3182 	/* SPCLK, SSL */
3183 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3184 };
3185 static const unsigned int qspi_ctrl_mux[] = {
3186 	SPCLK_MARK, SSL_MARK,
3187 };
3188 static const unsigned int qspi_data2_pins[] = {
3189 	/* MOSI_IO0, MISO_IO1 */
3190 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3191 };
3192 static const unsigned int qspi_data2_mux[] = {
3193 	MOSI_IO0_MARK, MISO_IO1_MARK,
3194 };
3195 static const unsigned int qspi_data4_pins[] = {
3196 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
3197 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3198 	RCAR_GP_PIN(1, 8),
3199 };
3200 static const unsigned int qspi_data4_mux[] = {
3201 	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3202 };
3203 
3204 static const unsigned int qspi_ctrl_b_pins[] = {
3205 	/* SPCLK, SSL */
3206 	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3207 };
3208 static const unsigned int qspi_ctrl_b_mux[] = {
3209 	SPCLK_B_MARK, SSL_B_MARK,
3210 };
3211 static const unsigned int qspi_data2_b_pins[] = {
3212 	/* MOSI_IO0, MISO_IO1 */
3213 	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3214 };
3215 static const unsigned int qspi_data2_b_mux[] = {
3216 	MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3217 };
3218 static const unsigned int qspi_data4_b_pins[] = {
3219 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
3220 	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3221 	RCAR_GP_PIN(6, 4),
3222 };
3223 static const unsigned int qspi_data4_b_mux[] = {
3224 	SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3225 	IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
3226 };
3227 /* - SCIF0 ------------------------------------------------------------------ */
3228 static const unsigned int scif0_data_pins[] = {
3229 	/* RX, TX */
3230 	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3231 };
3232 static const unsigned int scif0_data_mux[] = {
3233 	RX0_MARK, TX0_MARK,
3234 };
3235 static const unsigned int scif0_data_b_pins[] = {
3236 	/* RX, TX */
3237 	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3238 };
3239 static const unsigned int scif0_data_b_mux[] = {
3240 	RX0_B_MARK, TX0_B_MARK,
3241 };
3242 static const unsigned int scif0_data_c_pins[] = {
3243 	/* RX, TX */
3244 	RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3245 };
3246 static const unsigned int scif0_data_c_mux[] = {
3247 	RX0_C_MARK, TX0_C_MARK,
3248 };
3249 static const unsigned int scif0_data_d_pins[] = {
3250 	/* RX, TX */
3251 	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3252 };
3253 static const unsigned int scif0_data_d_mux[] = {
3254 	RX0_D_MARK, TX0_D_MARK,
3255 };
3256 static const unsigned int scif0_data_e_pins[] = {
3257 	/* RX, TX */
3258 	RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3259 };
3260 static const unsigned int scif0_data_e_mux[] = {
3261 	RX0_E_MARK, TX0_E_MARK,
3262 };
3263 /* - SCIF1 ------------------------------------------------------------------ */
3264 static const unsigned int scif1_data_pins[] = {
3265 	/* RX, TX */
3266 	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3267 };
3268 static const unsigned int scif1_data_mux[] = {
3269 	RX1_MARK, TX1_MARK,
3270 };
3271 static const unsigned int scif1_data_b_pins[] = {
3272 	/* RX, TX */
3273 	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3274 };
3275 static const unsigned int scif1_data_b_mux[] = {
3276 	RX1_B_MARK, TX1_B_MARK,
3277 };
3278 static const unsigned int scif1_clk_b_pins[] = {
3279 	/* SCK */
3280 	RCAR_GP_PIN(3, 10),
3281 };
3282 static const unsigned int scif1_clk_b_mux[] = {
3283 	SCIF1_SCK_B_MARK,
3284 };
3285 static const unsigned int scif1_data_c_pins[] = {
3286 	/* RX, TX */
3287 	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3288 };
3289 static const unsigned int scif1_data_c_mux[] = {
3290 	RX1_C_MARK, TX1_C_MARK,
3291 };
3292 static const unsigned int scif1_data_d_pins[] = {
3293 	/* RX, TX */
3294 	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3295 };
3296 static const unsigned int scif1_data_d_mux[] = {
3297 	RX1_D_MARK, TX1_D_MARK,
3298 };
3299 /* - SCIF2 ------------------------------------------------------------------ */
3300 static const unsigned int scif2_data_pins[] = {
3301 	/* RX, TX */
3302 	RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3303 };
3304 static const unsigned int scif2_data_mux[] = {
3305 	RX2_MARK, TX2_MARK,
3306 };
3307 static const unsigned int scif2_data_b_pins[] = {
3308 	/* RX, TX */
3309 	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3310 };
3311 static const unsigned int scif2_data_b_mux[] = {
3312 	RX2_B_MARK, TX2_B_MARK,
3313 };
3314 static const unsigned int scif2_clk_b_pins[] = {
3315 	/* SCK */
3316 	RCAR_GP_PIN(3, 18),
3317 };
3318 static const unsigned int scif2_clk_b_mux[] = {
3319 	SCIF2_SCK_B_MARK,
3320 };
3321 static const unsigned int scif2_data_c_pins[] = {
3322 	/* RX, TX */
3323 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3324 };
3325 static const unsigned int scif2_data_c_mux[] = {
3326 	RX2_C_MARK, TX2_C_MARK,
3327 };
3328 static const unsigned int scif2_data_e_pins[] = {
3329 	/* RX, TX */
3330 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3331 };
3332 static const unsigned int scif2_data_e_mux[] = {
3333 	RX2_E_MARK, TX2_E_MARK,
3334 };
3335 /* - SCIF3 ------------------------------------------------------------------ */
3336 static const unsigned int scif3_data_pins[] = {
3337 	/* RX, TX */
3338 	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3339 };
3340 static const unsigned int scif3_data_mux[] = {
3341 	RX3_MARK, TX3_MARK,
3342 };
3343 static const unsigned int scif3_clk_pins[] = {
3344 	/* SCK */
3345 	RCAR_GP_PIN(3, 23),
3346 };
3347 static const unsigned int scif3_clk_mux[] = {
3348 	SCIF3_SCK_MARK,
3349 };
3350 static const unsigned int scif3_data_b_pins[] = {
3351 	/* RX, TX */
3352 	RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3353 };
3354 static const unsigned int scif3_data_b_mux[] = {
3355 	RX3_B_MARK, TX3_B_MARK,
3356 };
3357 static const unsigned int scif3_clk_b_pins[] = {
3358 	/* SCK */
3359 	RCAR_GP_PIN(4, 8),
3360 };
3361 static const unsigned int scif3_clk_b_mux[] = {
3362 	SCIF3_SCK_B_MARK,
3363 };
3364 static const unsigned int scif3_data_c_pins[] = {
3365 	/* RX, TX */
3366 	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3367 };
3368 static const unsigned int scif3_data_c_mux[] = {
3369 	RX3_C_MARK, TX3_C_MARK,
3370 };
3371 static const unsigned int scif3_data_d_pins[] = {
3372 	/* RX, TX */
3373 	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3374 };
3375 static const unsigned int scif3_data_d_mux[] = {
3376 	RX3_D_MARK, TX3_D_MARK,
3377 };
3378 /* - SCIF4 ------------------------------------------------------------------ */
3379 static const unsigned int scif4_data_pins[] = {
3380 	/* RX, TX */
3381 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3382 };
3383 static const unsigned int scif4_data_mux[] = {
3384 	RX4_MARK, TX4_MARK,
3385 };
3386 static const unsigned int scif4_data_b_pins[] = {
3387 	/* RX, TX */
3388 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3389 };
3390 static const unsigned int scif4_data_b_mux[] = {
3391 	RX4_B_MARK, TX4_B_MARK,
3392 };
3393 static const unsigned int scif4_data_c_pins[] = {
3394 	/* RX, TX */
3395 	RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3396 };
3397 static const unsigned int scif4_data_c_mux[] = {
3398 	RX4_C_MARK, TX4_C_MARK,
3399 };
3400 /* - SCIF5 ------------------------------------------------------------------ */
3401 static const unsigned int scif5_data_pins[] = {
3402 	/* RX, TX */
3403 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3404 };
3405 static const unsigned int scif5_data_mux[] = {
3406 	RX5_MARK, TX5_MARK,
3407 };
3408 static const unsigned int scif5_data_b_pins[] = {
3409 	/* RX, TX */
3410 	RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3411 };
3412 static const unsigned int scif5_data_b_mux[] = {
3413 	RX5_B_MARK, TX5_B_MARK,
3414 };
3415 /* - SCIFA0 ----------------------------------------------------------------- */
3416 static const unsigned int scifa0_data_pins[] = {
3417 	/* RXD, TXD */
3418 	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3419 };
3420 static const unsigned int scifa0_data_mux[] = {
3421 	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3422 };
3423 static const unsigned int scifa0_data_b_pins[] = {
3424 	/* RXD, TXD */
3425 	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3426 };
3427 static const unsigned int scifa0_data_b_mux[] = {
3428 	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3429 };
3430 /* - SCIFA1 ----------------------------------------------------------------- */
3431 static const unsigned int scifa1_data_pins[] = {
3432 	/* RXD, TXD */
3433 	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3434 };
3435 static const unsigned int scifa1_data_mux[] = {
3436 	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3437 };
3438 static const unsigned int scifa1_clk_pins[] = {
3439 	/* SCK */
3440 	RCAR_GP_PIN(3, 10),
3441 };
3442 static const unsigned int scifa1_clk_mux[] = {
3443 	SCIFA1_SCK_MARK,
3444 };
3445 static const unsigned int scifa1_data_b_pins[] = {
3446 	/* RXD, TXD */
3447 	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3448 };
3449 static const unsigned int scifa1_data_b_mux[] = {
3450 	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3451 };
3452 static const unsigned int scifa1_clk_b_pins[] = {
3453 	/* SCK */
3454 	RCAR_GP_PIN(1, 0),
3455 };
3456 static const unsigned int scifa1_clk_b_mux[] = {
3457 	SCIFA1_SCK_B_MARK,
3458 };
3459 static const unsigned int scifa1_data_c_pins[] = {
3460 	/* RXD, TXD */
3461 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3462 };
3463 static const unsigned int scifa1_data_c_mux[] = {
3464 	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3465 };
3466 /* - SCIFA2 ----------------------------------------------------------------- */
3467 static const unsigned int scifa2_data_pins[] = {
3468 	/* RXD, TXD */
3469 	RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3470 };
3471 static const unsigned int scifa2_data_mux[] = {
3472 	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3473 };
3474 static const unsigned int scifa2_clk_pins[] = {
3475 	/* SCK */
3476 	RCAR_GP_PIN(3, 18),
3477 };
3478 static const unsigned int scifa2_clk_mux[] = {
3479 	SCIFA2_SCK_MARK,
3480 };
3481 static const unsigned int scifa2_data_b_pins[] = {
3482 	/* RXD, TXD */
3483 	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3484 };
3485 static const unsigned int scifa2_data_b_mux[] = {
3486 	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3487 };
3488 /* - SCIFA3 ----------------------------------------------------------------- */
3489 static const unsigned int scifa3_data_pins[] = {
3490 	/* RXD, TXD */
3491 	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3492 };
3493 static const unsigned int scifa3_data_mux[] = {
3494 	SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3495 };
3496 static const unsigned int scifa3_clk_pins[] = {
3497 	/* SCK */
3498 	RCAR_GP_PIN(3, 23),
3499 };
3500 static const unsigned int scifa3_clk_mux[] = {
3501 	SCIFA3_SCK_MARK,
3502 };
3503 static const unsigned int scifa3_data_b_pins[] = {
3504 	/* RXD, TXD */
3505 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3506 };
3507 static const unsigned int scifa3_data_b_mux[] = {
3508 	SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3509 };
3510 static const unsigned int scifa3_clk_b_pins[] = {
3511 	/* SCK */
3512 	RCAR_GP_PIN(4, 8),
3513 };
3514 static const unsigned int scifa3_clk_b_mux[] = {
3515 	SCIFA3_SCK_B_MARK,
3516 };
3517 static const unsigned int scifa3_data_c_pins[] = {
3518 	/* RXD, TXD */
3519 	RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3520 };
3521 static const unsigned int scifa3_data_c_mux[] = {
3522 	SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3523 };
3524 static const unsigned int scifa3_clk_c_pins[] = {
3525 	/* SCK */
3526 	RCAR_GP_PIN(7, 22),
3527 };
3528 static const unsigned int scifa3_clk_c_mux[] = {
3529 	SCIFA3_SCK_C_MARK,
3530 };
3531 /* - SCIFA4 ----------------------------------------------------------------- */
3532 static const unsigned int scifa4_data_pins[] = {
3533 	/* RXD, TXD */
3534 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3535 };
3536 static const unsigned int scifa4_data_mux[] = {
3537 	SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3538 };
3539 static const unsigned int scifa4_data_b_pins[] = {
3540 	/* RXD, TXD */
3541 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3542 };
3543 static const unsigned int scifa4_data_b_mux[] = {
3544 	SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3545 };
3546 static const unsigned int scifa4_data_c_pins[] = {
3547 	/* RXD, TXD */
3548 	RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3549 };
3550 static const unsigned int scifa4_data_c_mux[] = {
3551 	SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3552 };
3553 /* - SCIFA5 ----------------------------------------------------------------- */
3554 static const unsigned int scifa5_data_pins[] = {
3555 	/* RXD, TXD */
3556 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3557 };
3558 static const unsigned int scifa5_data_mux[] = {
3559 	SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3560 };
3561 static const unsigned int scifa5_data_b_pins[] = {
3562 	/* RXD, TXD */
3563 	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3564 };
3565 static const unsigned int scifa5_data_b_mux[] = {
3566 	SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3567 };
3568 static const unsigned int scifa5_data_c_pins[] = {
3569 	/* RXD, TXD */
3570 	RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3571 };
3572 static const unsigned int scifa5_data_c_mux[] = {
3573 	SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3574 };
3575 /* - SCIFB0 ----------------------------------------------------------------- */
3576 static const unsigned int scifb0_data_pins[] = {
3577 	/* RXD, TXD */
3578 	RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3579 };
3580 static const unsigned int scifb0_data_mux[] = {
3581 	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3582 };
3583 static const unsigned int scifb0_clk_pins[] = {
3584 	/* SCK */
3585 	RCAR_GP_PIN(7, 2),
3586 };
3587 static const unsigned int scifb0_clk_mux[] = {
3588 	SCIFB0_SCK_MARK,
3589 };
3590 static const unsigned int scifb0_ctrl_pins[] = {
3591 	/* RTS, CTS */
3592 	RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3593 };
3594 static const unsigned int scifb0_ctrl_mux[] = {
3595 	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3596 };
3597 static const unsigned int scifb0_data_b_pins[] = {
3598 	/* RXD, TXD */
3599 	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3600 };
3601 static const unsigned int scifb0_data_b_mux[] = {
3602 	SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3603 };
3604 static const unsigned int scifb0_clk_b_pins[] = {
3605 	/* SCK */
3606 	RCAR_GP_PIN(5, 31),
3607 };
3608 static const unsigned int scifb0_clk_b_mux[] = {
3609 	SCIFB0_SCK_B_MARK,
3610 };
3611 static const unsigned int scifb0_ctrl_b_pins[] = {
3612 	/* RTS, CTS */
3613 	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3614 };
3615 static const unsigned int scifb0_ctrl_b_mux[] = {
3616 	SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3617 };
3618 static const unsigned int scifb0_data_c_pins[] = {
3619 	/* RXD, TXD */
3620 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3621 };
3622 static const unsigned int scifb0_data_c_mux[] = {
3623 	SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3624 };
3625 static const unsigned int scifb0_clk_c_pins[] = {
3626 	/* SCK */
3627 	RCAR_GP_PIN(2, 30),
3628 };
3629 static const unsigned int scifb0_clk_c_mux[] = {
3630 	SCIFB0_SCK_C_MARK,
3631 };
3632 static const unsigned int scifb0_data_d_pins[] = {
3633 	/* RXD, TXD */
3634 	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3635 };
3636 static const unsigned int scifb0_data_d_mux[] = {
3637 	SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3638 };
3639 static const unsigned int scifb0_clk_d_pins[] = {
3640 	/* SCK */
3641 	RCAR_GP_PIN(4, 17),
3642 };
3643 static const unsigned int scifb0_clk_d_mux[] = {
3644 	SCIFB0_SCK_D_MARK,
3645 };
3646 /* - SCIFB1 ----------------------------------------------------------------- */
3647 static const unsigned int scifb1_data_pins[] = {
3648 	/* RXD, TXD */
3649 	RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3650 };
3651 static const unsigned int scifb1_data_mux[] = {
3652 	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3653 };
3654 static const unsigned int scifb1_clk_pins[] = {
3655 	/* SCK */
3656 	RCAR_GP_PIN(7, 7),
3657 };
3658 static const unsigned int scifb1_clk_mux[] = {
3659 	SCIFB1_SCK_MARK,
3660 };
3661 static const unsigned int scifb1_ctrl_pins[] = {
3662 	/* RTS, CTS */
3663 	RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3664 };
3665 static const unsigned int scifb1_ctrl_mux[] = {
3666 	SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3667 };
3668 static const unsigned int scifb1_data_b_pins[] = {
3669 	/* RXD, TXD */
3670 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3671 };
3672 static const unsigned int scifb1_data_b_mux[] = {
3673 	SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3674 };
3675 static const unsigned int scifb1_clk_b_pins[] = {
3676 	/* SCK */
3677 	RCAR_GP_PIN(1, 3),
3678 };
3679 static const unsigned int scifb1_clk_b_mux[] = {
3680 	SCIFB1_SCK_B_MARK,
3681 };
3682 static const unsigned int scifb1_data_c_pins[] = {
3683 	/* RXD, TXD */
3684 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3685 };
3686 static const unsigned int scifb1_data_c_mux[] = {
3687 	SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3688 };
3689 static const unsigned int scifb1_clk_c_pins[] = {
3690 	/* SCK */
3691 	RCAR_GP_PIN(7, 11),
3692 };
3693 static const unsigned int scifb1_clk_c_mux[] = {
3694 	SCIFB1_SCK_C_MARK,
3695 };
3696 static const unsigned int scifb1_data_d_pins[] = {
3697 	/* RXD, TXD */
3698 	RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3699 };
3700 static const unsigned int scifb1_data_d_mux[] = {
3701 	SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3702 };
3703 /* - SCIFB2 ----------------------------------------------------------------- */
3704 static const unsigned int scifb2_data_pins[] = {
3705 	/* RXD, TXD */
3706 	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3707 };
3708 static const unsigned int scifb2_data_mux[] = {
3709 	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3710 };
3711 static const unsigned int scifb2_clk_pins[] = {
3712 	/* SCK */
3713 	RCAR_GP_PIN(4, 15),
3714 };
3715 static const unsigned int scifb2_clk_mux[] = {
3716 	SCIFB2_SCK_MARK,
3717 };
3718 static const unsigned int scifb2_ctrl_pins[] = {
3719 	/* RTS, CTS */
3720 	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3721 };
3722 static const unsigned int scifb2_ctrl_mux[] = {
3723 	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3724 };
3725 static const unsigned int scifb2_data_b_pins[] = {
3726 	/* RXD, TXD */
3727 	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3728 };
3729 static const unsigned int scifb2_data_b_mux[] = {
3730 	SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3731 };
3732 static const unsigned int scifb2_clk_b_pins[] = {
3733 	/* SCK */
3734 	RCAR_GP_PIN(5, 31),
3735 };
3736 static const unsigned int scifb2_clk_b_mux[] = {
3737 	SCIFB2_SCK_B_MARK,
3738 };
3739 static const unsigned int scifb2_ctrl_b_pins[] = {
3740 	/* RTS, CTS */
3741 	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3742 };
3743 static const unsigned int scifb2_ctrl_b_mux[] = {
3744 	SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3745 };
3746 static const unsigned int scifb2_data_c_pins[] = {
3747 	/* RXD, TXD */
3748 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3749 };
3750 static const unsigned int scifb2_data_c_mux[] = {
3751 	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3752 };
3753 static const unsigned int scifb2_clk_c_pins[] = {
3754 	/* SCK */
3755 	RCAR_GP_PIN(5, 27),
3756 };
3757 static const unsigned int scifb2_clk_c_mux[] = {
3758 	SCIFB2_SCK_C_MARK,
3759 };
3760 static const unsigned int scifb2_data_d_pins[] = {
3761 	/* RXD, TXD */
3762 	RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3763 };
3764 static const unsigned int scifb2_data_d_mux[] = {
3765 	SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3766 };
3767 
3768 /* - SCIF Clock ------------------------------------------------------------- */
3769 static const unsigned int scif_clk_pins[] = {
3770 	/* SCIF_CLK */
3771 	RCAR_GP_PIN(2, 29),
3772 };
3773 static const unsigned int scif_clk_mux[] = {
3774 	SCIF_CLK_MARK,
3775 };
3776 static const unsigned int scif_clk_b_pins[] = {
3777 	/* SCIF_CLK */
3778 	RCAR_GP_PIN(7, 19),
3779 };
3780 static const unsigned int scif_clk_b_mux[] = {
3781 	SCIF_CLK_B_MARK,
3782 };
3783 
3784 /* - SDHI0 ------------------------------------------------------------------ */
3785 static const unsigned int sdhi0_data1_pins[] = {
3786 	/* D0 */
3787 	RCAR_GP_PIN(6, 2),
3788 };
3789 static const unsigned int sdhi0_data1_mux[] = {
3790 	SD0_DATA0_MARK,
3791 };
3792 static const unsigned int sdhi0_data4_pins[] = {
3793 	/* D[0:3] */
3794 	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3795 	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3796 };
3797 static const unsigned int sdhi0_data4_mux[] = {
3798 	SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3799 };
3800 static const unsigned int sdhi0_ctrl_pins[] = {
3801 	/* CLK, CMD */
3802 	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3803 };
3804 static const unsigned int sdhi0_ctrl_mux[] = {
3805 	SD0_CLK_MARK, SD0_CMD_MARK,
3806 };
3807 static const unsigned int sdhi0_cd_pins[] = {
3808 	/* CD */
3809 	RCAR_GP_PIN(6, 6),
3810 };
3811 static const unsigned int sdhi0_cd_mux[] = {
3812 	SD0_CD_MARK,
3813 };
3814 static const unsigned int sdhi0_wp_pins[] = {
3815 	/* WP */
3816 	RCAR_GP_PIN(6, 7),
3817 };
3818 static const unsigned int sdhi0_wp_mux[] = {
3819 	SD0_WP_MARK,
3820 };
3821 /* - SDHI1 ------------------------------------------------------------------ */
3822 static const unsigned int sdhi1_data1_pins[] = {
3823 	/* D0 */
3824 	RCAR_GP_PIN(6, 10),
3825 };
3826 static const unsigned int sdhi1_data1_mux[] = {
3827 	SD1_DATA0_MARK,
3828 };
3829 static const unsigned int sdhi1_data4_pins[] = {
3830 	/* D[0:3] */
3831 	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3832 	RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3833 };
3834 static const unsigned int sdhi1_data4_mux[] = {
3835 	SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3836 };
3837 static const unsigned int sdhi1_ctrl_pins[] = {
3838 	/* CLK, CMD */
3839 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3840 };
3841 static const unsigned int sdhi1_ctrl_mux[] = {
3842 	SD1_CLK_MARK, SD1_CMD_MARK,
3843 };
3844 static const unsigned int sdhi1_cd_pins[] = {
3845 	/* CD */
3846 	RCAR_GP_PIN(6, 14),
3847 };
3848 static const unsigned int sdhi1_cd_mux[] = {
3849 	SD1_CD_MARK,
3850 };
3851 static const unsigned int sdhi1_wp_pins[] = {
3852 	/* WP */
3853 	RCAR_GP_PIN(6, 15),
3854 };
3855 static const unsigned int sdhi1_wp_mux[] = {
3856 	SD1_WP_MARK,
3857 };
3858 /* - SDHI2 ------------------------------------------------------------------ */
3859 static const unsigned int sdhi2_data1_pins[] = {
3860 	/* D0 */
3861 	RCAR_GP_PIN(6, 18),
3862 };
3863 static const unsigned int sdhi2_data1_mux[] = {
3864 	SD2_DATA0_MARK,
3865 };
3866 static const unsigned int sdhi2_data4_pins[] = {
3867 	/* D[0:3] */
3868 	RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3869 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3870 };
3871 static const unsigned int sdhi2_data4_mux[] = {
3872 	SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3873 };
3874 static const unsigned int sdhi2_ctrl_pins[] = {
3875 	/* CLK, CMD */
3876 	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3877 };
3878 static const unsigned int sdhi2_ctrl_mux[] = {
3879 	SD2_CLK_MARK, SD2_CMD_MARK,
3880 };
3881 static const unsigned int sdhi2_cd_pins[] = {
3882 	/* CD */
3883 	RCAR_GP_PIN(6, 22),
3884 };
3885 static const unsigned int sdhi2_cd_mux[] = {
3886 	SD2_CD_MARK,
3887 };
3888 static const unsigned int sdhi2_wp_pins[] = {
3889 	/* WP */
3890 	RCAR_GP_PIN(6, 23),
3891 };
3892 static const unsigned int sdhi2_wp_mux[] = {
3893 	SD2_WP_MARK,
3894 };
3895 
3896 /* - SSI -------------------------------------------------------------------- */
3897 static const unsigned int ssi0_data_pins[] = {
3898 	/* SDATA */
3899 	RCAR_GP_PIN(2, 2),
3900 };
3901 
3902 static const unsigned int ssi0_data_mux[] = {
3903 	SSI_SDATA0_MARK,
3904 };
3905 
3906 static const unsigned int ssi0_data_b_pins[] = {
3907 	/* SDATA */
3908 	RCAR_GP_PIN(3, 4),
3909 };
3910 
3911 static const unsigned int ssi0_data_b_mux[] = {
3912 	SSI_SDATA0_B_MARK,
3913 };
3914 
3915 static const unsigned int ssi0129_ctrl_pins[] = {
3916 	/* SCK, WS */
3917 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3918 };
3919 
3920 static const unsigned int ssi0129_ctrl_mux[] = {
3921 	SSI_SCK0129_MARK, SSI_WS0129_MARK,
3922 };
3923 
3924 static const unsigned int ssi0129_ctrl_b_pins[] = {
3925 	/* SCK, WS */
3926 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3927 };
3928 
3929 static const unsigned int ssi0129_ctrl_b_mux[] = {
3930 	SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3931 };
3932 
3933 static const unsigned int ssi1_data_pins[] = {
3934 	/* SDATA */
3935 	RCAR_GP_PIN(2, 5),
3936 };
3937 
3938 static const unsigned int ssi1_data_mux[] = {
3939 	SSI_SDATA1_MARK,
3940 };
3941 
3942 static const unsigned int ssi1_data_b_pins[] = {
3943 	/* SDATA */
3944 	RCAR_GP_PIN(3, 7),
3945 };
3946 
3947 static const unsigned int ssi1_data_b_mux[] = {
3948 	SSI_SDATA1_B_MARK,
3949 };
3950 
3951 static const unsigned int ssi1_ctrl_pins[] = {
3952 	/* SCK, WS */
3953 	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3954 };
3955 
3956 static const unsigned int ssi1_ctrl_mux[] = {
3957 	SSI_SCK1_MARK, SSI_WS1_MARK,
3958 };
3959 
3960 static const unsigned int ssi1_ctrl_b_pins[] = {
3961 	/* SCK, WS */
3962 	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3963 };
3964 
3965 static const unsigned int ssi1_ctrl_b_mux[] = {
3966 	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3967 };
3968 
3969 static const unsigned int ssi2_data_pins[] = {
3970 	/* SDATA */
3971 	RCAR_GP_PIN(2, 8),
3972 };
3973 
3974 static const unsigned int ssi2_data_mux[] = {
3975 	SSI_SDATA2_MARK,
3976 };
3977 
3978 static const unsigned int ssi2_ctrl_pins[] = {
3979 	/* SCK, WS */
3980 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3981 };
3982 
3983 static const unsigned int ssi2_ctrl_mux[] = {
3984 	SSI_SCK2_MARK, SSI_WS2_MARK,
3985 };
3986 
3987 static const unsigned int ssi3_data_pins[] = {
3988 	/* SDATA */
3989 	RCAR_GP_PIN(2, 11),
3990 };
3991 
3992 static const unsigned int ssi3_data_mux[] = {
3993 	SSI_SDATA3_MARK,
3994 };
3995 
3996 static const unsigned int ssi34_ctrl_pins[] = {
3997 	/* SCK, WS */
3998 	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3999 };
4000 
4001 static const unsigned int ssi34_ctrl_mux[] = {
4002 	SSI_SCK34_MARK, SSI_WS34_MARK,
4003 };
4004 
4005 static const unsigned int ssi4_data_pins[] = {
4006 	/* SDATA */
4007 	RCAR_GP_PIN(2, 14),
4008 };
4009 
4010 static const unsigned int ssi4_data_mux[] = {
4011 	SSI_SDATA4_MARK,
4012 };
4013 
4014 static const unsigned int ssi4_ctrl_pins[] = {
4015 	/* SCK, WS */
4016 	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
4017 };
4018 
4019 static const unsigned int ssi4_ctrl_mux[] = {
4020 	SSI_SCK4_MARK, SSI_WS4_MARK,
4021 };
4022 
4023 static const unsigned int ssi5_data_pins[] = {
4024 	/* SDATA */
4025 	RCAR_GP_PIN(2, 17),
4026 };
4027 
4028 static const unsigned int ssi5_data_mux[] = {
4029 	SSI_SDATA5_MARK,
4030 };
4031 
4032 static const unsigned int ssi5_ctrl_pins[] = {
4033 	/* SCK, WS */
4034 	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4035 };
4036 
4037 static const unsigned int ssi5_ctrl_mux[] = {
4038 	SSI_SCK5_MARK, SSI_WS5_MARK,
4039 };
4040 
4041 static const unsigned int ssi6_data_pins[] = {
4042 	/* SDATA */
4043 	RCAR_GP_PIN(2, 20),
4044 };
4045 
4046 static const unsigned int ssi6_data_mux[] = {
4047 	SSI_SDATA6_MARK,
4048 };
4049 
4050 static const unsigned int ssi6_ctrl_pins[] = {
4051 	/* SCK, WS */
4052 	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
4053 };
4054 
4055 static const unsigned int ssi6_ctrl_mux[] = {
4056 	SSI_SCK6_MARK, SSI_WS6_MARK,
4057 };
4058 
4059 static const unsigned int ssi7_data_pins[] = {
4060 	/* SDATA */
4061 	RCAR_GP_PIN(2, 23),
4062 };
4063 
4064 static const unsigned int ssi7_data_mux[] = {
4065 	SSI_SDATA7_MARK,
4066 };
4067 
4068 static const unsigned int ssi7_data_b_pins[] = {
4069 	/* SDATA */
4070 	RCAR_GP_PIN(3, 12),
4071 };
4072 
4073 static const unsigned int ssi7_data_b_mux[] = {
4074 	SSI_SDATA7_B_MARK,
4075 };
4076 
4077 static const unsigned int ssi78_ctrl_pins[] = {
4078 	/* SCK, WS */
4079 	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
4080 };
4081 
4082 static const unsigned int ssi78_ctrl_mux[] = {
4083 	SSI_SCK78_MARK, SSI_WS78_MARK,
4084 };
4085 
4086 static const unsigned int ssi78_ctrl_b_pins[] = {
4087 	/* SCK, WS */
4088 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4089 };
4090 
4091 static const unsigned int ssi78_ctrl_b_mux[] = {
4092 	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4093 };
4094 
4095 static const unsigned int ssi8_data_pins[] = {
4096 	/* SDATA */
4097 	RCAR_GP_PIN(2, 24),
4098 };
4099 
4100 static const unsigned int ssi8_data_mux[] = {
4101 	SSI_SDATA8_MARK,
4102 };
4103 
4104 static const unsigned int ssi8_data_b_pins[] = {
4105 	/* SDATA */
4106 	RCAR_GP_PIN(3, 13),
4107 };
4108 
4109 static const unsigned int ssi8_data_b_mux[] = {
4110 	SSI_SDATA8_B_MARK,
4111 };
4112 
4113 static const unsigned int ssi9_data_pins[] = {
4114 	/* SDATA */
4115 	RCAR_GP_PIN(2, 27),
4116 };
4117 
4118 static const unsigned int ssi9_data_mux[] = {
4119 	SSI_SDATA9_MARK,
4120 };
4121 
4122 static const unsigned int ssi9_data_b_pins[] = {
4123 	/* SDATA */
4124 	RCAR_GP_PIN(3, 18),
4125 };
4126 
4127 static const unsigned int ssi9_data_b_mux[] = {
4128 	SSI_SDATA9_B_MARK,
4129 };
4130 
4131 static const unsigned int ssi9_ctrl_pins[] = {
4132 	/* SCK, WS */
4133 	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4134 };
4135 
4136 static const unsigned int ssi9_ctrl_mux[] = {
4137 	SSI_SCK9_MARK, SSI_WS9_MARK,
4138 };
4139 
4140 static const unsigned int ssi9_ctrl_b_pins[] = {
4141 	/* SCK, WS */
4142 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4143 };
4144 
4145 static const unsigned int ssi9_ctrl_b_mux[] = {
4146 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4147 };
4148 
4149 /* - USB0 ------------------------------------------------------------------- */
4150 static const unsigned int usb0_pins[] = {
4151 	RCAR_GP_PIN(7, 23), /* PWEN */
4152 	RCAR_GP_PIN(7, 24), /* OVC */
4153 };
4154 static const unsigned int usb0_mux[] = {
4155 	USB0_PWEN_MARK,
4156 	USB0_OVC_MARK,
4157 };
4158 /* - USB1 ------------------------------------------------------------------- */
4159 static const unsigned int usb1_pins[] = {
4160 	RCAR_GP_PIN(7, 25), /* PWEN */
4161 	RCAR_GP_PIN(6, 30), /* OVC */
4162 };
4163 static const unsigned int usb1_mux[] = {
4164 	USB1_PWEN_MARK,
4165 	USB1_OVC_MARK,
4166 };
4167 /* - VIN0 ------------------------------------------------------------------- */
4168 static const union vin_data vin0_data_pins = {
4169 	.data24 = {
4170 		/* B */
4171 		RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4172 		RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4173 		RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4174 		RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4175 		/* G */
4176 		RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4177 		RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4178 		RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4179 		RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4180 		/* R */
4181 		RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4182 		RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4183 		RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4184 		RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4185 	},
4186 };
4187 static const union vin_data vin0_data_mux = {
4188 	.data24 = {
4189 		/* B */
4190 		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4191 		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4192 		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4193 		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4194 		/* G */
4195 		VI0_G0_MARK, VI0_G1_MARK,
4196 		VI0_G2_MARK, VI0_G3_MARK,
4197 		VI0_G4_MARK, VI0_G5_MARK,
4198 		VI0_G6_MARK, VI0_G7_MARK,
4199 		/* R */
4200 		VI0_R0_MARK, VI0_R1_MARK,
4201 		VI0_R2_MARK, VI0_R3_MARK,
4202 		VI0_R4_MARK, VI0_R5_MARK,
4203 		VI0_R6_MARK, VI0_R7_MARK,
4204 	},
4205 };
4206 static const unsigned int vin0_data18_pins[] = {
4207 	/* B */
4208 	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4209 	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4210 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4211 	/* G */
4212 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4213 	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4214 	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4215 	/* R */
4216 	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4217 	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4218 	RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4219 };
4220 static const unsigned int vin0_data18_mux[] = {
4221 	/* B */
4222 	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4223 	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4224 	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4225 	/* G */
4226 	VI0_G2_MARK, VI0_G3_MARK,
4227 	VI0_G4_MARK, VI0_G5_MARK,
4228 	VI0_G6_MARK, VI0_G7_MARK,
4229 	/* R */
4230 	VI0_R2_MARK, VI0_R3_MARK,
4231 	VI0_R4_MARK, VI0_R5_MARK,
4232 	VI0_R6_MARK, VI0_R7_MARK,
4233 };
4234 static const unsigned int vin0_sync_pins[] = {
4235 	RCAR_GP_PIN(4, 3), /* HSYNC */
4236 	RCAR_GP_PIN(4, 4), /* VSYNC */
4237 };
4238 static const unsigned int vin0_sync_mux[] = {
4239 	VI0_HSYNC_N_MARK,
4240 	VI0_VSYNC_N_MARK,
4241 };
4242 static const unsigned int vin0_field_pins[] = {
4243 	RCAR_GP_PIN(4, 2),
4244 };
4245 static const unsigned int vin0_field_mux[] = {
4246 	VI0_FIELD_MARK,
4247 };
4248 static const unsigned int vin0_clkenb_pins[] = {
4249 	RCAR_GP_PIN(4, 1),
4250 };
4251 static const unsigned int vin0_clkenb_mux[] = {
4252 	VI0_CLKENB_MARK,
4253 };
4254 static const unsigned int vin0_clk_pins[] = {
4255 	RCAR_GP_PIN(4, 0),
4256 };
4257 static const unsigned int vin0_clk_mux[] = {
4258 	VI0_CLK_MARK,
4259 };
4260 /* - VIN1 ----------------------------------------------------------------- */
4261 static const unsigned int vin1_data8_pins[] = {
4262 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4263 	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4264 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4265 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4266 };
4267 static const unsigned int vin1_data8_mux[] = {
4268 	VI1_DATA0_MARK, VI1_DATA1_MARK,
4269 	VI1_DATA2_MARK, VI1_DATA3_MARK,
4270 	VI1_DATA4_MARK, VI1_DATA5_MARK,
4271 	VI1_DATA6_MARK, VI1_DATA7_MARK,
4272 };
4273 static const unsigned int vin1_sync_pins[] = {
4274 	RCAR_GP_PIN(5, 0), /* HSYNC */
4275 	RCAR_GP_PIN(5, 1), /* VSYNC */
4276 };
4277 static const unsigned int vin1_sync_mux[] = {
4278 	VI1_HSYNC_N_MARK,
4279 	VI1_VSYNC_N_MARK,
4280 };
4281 static const unsigned int vin1_field_pins[] = {
4282 	RCAR_GP_PIN(5, 3),
4283 };
4284 static const unsigned int vin1_field_mux[] = {
4285 	VI1_FIELD_MARK,
4286 };
4287 static const unsigned int vin1_clkenb_pins[] = {
4288 	RCAR_GP_PIN(5, 2),
4289 };
4290 static const unsigned int vin1_clkenb_mux[] = {
4291 	VI1_CLKENB_MARK,
4292 };
4293 static const unsigned int vin1_clk_pins[] = {
4294 	RCAR_GP_PIN(5, 4),
4295 };
4296 static const unsigned int vin1_clk_mux[] = {
4297 	VI1_CLK_MARK,
4298 };
4299 static const union vin_data vin1_b_data_pins = {
4300 	.data24 = {
4301 		/* B */
4302 		RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4303 		RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4304 		RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4305 		RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4306 		/* G */
4307 		RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4308 		RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4309 		RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4310 		RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4311 		/* R */
4312 		RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4313 		RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4314 		RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4315 		RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4316 	},
4317 };
4318 static const union vin_data vin1_b_data_mux = {
4319 	.data24 = {
4320 		/* B */
4321 		VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4322 		VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4323 		VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4324 		VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4325 		/* G */
4326 		VI1_G0_B_MARK, VI1_G1_B_MARK,
4327 		VI1_G2_B_MARK, VI1_G3_B_MARK,
4328 		VI1_G4_B_MARK, VI1_G5_B_MARK,
4329 		VI1_G6_B_MARK, VI1_G7_B_MARK,
4330 		/* R */
4331 		VI1_R0_B_MARK, VI1_R1_B_MARK,
4332 		VI1_R2_B_MARK, VI1_R3_B_MARK,
4333 		VI1_R4_B_MARK, VI1_R5_B_MARK,
4334 		VI1_R6_B_MARK, VI1_R7_B_MARK,
4335 	},
4336 };
4337 static const unsigned int vin1_b_data18_pins[] = {
4338 	/* B */
4339 	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4340 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4341 	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4342 	/* G */
4343 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4344 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4345 	RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4346 	/* R */
4347 	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4348 	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4349 	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4350 };
4351 static const unsigned int vin1_b_data18_mux[] = {
4352 	/* B */
4353 	VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4354 	VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4355 	VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4356 	VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4357 	/* G */
4358 	VI1_G0_B_MARK, VI1_G1_B_MARK,
4359 	VI1_G2_B_MARK, VI1_G3_B_MARK,
4360 	VI1_G4_B_MARK, VI1_G5_B_MARK,
4361 	VI1_G6_B_MARK, VI1_G7_B_MARK,
4362 	/* R */
4363 	VI1_R0_B_MARK, VI1_R1_B_MARK,
4364 	VI1_R2_B_MARK, VI1_R3_B_MARK,
4365 	VI1_R4_B_MARK, VI1_R5_B_MARK,
4366 	VI1_R6_B_MARK, VI1_R7_B_MARK,
4367 };
4368 static const unsigned int vin1_b_sync_pins[] = {
4369 	RCAR_GP_PIN(3, 17), /* HSYNC */
4370 	RCAR_GP_PIN(3, 18), /* VSYNC */
4371 };
4372 static const unsigned int vin1_b_sync_mux[] = {
4373 	VI1_HSYNC_N_B_MARK,
4374 	VI1_VSYNC_N_B_MARK,
4375 };
4376 static const unsigned int vin1_b_field_pins[] = {
4377 	RCAR_GP_PIN(3, 20),
4378 };
4379 static const unsigned int vin1_b_field_mux[] = {
4380 	VI1_FIELD_B_MARK,
4381 };
4382 static const unsigned int vin1_b_clkenb_pins[] = {
4383 	RCAR_GP_PIN(3, 19),
4384 };
4385 static const unsigned int vin1_b_clkenb_mux[] = {
4386 	VI1_CLKENB_B_MARK,
4387 };
4388 static const unsigned int vin1_b_clk_pins[] = {
4389 	RCAR_GP_PIN(3, 16),
4390 };
4391 static const unsigned int vin1_b_clk_mux[] = {
4392 	VI1_CLK_B_MARK,
4393 };
4394 /* - VIN2 ----------------------------------------------------------------- */
4395 static const unsigned int vin2_data8_pins[] = {
4396 	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4397 	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4398 	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4399 	RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4400 };
4401 static const unsigned int vin2_data8_mux[] = {
4402 	VI2_DATA0_MARK, VI2_DATA1_MARK,
4403 	VI2_DATA2_MARK, VI2_DATA3_MARK,
4404 	VI2_DATA4_MARK, VI2_DATA5_MARK,
4405 	VI2_DATA6_MARK, VI2_DATA7_MARK,
4406 };
4407 static const unsigned int vin2_sync_pins[] = {
4408 	RCAR_GP_PIN(4, 15), /* HSYNC */
4409 	RCAR_GP_PIN(4, 16), /* VSYNC */
4410 };
4411 static const unsigned int vin2_sync_mux[] = {
4412 	VI2_HSYNC_N_MARK,
4413 	VI2_VSYNC_N_MARK,
4414 };
4415 static const unsigned int vin2_field_pins[] = {
4416 	RCAR_GP_PIN(4, 18),
4417 };
4418 static const unsigned int vin2_field_mux[] = {
4419 	VI2_FIELD_MARK,
4420 };
4421 static const unsigned int vin2_clkenb_pins[] = {
4422 	RCAR_GP_PIN(4, 17),
4423 };
4424 static const unsigned int vin2_clkenb_mux[] = {
4425 	VI2_CLKENB_MARK,
4426 };
4427 static const unsigned int vin2_clk_pins[] = {
4428 	RCAR_GP_PIN(4, 19),
4429 };
4430 static const unsigned int vin2_clk_mux[] = {
4431 	VI2_CLK_MARK,
4432 };
4433 
4434 static const struct {
4435 	struct sh_pfc_pin_group common[342];
4436 	struct sh_pfc_pin_group r8a779x[9];
4437 } pinmux_groups = {
4438 	.common = {
4439 		SH_PFC_PIN_GROUP(audio_clk_a),
4440 		SH_PFC_PIN_GROUP(audio_clk_b),
4441 		SH_PFC_PIN_GROUP(audio_clk_b_b),
4442 		SH_PFC_PIN_GROUP(audio_clk_c),
4443 		SH_PFC_PIN_GROUP(audio_clkout),
4444 		SH_PFC_PIN_GROUP(avb_link),
4445 		SH_PFC_PIN_GROUP(avb_magic),
4446 		SH_PFC_PIN_GROUP(avb_phy_int),
4447 		SH_PFC_PIN_GROUP(avb_mdio),
4448 		SH_PFC_PIN_GROUP(avb_mii),
4449 		SH_PFC_PIN_GROUP(avb_gmii),
4450 		SH_PFC_PIN_GROUP(can0_data),
4451 		SH_PFC_PIN_GROUP(can0_data_b),
4452 		SH_PFC_PIN_GROUP(can0_data_c),
4453 		SH_PFC_PIN_GROUP(can0_data_d),
4454 		SH_PFC_PIN_GROUP(can0_data_e),
4455 		SH_PFC_PIN_GROUP(can0_data_f),
4456 		SH_PFC_PIN_GROUP(can1_data),
4457 		SH_PFC_PIN_GROUP(can1_data_b),
4458 		SH_PFC_PIN_GROUP(can1_data_c),
4459 		SH_PFC_PIN_GROUP(can1_data_d),
4460 		SH_PFC_PIN_GROUP(can_clk),
4461 		SH_PFC_PIN_GROUP(can_clk_b),
4462 		SH_PFC_PIN_GROUP(can_clk_c),
4463 		SH_PFC_PIN_GROUP(can_clk_d),
4464 		SH_PFC_PIN_GROUP(du_rgb666),
4465 		SH_PFC_PIN_GROUP(du_rgb888),
4466 		SH_PFC_PIN_GROUP(du_clk_out_0),
4467 		SH_PFC_PIN_GROUP(du_clk_out_1),
4468 		SH_PFC_PIN_GROUP(du_sync),
4469 		SH_PFC_PIN_GROUP(du_oddf),
4470 		SH_PFC_PIN_GROUP(du_cde),
4471 		SH_PFC_PIN_GROUP(du_disp),
4472 		SH_PFC_PIN_GROUP(du0_clk_in),
4473 		SH_PFC_PIN_GROUP(du1_clk_in),
4474 		SH_PFC_PIN_GROUP(du1_clk_in_b),
4475 		SH_PFC_PIN_GROUP(du1_clk_in_c),
4476 		SH_PFC_PIN_GROUP(eth_link),
4477 		SH_PFC_PIN_GROUP(eth_magic),
4478 		SH_PFC_PIN_GROUP(eth_mdio),
4479 		SH_PFC_PIN_GROUP(eth_rmii),
4480 		SH_PFC_PIN_GROUP(hscif0_data),
4481 		SH_PFC_PIN_GROUP(hscif0_clk),
4482 		SH_PFC_PIN_GROUP(hscif0_ctrl),
4483 		SH_PFC_PIN_GROUP(hscif0_data_b),
4484 		SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4485 		SH_PFC_PIN_GROUP(hscif0_data_c),
4486 		SH_PFC_PIN_GROUP(hscif0_clk_c),
4487 		SH_PFC_PIN_GROUP(hscif1_data),
4488 		SH_PFC_PIN_GROUP(hscif1_clk),
4489 		SH_PFC_PIN_GROUP(hscif1_ctrl),
4490 		SH_PFC_PIN_GROUP(hscif1_data_b),
4491 		SH_PFC_PIN_GROUP(hscif1_data_c),
4492 		SH_PFC_PIN_GROUP(hscif1_clk_c),
4493 		SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4494 		SH_PFC_PIN_GROUP(hscif1_data_d),
4495 		SH_PFC_PIN_GROUP(hscif1_data_e),
4496 		SH_PFC_PIN_GROUP(hscif1_clk_e),
4497 		SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4498 		SH_PFC_PIN_GROUP(hscif2_data),
4499 		SH_PFC_PIN_GROUP(hscif2_clk),
4500 		SH_PFC_PIN_GROUP(hscif2_ctrl),
4501 		SH_PFC_PIN_GROUP(hscif2_data_b),
4502 		SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4503 		SH_PFC_PIN_GROUP(hscif2_data_c),
4504 		SH_PFC_PIN_GROUP(hscif2_clk_c),
4505 		SH_PFC_PIN_GROUP(hscif2_data_d),
4506 		SH_PFC_PIN_GROUP(i2c0),
4507 		SH_PFC_PIN_GROUP(i2c0_b),
4508 		SH_PFC_PIN_GROUP(i2c0_c),
4509 		SH_PFC_PIN_GROUP(i2c1),
4510 		SH_PFC_PIN_GROUP(i2c1_b),
4511 		SH_PFC_PIN_GROUP(i2c1_c),
4512 		SH_PFC_PIN_GROUP(i2c1_d),
4513 		SH_PFC_PIN_GROUP(i2c1_e),
4514 		SH_PFC_PIN_GROUP(i2c2),
4515 		SH_PFC_PIN_GROUP(i2c2_b),
4516 		SH_PFC_PIN_GROUP(i2c2_c),
4517 		SH_PFC_PIN_GROUP(i2c2_d),
4518 		SH_PFC_PIN_GROUP(i2c3),
4519 		SH_PFC_PIN_GROUP(i2c3_b),
4520 		SH_PFC_PIN_GROUP(i2c3_c),
4521 		SH_PFC_PIN_GROUP(i2c3_d),
4522 		SH_PFC_PIN_GROUP(i2c4),
4523 		SH_PFC_PIN_GROUP(i2c4_b),
4524 		SH_PFC_PIN_GROUP(i2c4_c),
4525 		SH_PFC_PIN_GROUP(i2c7),
4526 		SH_PFC_PIN_GROUP(i2c7_b),
4527 		SH_PFC_PIN_GROUP(i2c7_c),
4528 		SH_PFC_PIN_GROUP(i2c8),
4529 		SH_PFC_PIN_GROUP(i2c8_b),
4530 		SH_PFC_PIN_GROUP(i2c8_c),
4531 		SH_PFC_PIN_GROUP(intc_irq0),
4532 		SH_PFC_PIN_GROUP(intc_irq1),
4533 		SH_PFC_PIN_GROUP(intc_irq2),
4534 		SH_PFC_PIN_GROUP(intc_irq3),
4535 		SH_PFC_PIN_GROUP(mmc_data1),
4536 		SH_PFC_PIN_GROUP(mmc_data4),
4537 		SH_PFC_PIN_GROUP(mmc_data8),
4538 		SH_PFC_PIN_GROUP(mmc_data8_b),
4539 		SH_PFC_PIN_GROUP(mmc_ctrl),
4540 		SH_PFC_PIN_GROUP(msiof0_clk),
4541 		SH_PFC_PIN_GROUP(msiof0_sync),
4542 		SH_PFC_PIN_GROUP(msiof0_ss1),
4543 		SH_PFC_PIN_GROUP(msiof0_ss2),
4544 		SH_PFC_PIN_GROUP(msiof0_rx),
4545 		SH_PFC_PIN_GROUP(msiof0_tx),
4546 		SH_PFC_PIN_GROUP(msiof0_clk_b),
4547 		SH_PFC_PIN_GROUP(msiof0_sync_b),
4548 		SH_PFC_PIN_GROUP(msiof0_ss1_b),
4549 		SH_PFC_PIN_GROUP(msiof0_ss2_b),
4550 		SH_PFC_PIN_GROUP(msiof0_rx_b),
4551 		SH_PFC_PIN_GROUP(msiof0_tx_b),
4552 		SH_PFC_PIN_GROUP(msiof0_clk_c),
4553 		SH_PFC_PIN_GROUP(msiof0_sync_c),
4554 		SH_PFC_PIN_GROUP(msiof0_ss1_c),
4555 		SH_PFC_PIN_GROUP(msiof0_ss2_c),
4556 		SH_PFC_PIN_GROUP(msiof0_rx_c),
4557 		SH_PFC_PIN_GROUP(msiof0_tx_c),
4558 		SH_PFC_PIN_GROUP(msiof1_clk),
4559 		SH_PFC_PIN_GROUP(msiof1_sync),
4560 		SH_PFC_PIN_GROUP(msiof1_ss1),
4561 		SH_PFC_PIN_GROUP(msiof1_ss2),
4562 		SH_PFC_PIN_GROUP(msiof1_rx),
4563 		SH_PFC_PIN_GROUP(msiof1_tx),
4564 		SH_PFC_PIN_GROUP(msiof1_clk_b),
4565 		SH_PFC_PIN_GROUP(msiof1_sync_b),
4566 		SH_PFC_PIN_GROUP(msiof1_ss1_b),
4567 		SH_PFC_PIN_GROUP(msiof1_ss2_b),
4568 		SH_PFC_PIN_GROUP(msiof1_rx_b),
4569 		SH_PFC_PIN_GROUP(msiof1_tx_b),
4570 		SH_PFC_PIN_GROUP(msiof1_clk_c),
4571 		SH_PFC_PIN_GROUP(msiof1_sync_c),
4572 		SH_PFC_PIN_GROUP(msiof1_rx_c),
4573 		SH_PFC_PIN_GROUP(msiof1_tx_c),
4574 		SH_PFC_PIN_GROUP(msiof1_clk_d),
4575 		SH_PFC_PIN_GROUP(msiof1_sync_d),
4576 		SH_PFC_PIN_GROUP(msiof1_ss1_d),
4577 		SH_PFC_PIN_GROUP(msiof1_rx_d),
4578 		SH_PFC_PIN_GROUP(msiof1_tx_d),
4579 		SH_PFC_PIN_GROUP(msiof1_clk_e),
4580 		SH_PFC_PIN_GROUP(msiof1_sync_e),
4581 		SH_PFC_PIN_GROUP(msiof1_rx_e),
4582 		SH_PFC_PIN_GROUP(msiof1_tx_e),
4583 		SH_PFC_PIN_GROUP(msiof2_clk),
4584 		SH_PFC_PIN_GROUP(msiof2_sync),
4585 		SH_PFC_PIN_GROUP(msiof2_ss1),
4586 		SH_PFC_PIN_GROUP(msiof2_ss2),
4587 		SH_PFC_PIN_GROUP(msiof2_rx),
4588 		SH_PFC_PIN_GROUP(msiof2_tx),
4589 		SH_PFC_PIN_GROUP(msiof2_clk_b),
4590 		SH_PFC_PIN_GROUP(msiof2_sync_b),
4591 		SH_PFC_PIN_GROUP(msiof2_ss1_b),
4592 		SH_PFC_PIN_GROUP(msiof2_ss2_b),
4593 		SH_PFC_PIN_GROUP(msiof2_rx_b),
4594 		SH_PFC_PIN_GROUP(msiof2_tx_b),
4595 		SH_PFC_PIN_GROUP(msiof2_clk_c),
4596 		SH_PFC_PIN_GROUP(msiof2_sync_c),
4597 		SH_PFC_PIN_GROUP(msiof2_rx_c),
4598 		SH_PFC_PIN_GROUP(msiof2_tx_c),
4599 		SH_PFC_PIN_GROUP(msiof2_clk_d),
4600 		SH_PFC_PIN_GROUP(msiof2_sync_d),
4601 		SH_PFC_PIN_GROUP(msiof2_ss1_d),
4602 		SH_PFC_PIN_GROUP(msiof2_ss2_d),
4603 		SH_PFC_PIN_GROUP(msiof2_rx_d),
4604 		SH_PFC_PIN_GROUP(msiof2_tx_d),
4605 		SH_PFC_PIN_GROUP(msiof2_clk_e),
4606 		SH_PFC_PIN_GROUP(msiof2_sync_e),
4607 		SH_PFC_PIN_GROUP(msiof2_rx_e),
4608 		SH_PFC_PIN_GROUP(msiof2_tx_e),
4609 		SH_PFC_PIN_GROUP(pwm0),
4610 		SH_PFC_PIN_GROUP(pwm0_b),
4611 		SH_PFC_PIN_GROUP(pwm1),
4612 		SH_PFC_PIN_GROUP(pwm1_b),
4613 		SH_PFC_PIN_GROUP(pwm2),
4614 		SH_PFC_PIN_GROUP(pwm2_b),
4615 		SH_PFC_PIN_GROUP(pwm3),
4616 		SH_PFC_PIN_GROUP(pwm4),
4617 		SH_PFC_PIN_GROUP(pwm4_b),
4618 		SH_PFC_PIN_GROUP(pwm5),
4619 		SH_PFC_PIN_GROUP(pwm5_b),
4620 		SH_PFC_PIN_GROUP(pwm6),
4621 		SH_PFC_PIN_GROUP(qspi_ctrl),
4622 		SH_PFC_PIN_GROUP(qspi_data2),
4623 		SH_PFC_PIN_GROUP(qspi_data4),
4624 		SH_PFC_PIN_GROUP(qspi_ctrl_b),
4625 		SH_PFC_PIN_GROUP(qspi_data2_b),
4626 		SH_PFC_PIN_GROUP(qspi_data4_b),
4627 		SH_PFC_PIN_GROUP(scif0_data),
4628 		SH_PFC_PIN_GROUP(scif0_data_b),
4629 		SH_PFC_PIN_GROUP(scif0_data_c),
4630 		SH_PFC_PIN_GROUP(scif0_data_d),
4631 		SH_PFC_PIN_GROUP(scif0_data_e),
4632 		SH_PFC_PIN_GROUP(scif1_data),
4633 		SH_PFC_PIN_GROUP(scif1_data_b),
4634 		SH_PFC_PIN_GROUP(scif1_clk_b),
4635 		SH_PFC_PIN_GROUP(scif1_data_c),
4636 		SH_PFC_PIN_GROUP(scif1_data_d),
4637 		SH_PFC_PIN_GROUP(scif2_data),
4638 		SH_PFC_PIN_GROUP(scif2_data_b),
4639 		SH_PFC_PIN_GROUP(scif2_clk_b),
4640 		SH_PFC_PIN_GROUP(scif2_data_c),
4641 		SH_PFC_PIN_GROUP(scif2_data_e),
4642 		SH_PFC_PIN_GROUP(scif3_data),
4643 		SH_PFC_PIN_GROUP(scif3_clk),
4644 		SH_PFC_PIN_GROUP(scif3_data_b),
4645 		SH_PFC_PIN_GROUP(scif3_clk_b),
4646 		SH_PFC_PIN_GROUP(scif3_data_c),
4647 		SH_PFC_PIN_GROUP(scif3_data_d),
4648 		SH_PFC_PIN_GROUP(scif4_data),
4649 		SH_PFC_PIN_GROUP(scif4_data_b),
4650 		SH_PFC_PIN_GROUP(scif4_data_c),
4651 		SH_PFC_PIN_GROUP(scif5_data),
4652 		SH_PFC_PIN_GROUP(scif5_data_b),
4653 		SH_PFC_PIN_GROUP(scifa0_data),
4654 		SH_PFC_PIN_GROUP(scifa0_data_b),
4655 		SH_PFC_PIN_GROUP(scifa1_data),
4656 		SH_PFC_PIN_GROUP(scifa1_clk),
4657 		SH_PFC_PIN_GROUP(scifa1_data_b),
4658 		SH_PFC_PIN_GROUP(scifa1_clk_b),
4659 		SH_PFC_PIN_GROUP(scifa1_data_c),
4660 		SH_PFC_PIN_GROUP(scifa2_data),
4661 		SH_PFC_PIN_GROUP(scifa2_clk),
4662 		SH_PFC_PIN_GROUP(scifa2_data_b),
4663 		SH_PFC_PIN_GROUP(scifa3_data),
4664 		SH_PFC_PIN_GROUP(scifa3_clk),
4665 		SH_PFC_PIN_GROUP(scifa3_data_b),
4666 		SH_PFC_PIN_GROUP(scifa3_clk_b),
4667 		SH_PFC_PIN_GROUP(scifa3_data_c),
4668 		SH_PFC_PIN_GROUP(scifa3_clk_c),
4669 		SH_PFC_PIN_GROUP(scifa4_data),
4670 		SH_PFC_PIN_GROUP(scifa4_data_b),
4671 		SH_PFC_PIN_GROUP(scifa4_data_c),
4672 		SH_PFC_PIN_GROUP(scifa5_data),
4673 		SH_PFC_PIN_GROUP(scifa5_data_b),
4674 		SH_PFC_PIN_GROUP(scifa5_data_c),
4675 		SH_PFC_PIN_GROUP(scifb0_data),
4676 		SH_PFC_PIN_GROUP(scifb0_clk),
4677 		SH_PFC_PIN_GROUP(scifb0_ctrl),
4678 		SH_PFC_PIN_GROUP(scifb0_data_b),
4679 		SH_PFC_PIN_GROUP(scifb0_clk_b),
4680 		SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4681 		SH_PFC_PIN_GROUP(scifb0_data_c),
4682 		SH_PFC_PIN_GROUP(scifb0_clk_c),
4683 		SH_PFC_PIN_GROUP(scifb0_data_d),
4684 		SH_PFC_PIN_GROUP(scifb0_clk_d),
4685 		SH_PFC_PIN_GROUP(scifb1_data),
4686 		SH_PFC_PIN_GROUP(scifb1_clk),
4687 		SH_PFC_PIN_GROUP(scifb1_ctrl),
4688 		SH_PFC_PIN_GROUP(scifb1_data_b),
4689 		SH_PFC_PIN_GROUP(scifb1_clk_b),
4690 		SH_PFC_PIN_GROUP(scifb1_data_c),
4691 		SH_PFC_PIN_GROUP(scifb1_clk_c),
4692 		SH_PFC_PIN_GROUP(scifb1_data_d),
4693 		SH_PFC_PIN_GROUP(scifb2_data),
4694 		SH_PFC_PIN_GROUP(scifb2_clk),
4695 		SH_PFC_PIN_GROUP(scifb2_ctrl),
4696 		SH_PFC_PIN_GROUP(scifb2_data_b),
4697 		SH_PFC_PIN_GROUP(scifb2_clk_b),
4698 		SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4699 		SH_PFC_PIN_GROUP(scifb2_data_c),
4700 		SH_PFC_PIN_GROUP(scifb2_clk_c),
4701 		SH_PFC_PIN_GROUP(scifb2_data_d),
4702 		SH_PFC_PIN_GROUP(scif_clk),
4703 		SH_PFC_PIN_GROUP(scif_clk_b),
4704 		SH_PFC_PIN_GROUP(sdhi0_data1),
4705 		SH_PFC_PIN_GROUP(sdhi0_data4),
4706 		SH_PFC_PIN_GROUP(sdhi0_ctrl),
4707 		SH_PFC_PIN_GROUP(sdhi0_cd),
4708 		SH_PFC_PIN_GROUP(sdhi0_wp),
4709 		SH_PFC_PIN_GROUP(sdhi1_data1),
4710 		SH_PFC_PIN_GROUP(sdhi1_data4),
4711 		SH_PFC_PIN_GROUP(sdhi1_ctrl),
4712 		SH_PFC_PIN_GROUP(sdhi1_cd),
4713 		SH_PFC_PIN_GROUP(sdhi1_wp),
4714 		SH_PFC_PIN_GROUP(sdhi2_data1),
4715 		SH_PFC_PIN_GROUP(sdhi2_data4),
4716 		SH_PFC_PIN_GROUP(sdhi2_ctrl),
4717 		SH_PFC_PIN_GROUP(sdhi2_cd),
4718 		SH_PFC_PIN_GROUP(sdhi2_wp),
4719 		SH_PFC_PIN_GROUP(ssi0_data),
4720 		SH_PFC_PIN_GROUP(ssi0_data_b),
4721 		SH_PFC_PIN_GROUP(ssi0129_ctrl),
4722 		SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4723 		SH_PFC_PIN_GROUP(ssi1_data),
4724 		SH_PFC_PIN_GROUP(ssi1_data_b),
4725 		SH_PFC_PIN_GROUP(ssi1_ctrl),
4726 		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4727 		SH_PFC_PIN_GROUP(ssi2_data),
4728 		SH_PFC_PIN_GROUP(ssi2_ctrl),
4729 		SH_PFC_PIN_GROUP(ssi3_data),
4730 		SH_PFC_PIN_GROUP(ssi34_ctrl),
4731 		SH_PFC_PIN_GROUP(ssi4_data),
4732 		SH_PFC_PIN_GROUP(ssi4_ctrl),
4733 		SH_PFC_PIN_GROUP(ssi5_data),
4734 		SH_PFC_PIN_GROUP(ssi5_ctrl),
4735 		SH_PFC_PIN_GROUP(ssi6_data),
4736 		SH_PFC_PIN_GROUP(ssi6_ctrl),
4737 		SH_PFC_PIN_GROUP(ssi7_data),
4738 		SH_PFC_PIN_GROUP(ssi7_data_b),
4739 		SH_PFC_PIN_GROUP(ssi78_ctrl),
4740 		SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4741 		SH_PFC_PIN_GROUP(ssi8_data),
4742 		SH_PFC_PIN_GROUP(ssi8_data_b),
4743 		SH_PFC_PIN_GROUP(ssi9_data),
4744 		SH_PFC_PIN_GROUP(ssi9_data_b),
4745 		SH_PFC_PIN_GROUP(ssi9_ctrl),
4746 		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4747 		SH_PFC_PIN_GROUP(usb0),
4748 		SH_PFC_PIN_GROUP(usb1),
4749 		VIN_DATA_PIN_GROUP(vin0_data, 24),
4750 		VIN_DATA_PIN_GROUP(vin0_data, 20),
4751 		SH_PFC_PIN_GROUP(vin0_data18),
4752 		VIN_DATA_PIN_GROUP(vin0_data, 16),
4753 		VIN_DATA_PIN_GROUP(vin0_data, 12),
4754 		VIN_DATA_PIN_GROUP(vin0_data, 10),
4755 		VIN_DATA_PIN_GROUP(vin0_data, 8),
4756 		SH_PFC_PIN_GROUP(vin0_sync),
4757 		SH_PFC_PIN_GROUP(vin0_field),
4758 		SH_PFC_PIN_GROUP(vin0_clkenb),
4759 		SH_PFC_PIN_GROUP(vin0_clk),
4760 		SH_PFC_PIN_GROUP(vin1_data8),
4761 		SH_PFC_PIN_GROUP(vin1_sync),
4762 		SH_PFC_PIN_GROUP(vin1_field),
4763 		SH_PFC_PIN_GROUP(vin1_clkenb),
4764 		SH_PFC_PIN_GROUP(vin1_clk),
4765 		VIN_DATA_PIN_GROUP(vin1_b_data, 24),
4766 		VIN_DATA_PIN_GROUP(vin1_b_data, 20),
4767 		SH_PFC_PIN_GROUP(vin1_b_data18),
4768 		VIN_DATA_PIN_GROUP(vin1_b_data, 16),
4769 		VIN_DATA_PIN_GROUP(vin1_b_data, 12),
4770 		VIN_DATA_PIN_GROUP(vin1_b_data, 10),
4771 		VIN_DATA_PIN_GROUP(vin1_b_data, 8),
4772 		SH_PFC_PIN_GROUP(vin1_b_sync),
4773 		SH_PFC_PIN_GROUP(vin1_b_field),
4774 		SH_PFC_PIN_GROUP(vin1_b_clkenb),
4775 		SH_PFC_PIN_GROUP(vin1_b_clk),
4776 		SH_PFC_PIN_GROUP(vin2_data8),
4777 		SH_PFC_PIN_GROUP(vin2_sync),
4778 		SH_PFC_PIN_GROUP(vin2_field),
4779 		SH_PFC_PIN_GROUP(vin2_clkenb),
4780 		SH_PFC_PIN_GROUP(vin2_clk),
4781 	},
4782 	.r8a779x = {
4783 		SH_PFC_PIN_GROUP(adi_common),
4784 		SH_PFC_PIN_GROUP(adi_chsel0),
4785 		SH_PFC_PIN_GROUP(adi_chsel1),
4786 		SH_PFC_PIN_GROUP(adi_chsel2),
4787 		SH_PFC_PIN_GROUP(adi_common_b),
4788 		SH_PFC_PIN_GROUP(adi_chsel0_b),
4789 		SH_PFC_PIN_GROUP(adi_chsel1_b),
4790 		SH_PFC_PIN_GROUP(adi_chsel2_b),
4791 		SH_PFC_PIN_GROUP(mlb_3pin),
4792 	}
4793 };
4794 
4795 static const char * const adi_groups[] = {
4796 	"adi_common",
4797 	"adi_chsel0",
4798 	"adi_chsel1",
4799 	"adi_chsel2",
4800 	"adi_common_b",
4801 	"adi_chsel0_b",
4802 	"adi_chsel1_b",
4803 	"adi_chsel2_b",
4804 };
4805 
4806 static const char * const audio_clk_groups[] = {
4807 	"audio_clk_a",
4808 	"audio_clk_b",
4809 	"audio_clk_b_b",
4810 	"audio_clk_c",
4811 	"audio_clkout",
4812 };
4813 
4814 static const char * const avb_groups[] = {
4815 	"avb_link",
4816 	"avb_magic",
4817 	"avb_phy_int",
4818 	"avb_mdio",
4819 	"avb_mii",
4820 	"avb_gmii",
4821 };
4822 
4823 static const char * const can0_groups[] = {
4824 	"can0_data",
4825 	"can0_data_b",
4826 	"can0_data_c",
4827 	"can0_data_d",
4828 	"can0_data_e",
4829 	"can0_data_f",
4830 	"can_clk",
4831 	"can_clk_b",
4832 	"can_clk_c",
4833 	"can_clk_d",
4834 };
4835 
4836 static const char * const can1_groups[] = {
4837 	"can1_data",
4838 	"can1_data_b",
4839 	"can1_data_c",
4840 	"can1_data_d",
4841 	"can_clk",
4842 	"can_clk_b",
4843 	"can_clk_c",
4844 	"can_clk_d",
4845 };
4846 
4847 static const char * const du_groups[] = {
4848 	"du_rgb666",
4849 	"du_rgb888",
4850 	"du_clk_out_0",
4851 	"du_clk_out_1",
4852 	"du_sync",
4853 	"du_oddf",
4854 	"du_cde",
4855 	"du_disp",
4856 };
4857 
4858 static const char * const du0_groups[] = {
4859 	"du0_clk_in",
4860 };
4861 
4862 static const char * const du1_groups[] = {
4863 	"du1_clk_in",
4864 	"du1_clk_in_b",
4865 	"du1_clk_in_c",
4866 };
4867 
4868 static const char * const eth_groups[] = {
4869 	"eth_link",
4870 	"eth_magic",
4871 	"eth_mdio",
4872 	"eth_rmii",
4873 };
4874 
4875 static const char * const hscif0_groups[] = {
4876 	"hscif0_data",
4877 	"hscif0_clk",
4878 	"hscif0_ctrl",
4879 	"hscif0_data_b",
4880 	"hscif0_ctrl_b",
4881 	"hscif0_data_c",
4882 	"hscif0_clk_c",
4883 };
4884 
4885 static const char * const hscif1_groups[] = {
4886 	"hscif1_data",
4887 	"hscif1_clk",
4888 	"hscif1_ctrl",
4889 	"hscif1_data_b",
4890 	"hscif1_data_c",
4891 	"hscif1_clk_c",
4892 	"hscif1_ctrl_c",
4893 	"hscif1_data_d",
4894 	"hscif1_data_e",
4895 	"hscif1_clk_e",
4896 	"hscif1_ctrl_e",
4897 };
4898 
4899 static const char * const hscif2_groups[] = {
4900 	"hscif2_data",
4901 	"hscif2_clk",
4902 	"hscif2_ctrl",
4903 	"hscif2_data_b",
4904 	"hscif2_ctrl_b",
4905 	"hscif2_data_c",
4906 	"hscif2_clk_c",
4907 	"hscif2_data_d",
4908 };
4909 
4910 static const char * const i2c0_groups[] = {
4911 	"i2c0",
4912 	"i2c0_b",
4913 	"i2c0_c",
4914 };
4915 
4916 static const char * const i2c1_groups[] = {
4917 	"i2c1",
4918 	"i2c1_b",
4919 	"i2c1_c",
4920 	"i2c1_d",
4921 	"i2c1_e",
4922 };
4923 
4924 static const char * const i2c2_groups[] = {
4925 	"i2c2",
4926 	"i2c2_b",
4927 	"i2c2_c",
4928 	"i2c2_d",
4929 };
4930 
4931 static const char * const i2c3_groups[] = {
4932 	"i2c3",
4933 	"i2c3_b",
4934 	"i2c3_c",
4935 	"i2c3_d",
4936 };
4937 
4938 static const char * const i2c4_groups[] = {
4939 	"i2c4",
4940 	"i2c4_b",
4941 	"i2c4_c",
4942 };
4943 
4944 static const char * const i2c7_groups[] = {
4945 	"i2c7",
4946 	"i2c7_b",
4947 	"i2c7_c",
4948 };
4949 
4950 static const char * const i2c8_groups[] = {
4951 	"i2c8",
4952 	"i2c8_b",
4953 	"i2c8_c",
4954 };
4955 
4956 static const char * const intc_groups[] = {
4957 	"intc_irq0",
4958 	"intc_irq1",
4959 	"intc_irq2",
4960 	"intc_irq3",
4961 };
4962 
4963 static const char * const mlb_groups[] = {
4964 	"mlb_3pin",
4965 };
4966 
4967 static const char * const mmc_groups[] = {
4968 	"mmc_data1",
4969 	"mmc_data4",
4970 	"mmc_data8",
4971 	"mmc_data8_b",
4972 	"mmc_ctrl",
4973 };
4974 
4975 static const char * const msiof0_groups[] = {
4976 	"msiof0_clk",
4977 	"msiof0_sync",
4978 	"msiof0_ss1",
4979 	"msiof0_ss2",
4980 	"msiof0_rx",
4981 	"msiof0_tx",
4982 	"msiof0_clk_b",
4983 	"msiof0_sync_b",
4984 	"msiof0_ss1_b",
4985 	"msiof0_ss2_b",
4986 	"msiof0_rx_b",
4987 	"msiof0_tx_b",
4988 	"msiof0_clk_c",
4989 	"msiof0_sync_c",
4990 	"msiof0_ss1_c",
4991 	"msiof0_ss2_c",
4992 	"msiof0_rx_c",
4993 	"msiof0_tx_c",
4994 };
4995 
4996 static const char * const msiof1_groups[] = {
4997 	"msiof1_clk",
4998 	"msiof1_sync",
4999 	"msiof1_ss1",
5000 	"msiof1_ss2",
5001 	"msiof1_rx",
5002 	"msiof1_tx",
5003 	"msiof1_clk_b",
5004 	"msiof1_sync_b",
5005 	"msiof1_ss1_b",
5006 	"msiof1_ss2_b",
5007 	"msiof1_rx_b",
5008 	"msiof1_tx_b",
5009 	"msiof1_clk_c",
5010 	"msiof1_sync_c",
5011 	"msiof1_rx_c",
5012 	"msiof1_tx_c",
5013 	"msiof1_clk_d",
5014 	"msiof1_sync_d",
5015 	"msiof1_ss1_d",
5016 	"msiof1_rx_d",
5017 	"msiof1_tx_d",
5018 	"msiof1_clk_e",
5019 	"msiof1_sync_e",
5020 	"msiof1_rx_e",
5021 	"msiof1_tx_e",
5022 };
5023 
5024 static const char * const msiof2_groups[] = {
5025 	"msiof2_clk",
5026 	"msiof2_sync",
5027 	"msiof2_ss1",
5028 	"msiof2_ss2",
5029 	"msiof2_rx",
5030 	"msiof2_tx",
5031 	"msiof2_clk_b",
5032 	"msiof2_sync_b",
5033 	"msiof2_ss1_b",
5034 	"msiof2_ss2_b",
5035 	"msiof2_rx_b",
5036 	"msiof2_tx_b",
5037 	"msiof2_clk_c",
5038 	"msiof2_sync_c",
5039 	"msiof2_rx_c",
5040 	"msiof2_tx_c",
5041 	"msiof2_clk_d",
5042 	"msiof2_sync_d",
5043 	"msiof2_ss1_d",
5044 	"msiof2_ss2_d",
5045 	"msiof2_rx_d",
5046 	"msiof2_tx_d",
5047 	"msiof2_clk_e",
5048 	"msiof2_sync_e",
5049 	"msiof2_rx_e",
5050 	"msiof2_tx_e",
5051 };
5052 
5053 static const char * const pwm0_groups[] = {
5054 	"pwm0",
5055 	"pwm0_b",
5056 };
5057 
5058 static const char * const pwm1_groups[] = {
5059 	"pwm1",
5060 	"pwm1_b",
5061 };
5062 
5063 static const char * const pwm2_groups[] = {
5064 	"pwm2",
5065 	"pwm2_b",
5066 };
5067 
5068 static const char * const pwm3_groups[] = {
5069 	"pwm3",
5070 };
5071 
5072 static const char * const pwm4_groups[] = {
5073 	"pwm4",
5074 	"pwm4_b",
5075 };
5076 
5077 static const char * const pwm5_groups[] = {
5078 	"pwm5",
5079 	"pwm5_b",
5080 };
5081 
5082 static const char * const pwm6_groups[] = {
5083 	"pwm6",
5084 };
5085 
5086 static const char * const qspi_groups[] = {
5087 	"qspi_ctrl",
5088 	"qspi_data2",
5089 	"qspi_data4",
5090 	"qspi_ctrl_b",
5091 	"qspi_data2_b",
5092 	"qspi_data4_b",
5093 };
5094 
5095 static const char * const scif0_groups[] = {
5096 	"scif0_data",
5097 	"scif0_data_b",
5098 	"scif0_data_c",
5099 	"scif0_data_d",
5100 	"scif0_data_e",
5101 };
5102 
5103 static const char * const scif1_groups[] = {
5104 	"scif1_data",
5105 	"scif1_data_b",
5106 	"scif1_clk_b",
5107 	"scif1_data_c",
5108 	"scif1_data_d",
5109 };
5110 
5111 static const char * const scif2_groups[] = {
5112 	"scif2_data",
5113 	"scif2_data_b",
5114 	"scif2_clk_b",
5115 	"scif2_data_c",
5116 	"scif2_data_e",
5117 };
5118 static const char * const scif3_groups[] = {
5119 	"scif3_data",
5120 	"scif3_clk",
5121 	"scif3_data_b",
5122 	"scif3_clk_b",
5123 	"scif3_data_c",
5124 	"scif3_data_d",
5125 };
5126 static const char * const scif4_groups[] = {
5127 	"scif4_data",
5128 	"scif4_data_b",
5129 	"scif4_data_c",
5130 };
5131 static const char * const scif5_groups[] = {
5132 	"scif5_data",
5133 	"scif5_data_b",
5134 };
5135 static const char * const scifa0_groups[] = {
5136 	"scifa0_data",
5137 	"scifa0_data_b",
5138 };
5139 static const char * const scifa1_groups[] = {
5140 	"scifa1_data",
5141 	"scifa1_clk",
5142 	"scifa1_data_b",
5143 	"scifa1_clk_b",
5144 	"scifa1_data_c",
5145 };
5146 static const char * const scifa2_groups[] = {
5147 	"scifa2_data",
5148 	"scifa2_clk",
5149 	"scifa2_data_b",
5150 };
5151 static const char * const scifa3_groups[] = {
5152 	"scifa3_data",
5153 	"scifa3_clk",
5154 	"scifa3_data_b",
5155 	"scifa3_clk_b",
5156 	"scifa3_data_c",
5157 	"scifa3_clk_c",
5158 };
5159 static const char * const scifa4_groups[] = {
5160 	"scifa4_data",
5161 	"scifa4_data_b",
5162 	"scifa4_data_c",
5163 };
5164 static const char * const scifa5_groups[] = {
5165 	"scifa5_data",
5166 	"scifa5_data_b",
5167 	"scifa5_data_c",
5168 };
5169 static const char * const scifb0_groups[] = {
5170 	"scifb0_data",
5171 	"scifb0_clk",
5172 	"scifb0_ctrl",
5173 	"scifb0_data_b",
5174 	"scifb0_clk_b",
5175 	"scifb0_ctrl_b",
5176 	"scifb0_data_c",
5177 	"scifb0_clk_c",
5178 	"scifb0_data_d",
5179 	"scifb0_clk_d",
5180 };
5181 static const char * const scifb1_groups[] = {
5182 	"scifb1_data",
5183 	"scifb1_clk",
5184 	"scifb1_ctrl",
5185 	"scifb1_data_b",
5186 	"scifb1_clk_b",
5187 	"scifb1_data_c",
5188 	"scifb1_clk_c",
5189 	"scifb1_data_d",
5190 };
5191 static const char * const scifb2_groups[] = {
5192 	"scifb2_data",
5193 	"scifb2_clk",
5194 	"scifb2_ctrl",
5195 	"scifb2_data_b",
5196 	"scifb2_clk_b",
5197 	"scifb2_ctrl_b",
5198 	"scifb0_data_c",
5199 	"scifb2_clk_c",
5200 	"scifb2_data_d",
5201 };
5202 
5203 static const char * const scif_clk_groups[] = {
5204 	"scif_clk",
5205 	"scif_clk_b",
5206 };
5207 
5208 static const char * const sdhi0_groups[] = {
5209 	"sdhi0_data1",
5210 	"sdhi0_data4",
5211 	"sdhi0_ctrl",
5212 	"sdhi0_cd",
5213 	"sdhi0_wp",
5214 };
5215 
5216 static const char * const sdhi1_groups[] = {
5217 	"sdhi1_data1",
5218 	"sdhi1_data4",
5219 	"sdhi1_ctrl",
5220 	"sdhi1_cd",
5221 	"sdhi1_wp",
5222 };
5223 
5224 static const char * const sdhi2_groups[] = {
5225 	"sdhi2_data1",
5226 	"sdhi2_data4",
5227 	"sdhi2_ctrl",
5228 	"sdhi2_cd",
5229 	"sdhi2_wp",
5230 };
5231 
5232 static const char * const ssi_groups[] = {
5233 	"ssi0_data",
5234 	"ssi0_data_b",
5235 	"ssi0129_ctrl",
5236 	"ssi0129_ctrl_b",
5237 	"ssi1_data",
5238 	"ssi1_data_b",
5239 	"ssi1_ctrl",
5240 	"ssi1_ctrl_b",
5241 	"ssi2_data",
5242 	"ssi2_ctrl",
5243 	"ssi3_data",
5244 	"ssi34_ctrl",
5245 	"ssi4_data",
5246 	"ssi4_ctrl",
5247 	"ssi5_data",
5248 	"ssi5_ctrl",
5249 	"ssi6_data",
5250 	"ssi6_ctrl",
5251 	"ssi7_data",
5252 	"ssi7_data_b",
5253 	"ssi78_ctrl",
5254 	"ssi78_ctrl_b",
5255 	"ssi8_data",
5256 	"ssi8_data_b",
5257 	"ssi9_data",
5258 	"ssi9_data_b",
5259 	"ssi9_ctrl",
5260 	"ssi9_ctrl_b",
5261 };
5262 
5263 static const char * const usb0_groups[] = {
5264 	"usb0",
5265 };
5266 static const char * const usb1_groups[] = {
5267 	"usb1",
5268 };
5269 
5270 static const char * const vin0_groups[] = {
5271 	"vin0_data24",
5272 	"vin0_data20",
5273 	"vin0_data18",
5274 	"vin0_data16",
5275 	"vin0_data12",
5276 	"vin0_data10",
5277 	"vin0_data8",
5278 	"vin0_sync",
5279 	"vin0_field",
5280 	"vin0_clkenb",
5281 	"vin0_clk",
5282 };
5283 
5284 static const char * const vin1_groups[] = {
5285 	"vin1_data8",
5286 	"vin1_sync",
5287 	"vin1_field",
5288 	"vin1_clkenb",
5289 	"vin1_clk",
5290 	"vin1_b_data24",
5291 	"vin1_b_data20",
5292 	"vin1_b_data18",
5293 	"vin1_b_data16",
5294 	"vin1_b_data12",
5295 	"vin1_b_data10",
5296 	"vin1_b_data8",
5297 	"vin1_b_sync",
5298 	"vin1_b_field",
5299 	"vin1_b_clkenb",
5300 	"vin1_b_clk",
5301 };
5302 
5303 static const char * const vin2_groups[] = {
5304 	"vin2_data8",
5305 	"vin2_sync",
5306 	"vin2_field",
5307 	"vin2_clkenb",
5308 	"vin2_clk",
5309 };
5310 
5311 static const struct {
5312 	struct sh_pfc_function common[56];
5313 	struct sh_pfc_function r8a779x[2];
5314 } pinmux_functions = {
5315 	.common = {
5316 		SH_PFC_FUNCTION(audio_clk),
5317 		SH_PFC_FUNCTION(avb),
5318 		SH_PFC_FUNCTION(can0),
5319 		SH_PFC_FUNCTION(can1),
5320 		SH_PFC_FUNCTION(du),
5321 		SH_PFC_FUNCTION(du0),
5322 		SH_PFC_FUNCTION(du1),
5323 		SH_PFC_FUNCTION(eth),
5324 		SH_PFC_FUNCTION(hscif0),
5325 		SH_PFC_FUNCTION(hscif1),
5326 		SH_PFC_FUNCTION(hscif2),
5327 		SH_PFC_FUNCTION(i2c0),
5328 		SH_PFC_FUNCTION(i2c1),
5329 		SH_PFC_FUNCTION(i2c2),
5330 		SH_PFC_FUNCTION(i2c3),
5331 		SH_PFC_FUNCTION(i2c4),
5332 		SH_PFC_FUNCTION(i2c7),
5333 		SH_PFC_FUNCTION(i2c8),
5334 		SH_PFC_FUNCTION(intc),
5335 		SH_PFC_FUNCTION(mmc),
5336 		SH_PFC_FUNCTION(msiof0),
5337 		SH_PFC_FUNCTION(msiof1),
5338 		SH_PFC_FUNCTION(msiof2),
5339 		SH_PFC_FUNCTION(pwm0),
5340 		SH_PFC_FUNCTION(pwm1),
5341 		SH_PFC_FUNCTION(pwm2),
5342 		SH_PFC_FUNCTION(pwm3),
5343 		SH_PFC_FUNCTION(pwm4),
5344 		SH_PFC_FUNCTION(pwm5),
5345 		SH_PFC_FUNCTION(pwm6),
5346 		SH_PFC_FUNCTION(qspi),
5347 		SH_PFC_FUNCTION(scif0),
5348 		SH_PFC_FUNCTION(scif1),
5349 		SH_PFC_FUNCTION(scif2),
5350 		SH_PFC_FUNCTION(scif3),
5351 		SH_PFC_FUNCTION(scif4),
5352 		SH_PFC_FUNCTION(scif5),
5353 		SH_PFC_FUNCTION(scifa0),
5354 		SH_PFC_FUNCTION(scifa1),
5355 		SH_PFC_FUNCTION(scifa2),
5356 		SH_PFC_FUNCTION(scifa3),
5357 		SH_PFC_FUNCTION(scifa4),
5358 		SH_PFC_FUNCTION(scifa5),
5359 		SH_PFC_FUNCTION(scifb0),
5360 		SH_PFC_FUNCTION(scifb1),
5361 		SH_PFC_FUNCTION(scifb2),
5362 		SH_PFC_FUNCTION(scif_clk),
5363 		SH_PFC_FUNCTION(sdhi0),
5364 		SH_PFC_FUNCTION(sdhi1),
5365 		SH_PFC_FUNCTION(sdhi2),
5366 		SH_PFC_FUNCTION(ssi),
5367 		SH_PFC_FUNCTION(usb0),
5368 		SH_PFC_FUNCTION(usb1),
5369 		SH_PFC_FUNCTION(vin0),
5370 		SH_PFC_FUNCTION(vin1),
5371 		SH_PFC_FUNCTION(vin2),
5372 	},
5373 	.r8a779x = {
5374 		SH_PFC_FUNCTION(adi),
5375 		SH_PFC_FUNCTION(mlb),
5376 	}
5377 };
5378 
5379 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5380 	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5381 		GP_0_31_FN, FN_IP1_22_20,
5382 		GP_0_30_FN, FN_IP1_19_17,
5383 		GP_0_29_FN, FN_IP1_16_14,
5384 		GP_0_28_FN, FN_IP1_13_11,
5385 		GP_0_27_FN, FN_IP1_10_8,
5386 		GP_0_26_FN, FN_IP1_7_6,
5387 		GP_0_25_FN, FN_IP1_5_4,
5388 		GP_0_24_FN, FN_IP1_3_2,
5389 		GP_0_23_FN, FN_IP1_1_0,
5390 		GP_0_22_FN, FN_IP0_30_29,
5391 		GP_0_21_FN, FN_IP0_28_27,
5392 		GP_0_20_FN, FN_IP0_26_25,
5393 		GP_0_19_FN, FN_IP0_24_23,
5394 		GP_0_18_FN, FN_IP0_22_21,
5395 		GP_0_17_FN, FN_IP0_20_19,
5396 		GP_0_16_FN, FN_IP0_18_16,
5397 		GP_0_15_FN, FN_IP0_15,
5398 		GP_0_14_FN, FN_IP0_14,
5399 		GP_0_13_FN, FN_IP0_13,
5400 		GP_0_12_FN, FN_IP0_12,
5401 		GP_0_11_FN, FN_IP0_11,
5402 		GP_0_10_FN, FN_IP0_10,
5403 		GP_0_9_FN, FN_IP0_9,
5404 		GP_0_8_FN, FN_IP0_8,
5405 		GP_0_7_FN, FN_IP0_7,
5406 		GP_0_6_FN, FN_IP0_6,
5407 		GP_0_5_FN, FN_IP0_5,
5408 		GP_0_4_FN, FN_IP0_4,
5409 		GP_0_3_FN, FN_IP0_3,
5410 		GP_0_2_FN, FN_IP0_2,
5411 		GP_0_1_FN, FN_IP0_1,
5412 		GP_0_0_FN, FN_IP0_0, }
5413 	},
5414 	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5415 		0, 0,
5416 		0, 0,
5417 		0, 0,
5418 		0, 0,
5419 		0, 0,
5420 		0, 0,
5421 		GP_1_25_FN, FN_IP3_21_20,
5422 		GP_1_24_FN, FN_IP3_19_18,
5423 		GP_1_23_FN, FN_IP3_17_16,
5424 		GP_1_22_FN, FN_IP3_15_14,
5425 		GP_1_21_FN, FN_IP3_13_12,
5426 		GP_1_20_FN, FN_IP3_11_9,
5427 		GP_1_19_FN, FN_RD_N,
5428 		GP_1_18_FN, FN_IP3_8_6,
5429 		GP_1_17_FN, FN_IP3_5_3,
5430 		GP_1_16_FN, FN_IP3_2_0,
5431 		GP_1_15_FN, FN_IP2_29_27,
5432 		GP_1_14_FN, FN_IP2_26_25,
5433 		GP_1_13_FN, FN_IP2_24_23,
5434 		GP_1_12_FN, FN_EX_CS0_N,
5435 		GP_1_11_FN, FN_IP2_22_21,
5436 		GP_1_10_FN, FN_IP2_20_19,
5437 		GP_1_9_FN, FN_IP2_18_16,
5438 		GP_1_8_FN, FN_IP2_15_13,
5439 		GP_1_7_FN, FN_IP2_12_10,
5440 		GP_1_6_FN, FN_IP2_9_7,
5441 		GP_1_5_FN, FN_IP2_6_5,
5442 		GP_1_4_FN, FN_IP2_4_3,
5443 		GP_1_3_FN, FN_IP2_2_0,
5444 		GP_1_2_FN, FN_IP1_31_29,
5445 		GP_1_1_FN, FN_IP1_28_26,
5446 		GP_1_0_FN, FN_IP1_25_23, }
5447 	},
5448 	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5449 		GP_2_31_FN, FN_IP6_7_6,
5450 		GP_2_30_FN, FN_IP6_5_3,
5451 		GP_2_29_FN, FN_IP6_2_0,
5452 		GP_2_28_FN, FN_AUDIO_CLKA,
5453 		GP_2_27_FN, FN_IP5_31_29,
5454 		GP_2_26_FN, FN_IP5_28_26,
5455 		GP_2_25_FN, FN_IP5_25_24,
5456 		GP_2_24_FN, FN_IP5_23_22,
5457 		GP_2_23_FN, FN_IP5_21_20,
5458 		GP_2_22_FN, FN_IP5_19_17,
5459 		GP_2_21_FN, FN_IP5_16_15,
5460 		GP_2_20_FN, FN_IP5_14_12,
5461 		GP_2_19_FN, FN_IP5_11_9,
5462 		GP_2_18_FN, FN_IP5_8_6,
5463 		GP_2_17_FN, FN_IP5_5_3,
5464 		GP_2_16_FN, FN_IP5_2_0,
5465 		GP_2_15_FN, FN_IP4_30_28,
5466 		GP_2_14_FN, FN_IP4_27_26,
5467 		GP_2_13_FN, FN_IP4_25_24,
5468 		GP_2_12_FN, FN_IP4_23_22,
5469 		GP_2_11_FN, FN_IP4_21,
5470 		GP_2_10_FN, FN_IP4_20,
5471 		GP_2_9_FN, FN_IP4_19,
5472 		GP_2_8_FN, FN_IP4_18_16,
5473 		GP_2_7_FN, FN_IP4_15_13,
5474 		GP_2_6_FN, FN_IP4_12_10,
5475 		GP_2_5_FN, FN_IP4_9_8,
5476 		GP_2_4_FN, FN_IP4_7_5,
5477 		GP_2_3_FN, FN_IP4_4_2,
5478 		GP_2_2_FN, FN_IP4_1_0,
5479 		GP_2_1_FN, FN_IP3_30_28,
5480 		GP_2_0_FN, FN_IP3_27_25 }
5481 	},
5482 	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5483 		GP_3_31_FN, FN_IP9_18_17,
5484 		GP_3_30_FN, FN_IP9_16,
5485 		GP_3_29_FN, FN_IP9_15_13,
5486 		GP_3_28_FN, FN_IP9_12,
5487 		GP_3_27_FN, FN_IP9_11,
5488 		GP_3_26_FN, FN_IP9_10_8,
5489 		GP_3_25_FN, FN_IP9_7,
5490 		GP_3_24_FN, FN_IP9_6,
5491 		GP_3_23_FN, FN_IP9_5_3,
5492 		GP_3_22_FN, FN_IP9_2_0,
5493 		GP_3_21_FN, FN_IP8_30_28,
5494 		GP_3_20_FN, FN_IP8_27_26,
5495 		GP_3_19_FN, FN_IP8_25_24,
5496 		GP_3_18_FN, FN_IP8_23_21,
5497 		GP_3_17_FN, FN_IP8_20_18,
5498 		GP_3_16_FN, FN_IP8_17_15,
5499 		GP_3_15_FN, FN_IP8_14_12,
5500 		GP_3_14_FN, FN_IP8_11_9,
5501 		GP_3_13_FN, FN_IP8_8_6,
5502 		GP_3_12_FN, FN_IP8_5_3,
5503 		GP_3_11_FN, FN_IP8_2_0,
5504 		GP_3_10_FN, FN_IP7_29_27,
5505 		GP_3_9_FN, FN_IP7_26_24,
5506 		GP_3_8_FN, FN_IP7_23_21,
5507 		GP_3_7_FN, FN_IP7_20_19,
5508 		GP_3_6_FN, FN_IP7_18_17,
5509 		GP_3_5_FN, FN_IP7_16_15,
5510 		GP_3_4_FN, FN_IP7_14_13,
5511 		GP_3_3_FN, FN_IP7_12_11,
5512 		GP_3_2_FN, FN_IP7_10_9,
5513 		GP_3_1_FN, FN_IP7_8_6,
5514 		GP_3_0_FN, FN_IP7_5_3 }
5515 	},
5516 	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5517 		GP_4_31_FN, FN_IP15_5_4,
5518 		GP_4_30_FN, FN_IP15_3_2,
5519 		GP_4_29_FN, FN_IP15_1_0,
5520 		GP_4_28_FN, FN_IP11_8_6,
5521 		GP_4_27_FN, FN_IP11_5_3,
5522 		GP_4_26_FN, FN_IP11_2_0,
5523 		GP_4_25_FN, FN_IP10_31_29,
5524 		GP_4_24_FN, FN_IP10_28_27,
5525 		GP_4_23_FN, FN_IP10_26_25,
5526 		GP_4_22_FN, FN_IP10_24_22,
5527 		GP_4_21_FN, FN_IP10_21_19,
5528 		GP_4_20_FN, FN_IP10_18_17,
5529 		GP_4_19_FN, FN_IP10_16_15,
5530 		GP_4_18_FN, FN_IP10_14_12,
5531 		GP_4_17_FN, FN_IP10_11_9,
5532 		GP_4_16_FN, FN_IP10_8_6,
5533 		GP_4_15_FN, FN_IP10_5_3,
5534 		GP_4_14_FN, FN_IP10_2_0,
5535 		GP_4_13_FN, FN_IP9_31_29,
5536 		GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5537 		GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5538 		GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5539 		GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5540 		GP_4_8_FN, FN_IP9_28_27,
5541 		GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5542 		GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5543 		GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5544 		GP_4_4_FN, FN_IP9_26_25,
5545 		GP_4_3_FN, FN_IP9_24_23,
5546 		GP_4_2_FN, FN_IP9_22_21,
5547 		GP_4_1_FN, FN_IP9_20_19,
5548 		GP_4_0_FN, FN_VI0_CLK }
5549 	},
5550 	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5551 		GP_5_31_FN, FN_IP3_24_22,
5552 		GP_5_30_FN, FN_IP13_9_7,
5553 		GP_5_29_FN, FN_IP13_6_5,
5554 		GP_5_28_FN, FN_IP13_4_3,
5555 		GP_5_27_FN, FN_IP13_2_0,
5556 		GP_5_26_FN, FN_IP12_29_27,
5557 		GP_5_25_FN, FN_IP12_26_24,
5558 		GP_5_24_FN, FN_IP12_23_22,
5559 		GP_5_23_FN, FN_IP12_21_20,
5560 		GP_5_22_FN, FN_IP12_19_18,
5561 		GP_5_21_FN, FN_IP12_17_16,
5562 		GP_5_20_FN, FN_IP12_15_13,
5563 		GP_5_19_FN, FN_IP12_12_10,
5564 		GP_5_18_FN, FN_IP12_9_7,
5565 		GP_5_17_FN, FN_IP12_6_4,
5566 		GP_5_16_FN, FN_IP12_3_2,
5567 		GP_5_15_FN, FN_IP12_1_0,
5568 		GP_5_14_FN, FN_IP11_31_30,
5569 		GP_5_13_FN, FN_IP11_29_28,
5570 		GP_5_12_FN, FN_IP11_27,
5571 		GP_5_11_FN, FN_IP11_26,
5572 		GP_5_10_FN, FN_IP11_25,
5573 		GP_5_9_FN, FN_IP11_24,
5574 		GP_5_8_FN, FN_IP11_23,
5575 		GP_5_7_FN, FN_IP11_22,
5576 		GP_5_6_FN, FN_IP11_21,
5577 		GP_5_5_FN, FN_IP11_20,
5578 		GP_5_4_FN, FN_IP11_19,
5579 		GP_5_3_FN, FN_IP11_18_17,
5580 		GP_5_2_FN, FN_IP11_16_15,
5581 		GP_5_1_FN, FN_IP11_14_12,
5582 		GP_5_0_FN, FN_IP11_11_9 }
5583 	},
5584 	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5585 		GP_6_31_FN, FN_DU0_DOTCLKIN,
5586 		GP_6_30_FN, FN_USB1_OVC,
5587 		GP_6_29_FN, FN_IP14_31_29,
5588 		GP_6_28_FN, FN_IP14_28_26,
5589 		GP_6_27_FN, FN_IP14_25_23,
5590 		GP_6_26_FN, FN_IP14_22_20,
5591 		GP_6_25_FN, FN_IP14_19_17,
5592 		GP_6_24_FN, FN_IP14_16_14,
5593 		GP_6_23_FN, FN_IP14_13_11,
5594 		GP_6_22_FN, FN_IP14_10_8,
5595 		GP_6_21_FN, FN_IP14_7,
5596 		GP_6_20_FN, FN_IP14_6,
5597 		GP_6_19_FN, FN_IP14_5,
5598 		GP_6_18_FN, FN_IP14_4,
5599 		GP_6_17_FN, FN_IP14_3,
5600 		GP_6_16_FN, FN_IP14_2,
5601 		GP_6_15_FN, FN_IP14_1_0,
5602 		GP_6_14_FN, FN_IP13_30_28,
5603 		GP_6_13_FN, FN_IP13_27,
5604 		GP_6_12_FN, FN_IP13_26,
5605 		GP_6_11_FN, FN_IP13_25,
5606 		GP_6_10_FN, FN_IP13_24_23,
5607 		GP_6_9_FN, FN_IP13_22,
5608 		GP_6_8_FN, FN_SD1_CLK,
5609 		GP_6_7_FN, FN_IP13_21_19,
5610 		GP_6_6_FN, FN_IP13_18_16,
5611 		GP_6_5_FN, FN_IP13_15,
5612 		GP_6_4_FN, FN_IP13_14,
5613 		GP_6_3_FN, FN_IP13_13,
5614 		GP_6_2_FN, FN_IP13_12,
5615 		GP_6_1_FN, FN_IP13_11,
5616 		GP_6_0_FN, FN_IP13_10 }
5617 	},
5618 	{ PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5619 		0, 0,
5620 		0, 0,
5621 		0, 0,
5622 		0, 0,
5623 		0, 0,
5624 		0, 0,
5625 		GP_7_25_FN, FN_USB1_PWEN,
5626 		GP_7_24_FN, FN_USB0_OVC,
5627 		GP_7_23_FN, FN_USB0_PWEN,
5628 		GP_7_22_FN, FN_IP15_14_12,
5629 		GP_7_21_FN, FN_IP15_11_9,
5630 		GP_7_20_FN, FN_IP15_8_6,
5631 		GP_7_19_FN, FN_IP7_2_0,
5632 		GP_7_18_FN, FN_IP6_29_27,
5633 		GP_7_17_FN, FN_IP6_26_24,
5634 		GP_7_16_FN, FN_IP6_23_21,
5635 		GP_7_15_FN, FN_IP6_20_19,
5636 		GP_7_14_FN, FN_IP6_18_16,
5637 		GP_7_13_FN, FN_IP6_15_14,
5638 		GP_7_12_FN, FN_IP6_13_12,
5639 		GP_7_11_FN, FN_IP6_11_10,
5640 		GP_7_10_FN, FN_IP6_9_8,
5641 		GP_7_9_FN, FN_IP16_11_10,
5642 		GP_7_8_FN, FN_IP16_9_8,
5643 		GP_7_7_FN, FN_IP16_7_6,
5644 		GP_7_6_FN, FN_IP16_5_3,
5645 		GP_7_5_FN, FN_IP16_2_0,
5646 		GP_7_4_FN, FN_IP15_29_27,
5647 		GP_7_3_FN, FN_IP15_26_24,
5648 		GP_7_2_FN, FN_IP15_23_21,
5649 		GP_7_1_FN, FN_IP15_20_18,
5650 		GP_7_0_FN, FN_IP15_17_15 }
5651 	},
5652 	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5653 			     1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5654 			     1, 1, 1, 1, 1, 1, 1, 1) {
5655 		/* IP0_31 [1] */
5656 		0, 0,
5657 		/* IP0_30_29 [2] */
5658 		FN_A6, FN_MSIOF1_SCK,
5659 		0, 0,
5660 		/* IP0_28_27 [2] */
5661 		FN_A5, FN_MSIOF0_RXD_B,
5662 		0, 0,
5663 		/* IP0_26_25 [2] */
5664 		FN_A4, FN_MSIOF0_TXD_B,
5665 		0, 0,
5666 		/* IP0_24_23 [2] */
5667 		FN_A3, FN_MSIOF0_SS2_B,
5668 		0, 0,
5669 		/* IP0_22_21 [2] */
5670 		FN_A2, FN_MSIOF0_SS1_B,
5671 		0, 0,
5672 		/* IP0_20_19 [2] */
5673 		FN_A1, FN_MSIOF0_SYNC_B,
5674 		0, 0,
5675 		/* IP0_18_16 [3] */
5676 		FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
5677 		0, 0, 0,
5678 		/* IP0_15 [1] */
5679 		FN_D15, 0,
5680 		/* IP0_14 [1] */
5681 		FN_D14, 0,
5682 		/* IP0_13 [1] */
5683 		FN_D13, 0,
5684 		/* IP0_12 [1] */
5685 		FN_D12, 0,
5686 		/* IP0_11 [1] */
5687 		FN_D11, 0,
5688 		/* IP0_10 [1] */
5689 		FN_D10, 0,
5690 		/* IP0_9 [1] */
5691 		FN_D9, 0,
5692 		/* IP0_8 [1] */
5693 		FN_D8, 0,
5694 		/* IP0_7 [1] */
5695 		FN_D7, 0,
5696 		/* IP0_6 [1] */
5697 		FN_D6, 0,
5698 		/* IP0_5 [1] */
5699 		FN_D5, 0,
5700 		/* IP0_4 [1] */
5701 		FN_D4, 0,
5702 		/* IP0_3 [1] */
5703 		FN_D3, 0,
5704 		/* IP0_2 [1] */
5705 		FN_D2, 0,
5706 		/* IP0_1 [1] */
5707 		FN_D1, 0,
5708 		/* IP0_0 [1] */
5709 		FN_D0, 0, }
5710 	},
5711 	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5712 			     3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5713 		/* IP1_31_29 [3] */
5714 		FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5715 		0, 0, 0,
5716 		/* IP1_28_26 [3] */
5717 		FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5718 		0, 0, 0, 0,
5719 		/* IP1_25_23 [3] */
5720 		FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5721 		0, 0, 0,
5722 		/* IP1_22_20 [3] */
5723 		FN_A15, FN_BPFCLK_C,
5724 		0, 0, 0, 0, 0, 0,
5725 		/* IP1_19_17 [3] */
5726 		FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5727 		0, 0, 0,
5728 		/* IP1_16_14 [3] */
5729 		FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5730 		0, 0, 0, 0,
5731 		/* IP1_13_11 [3] */
5732 		FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
5733 		0, 0, 0, 0,
5734 		/* IP1_10_8 [3] */
5735 		FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
5736 		0, 0, 0, 0,
5737 		/* IP1_7_6 [2] */
5738 		FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5739 		/* IP1_5_4 [2] */
5740 		FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5741 		/* IP1_3_2 [2] */
5742 		FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5743 		/* IP1_1_0 [2] */
5744 		FN_A7, FN_MSIOF1_SYNC,
5745 		0, 0, }
5746 	},
5747 	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5748 			     2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5749 		/* IP2_31_30 [2] */
5750 		0, 0, 0, 0,
5751 		/* IP2_29_27 [3] */
5752 		FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5753 		FN_ATAG0_N, 0, FN_EX_WAIT1,
5754 		0, 0,
5755 		/* IP2_26_25 [2] */
5756 		FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5757 		/* IP2_24_23 [2] */
5758 		FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5759 		/* IP2_22_21 [2] */
5760 		FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5761 		/* IP2_20_19 [2] */
5762 		FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5763 		/* IP2_18_16 [3] */
5764 		FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5765 		0, 0,
5766 		/* IP2_15_13 [3] */
5767 		FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5768 		0, 0, 0,
5769 		/* IP2_12_10 [3] */
5770 		FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5771 		0, 0, 0,
5772 		/* IP2_9_7 [3] */
5773 		FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5774 		0, 0, 0,
5775 		/* IP2_6_5 [2] */
5776 		FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5777 		/* IP2_4_3 [2] */
5778 		FN_A20, FN_SPCLK, 0, 0,
5779 		/* IP2_2_0 [3] */
5780 		FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5781 		FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
5782 	},
5783 	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5784 			     1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5785 		/* IP3_31 [1] */
5786 		0, 0,
5787 		/* IP3_30_28 [3] */
5788 		FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5789 		FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5790 		0, 0, 0,
5791 		/* IP3_27_25 [3] */
5792 		FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5793 		FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5794 		0, 0, 0,
5795 		/* IP3_24_22 [3] */
5796 		FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5797 		FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5798 		/* IP3_21_20 [2] */
5799 		FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5800 		/* IP3_19_18 [2] */
5801 		FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5802 		/* IP3_17_16 [2] */
5803 		FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5804 		/* IP3_15_14 [2] */
5805 		FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5806 		/* IP3_13_12 [2] */
5807 		FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5808 		/* IP3_11_9 [3] */
5809 		FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5810 		0, 0, 0,
5811 		/* IP3_8_6 [3] */
5812 		FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5813 		FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5814 		/* IP3_5_3 [3] */
5815 		FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5816 		FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5817 		/* IP3_2_0 [3] */
5818 		FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5819 		0, 0, 0, }
5820 	},
5821 	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5822 			     1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5823 		/* IP4_31 [1] */
5824 		0, 0,
5825 		/* IP4_30_28 [3] */
5826 		FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5827 		FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5828 		0, 0,
5829 		/* IP4_27_26 [2] */
5830 		FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5831 		/* IP4_25_24 [2] */
5832 		FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5833 		/* IP4_23_22 [2] */
5834 		FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5835 		/* IP4_21 [1] */
5836 		FN_SSI_SDATA3, 0,
5837 		/* IP4_20 [1] */
5838 		FN_SSI_WS34, 0,
5839 		/* IP4_19 [1] */
5840 		FN_SSI_SCK34, 0,
5841 		/* IP4_18_16 [3] */
5842 		FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5843 		0, 0, 0, 0,
5844 		/* IP4_15_13 [3] */
5845 		FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
5846 		FN_GLO_Q1_D, FN_HCTS1_N_E,
5847 		0, 0,
5848 		/* IP4_12_10 [3] */
5849 		FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5850 		0, 0, 0,
5851 		/* IP4_9_8 [2] */
5852 		FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
5853 		/* IP4_7_5 [3] */
5854 		FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
5855 		FN_GLO_I1_D, 0, 0, 0,
5856 		/* IP4_4_2 [3] */
5857 		FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
5858 		FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5859 		0, 0, 0,
5860 		/* IP4_1_0 [2] */
5861 		FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
5862 	},
5863 	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5864 			     3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5865 		/* IP5_31_29 [3] */
5866 		FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5867 		0, 0, 0, 0, 0,
5868 		/* IP5_28_26 [3] */
5869 		FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5870 		0, 0, 0, 0,
5871 		/* IP5_25_24 [2] */
5872 		FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5873 		/* IP5_23_22 [2] */
5874 		FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5875 		/* IP5_21_20 [2] */
5876 		FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5877 		/* IP5_19_17 [3] */
5878 		FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5879 		0, 0, 0, 0,
5880 		/* IP5_16_15 [2] */
5881 		FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5882 		/* IP5_14_12 [3] */
5883 		FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5884 		0, 0, 0, 0,
5885 		/* IP5_11_9 [3] */
5886 		FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5887 		0, 0, 0, 0,
5888 		/* IP5_8_6 [3] */
5889 		FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5890 		FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5891 		0, 0,
5892 		/* IP5_5_3 [3] */
5893 		FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5894 		FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5895 		0, 0,
5896 		/* IP5_2_0 [3] */
5897 		FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5898 		FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5899 		0, 0, }
5900 	},
5901 	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5902 			     2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5903 		/* IP6_31_30 [2] */
5904 		0, 0, 0, 0,
5905 		/* IP6_29_27 [3] */
5906 		FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5907 		FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5908 		0, 0, 0,
5909 		/* IP6_26_24 [3] */
5910 		FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5911 		FN_GPS_CLK_C, FN_GPS_CLK_D,
5912 		0, 0, 0,
5913 		/* IP6_23_21 [3] */
5914 		FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5915 		FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
5916 		0, 0, 0,
5917 		/* IP6_20_19 [2] */
5918 		FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
5919 		/* IP6_18_16 [3] */
5920 		FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
5921 		FN_INTC_IRQ4_N,	0, 0, 0,
5922 		/* IP6_15_14 [2] */
5923 		FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5924 		/* IP6_13_12 [2] */
5925 		FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5926 		/* IP6_11_10 [2] */
5927 		FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5928 		/* IP6_9_8 [2] */
5929 		FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5930 		/* IP6_7_6 [2] */
5931 		FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5932 		/* IP6_5_3 [3] */
5933 		FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5934 		FN_SCIFA2_RXD, FN_FMIN_E,
5935 		0, 0,
5936 		/* IP6_2_0 [3] */
5937 		FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5938 		FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
5939 		0, 0, }
5940 	},
5941 	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5942 			     2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5943 		/* IP7_31_30 [2] */
5944 		0, 0, 0, 0,
5945 		/* IP7_29_27 [3] */
5946 		FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5947 		FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5948 		0, 0,
5949 		/* IP7_26_24 [3] */
5950 		FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
5951 		FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
5952 		0, 0,
5953 		/* IP7_23_21 [3] */
5954 		FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
5955 		FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
5956 		0, 0,
5957 		/* IP7_20_19 [2] */
5958 		FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
5959 		/* IP7_18_17 [2] */
5960 		FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
5961 		/* IP7_16_15 [2] */
5962 		FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
5963 		/* IP7_14_13 [2] */
5964 		FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
5965 		/* IP7_12_11 [2] */
5966 		FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
5967 		/* IP7_10_9 [2] */
5968 		FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
5969 		/* IP7_8_6 [3] */
5970 		FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
5971 		FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
5972 		0, 0,
5973 		/* IP7_5_3 [3] */
5974 		FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
5975 		FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
5976 		0, 0,
5977 		/* IP7_2_0 [3] */
5978 		FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
5979 		FN_SCIF_CLK_B, FN_GPS_MAG_D,
5980 		0, 0, }
5981 	},
5982 	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5983 			     1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
5984 		/* IP8_31 [1] */
5985 		0, 0,
5986 		/* IP8_30_28 [3] */
5987 		FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
5988 		0, 0, 0,
5989 		/* IP8_27_26 [2] */
5990 		FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
5991 		/* IP8_25_24 [2] */
5992 		FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
5993 		/* IP8_23_21 [3] */
5994 		FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
5995 		FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
5996 		0, 0,
5997 		/* IP8_20_18 [3] */
5998 		FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
5999 		FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
6000 		0, 0,
6001 		/* IP8_17_15 [3] */
6002 		FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
6003 		FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
6004 		0, 0,
6005 		/* IP8_14_12 [3] */
6006 		FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
6007 		FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
6008 		0, 0, 0,
6009 		/* IP8_11_9 [3] */
6010 		FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
6011 		FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
6012 		0, 0, 0,
6013 		/* IP8_8_6 [3] */
6014 		FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
6015 		FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
6016 		0, 0,
6017 		/* IP8_5_3 [3] */
6018 		FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
6019 		FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
6020 		0, 0,
6021 		/* IP8_2_0 [3] */
6022 		FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6023 		0, 0, 0, }
6024 	},
6025 	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6026 			     3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
6027 		/* IP9_31_29 [3] */
6028 		FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
6029 		FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6030 		/* IP9_28_27 [2] */
6031 		FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6032 		/* IP9_26_25 [2] */
6033 		FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
6034 		/* IP9_24_23 [2] */
6035 		FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
6036 		/* IP9_22_21 [2] */
6037 		FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
6038 		/* IP9_20_19 [2] */
6039 		FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
6040 		/* IP9_18_17 [2] */
6041 		FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6042 		/* IP9_16 [1] */
6043 		FN_DU1_DISP, FN_QPOLA,
6044 		/* IP9_15_13 [3] */
6045 		FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
6046 		FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
6047 		0, 0, 0,
6048 		/* IP9_12 [1] */
6049 		FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
6050 		/* IP9_11 [1] */
6051 		FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
6052 		/* IP9_10_8 [3] */
6053 		FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
6054 		FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
6055 		0, 0,
6056 		/* IP9_7 [1] */
6057 		FN_DU1_DOTCLKOUT0, FN_QCLK,
6058 		/* IP9_6 [1] */
6059 		FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
6060 		/* IP9_5_3 [3] */
6061 		FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
6062 		FN_SCIF3_SCK, FN_SCIFA3_SCK,
6063 		0, 0, 0,
6064 		/* IP9_2_0 [3] */
6065 		FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
6066 		0, 0, 0, }
6067 	},
6068 	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6069 			     3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
6070 		/* IP10_31_29 [3] */
6071 		FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
6072 		0, 0, 0,
6073 		/* IP10_28_27 [2] */
6074 		FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
6075 		/* IP10_26_25 [2] */
6076 		FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
6077 		/* IP10_24_22 [3] */
6078 		FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
6079 		0, 0, 0,
6080 		/* IP10_21_19 [3] */
6081 		FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
6082 		FN_TS_SDATA0_C, FN_ATACS11_N,
6083 		0, 0, 0,
6084 		/* IP10_18_17 [2] */
6085 		FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6086 		/* IP10_16_15 [2] */
6087 		FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6088 		/* IP10_14_12 [3] */
6089 		FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
6090 		FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6091 		/* IP10_11_9 [3] */
6092 		FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
6093 		FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
6094 		0, 0,
6095 		/* IP10_8_6 [3] */
6096 		FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
6097 		FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6098 		/* IP10_5_3 [3] */
6099 		FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
6100 		FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6101 		/* IP10_2_0 [3] */
6102 		FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
6103 		FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
6104 	},
6105 	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6106 			     2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
6107 			     3, 3, 3, 3, 3) {
6108 		/* IP11_31_30 [2] */
6109 		FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6110 		/* IP11_29_28 [2] */
6111 		FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6112 		/* IP11_27 [1] */
6113 		FN_VI1_DATA7, FN_AVB_MDC,
6114 		/* IP11_26 [1] */
6115 		FN_VI1_DATA6, FN_AVB_MAGIC,
6116 		/* IP11_25 [1] */
6117 		FN_VI1_DATA5, FN_AVB_RX_DV,
6118 		/* IP11_24 [1] */
6119 		FN_VI1_DATA4, FN_AVB_MDIO,
6120 		/* IP11_23 [1] */
6121 		FN_VI1_DATA3, FN_AVB_RX_ER,
6122 		/* IP11_22 [1] */
6123 		FN_VI1_DATA2, FN_AVB_RXD7,
6124 		/* IP11_21 [1] */
6125 		FN_VI1_DATA1, FN_AVB_RXD6,
6126 		/* IP11_20 [1] */
6127 		FN_VI1_DATA0, FN_AVB_RXD5,
6128 		/* IP11_19 [1] */
6129 		FN_VI1_CLK, FN_AVB_RXD4,
6130 		/* IP11_18_17 [2] */
6131 		FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6132 		/* IP11_16_15 [2] */
6133 		FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6134 		/* IP11_14_12 [3] */
6135 		FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6136 		FN_RX4_B, FN_SCIFA4_RXD_B,
6137 		0, 0, 0,
6138 		/* IP11_11_9 [3] */
6139 		FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6140 		FN_TX4_B, FN_SCIFA4_TXD_B,
6141 		0, 0, 0,
6142 		/* IP11_8_6 [3] */
6143 		FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6144 		FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6145 		/* IP11_5_3 [3] */
6146 		FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
6147 		0, 0, 0,
6148 		/* IP11_2_0 [3] */
6149 		FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
6150 		FN_I2C1_SDA_D, 0, 0, 0, }
6151 	},
6152 	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6153 			     2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
6154 		/* IP12_31_30 [2] */
6155 		0, 0, 0, 0,
6156 		/* IP12_29_27 [3] */
6157 		FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6158 		FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6159 		0, 0, 0,
6160 		/* IP12_26_24 [3] */
6161 		FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6162 		FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6163 		0, 0, 0,
6164 		/* IP12_23_22 [2] */
6165 		FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6166 		/* IP12_21_20 [2] */
6167 		FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6168 		/* IP12_19_18 [2] */
6169 		FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6170 		/* IP12_17_16 [2] */
6171 		FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6172 		/* IP12_15_13 [3] */
6173 		FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6174 		FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6175 		0, 0, 0,
6176 		/* IP12_12_10 [3] */
6177 		FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6178 		FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6179 		0, 0, 0,
6180 		/* IP12_9_7 [3] */
6181 		FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6182 		FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
6183 		0, 0, 0,
6184 		/* IP12_6_4 [3] */
6185 		FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6186 		FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
6187 		0, 0, 0,
6188 		/* IP12_3_2 [2] */
6189 		FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
6190 		/* IP12_1_0 [2] */
6191 		FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
6192 	},
6193 	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6194 			     1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
6195 			     3, 2, 2, 3) {
6196 		/* IP13_31 [1] */
6197 		0, 0,
6198 		/* IP13_30_28 [3] */
6199 		FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
6200 		0, 0, 0, 0,
6201 		/* IP13_27 [1] */
6202 		FN_SD1_DATA3, FN_IERX_B,
6203 		/* IP13_26 [1] */
6204 		FN_SD1_DATA2, FN_IECLK_B,
6205 		/* IP13_25 [1] */
6206 		FN_SD1_DATA1, FN_IETX_B,
6207 		/* IP13_24_23 [2] */
6208 		FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6209 		/* IP13_22 [1] */
6210 		FN_SD1_CMD, FN_REMOCON_B,
6211 		/* IP13_21_19 [3] */
6212 		FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6213 		FN_SCIFA5_RXD_B, FN_RX3_C,
6214 		0, 0,
6215 		/* IP13_18_16 [3] */
6216 		FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6217 		FN_SCIFA5_TXD_B, FN_TX3_C,
6218 		0, 0,
6219 		/* IP13_15 [1] */
6220 		FN_SD0_DATA3, FN_SSL_B,
6221 		/* IP13_14 [1] */
6222 		FN_SD0_DATA2, FN_IO3_B,
6223 		/* IP13_13 [1] */
6224 		FN_SD0_DATA1, FN_IO2_B,
6225 		/* IP13_12 [1] */
6226 		FN_SD0_DATA0, FN_MISO_IO1_B,
6227 		/* IP13_11 [1] */
6228 		FN_SD0_CMD, FN_MOSI_IO0_B,
6229 		/* IP13_10 [1] */
6230 		FN_SD0_CLK, FN_SPCLK_B,
6231 		/* IP13_9_7 [3] */
6232 		FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6233 		FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6234 		0, 0, 0,
6235 		/* IP13_6_5 [2] */
6236 		FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6237 		/* IP13_4_3 [2] */
6238 		FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6239 		/* IP13_2_0 [3] */
6240 		FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6241 		FN_ADICLK_B, FN_MSIOF0_SS1_C,
6242 		0, 0, 0, }
6243 	},
6244 	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6245 			     3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6246 		/* IP14_31_29 [3] */
6247 		FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6248 		FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6249 		/* IP14_28_26 [3] */
6250 		FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6251 		FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6252 		/* IP14_25_23 [3] */
6253 		FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6254 		0, 0, 0,
6255 		/* IP14_22_20 [3] */
6256 		FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6257 		0, 0, 0,
6258 		/* IP14_19_17 [3] */
6259 		FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6260 		FN_VI1_CLKENB_C, FN_VI1_G1_B,
6261 		0, 0,
6262 		/* IP14_16_14 [3] */
6263 		FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6264 		FN_VI1_CLK_C, FN_VI1_G0_B,
6265 		0, 0,
6266 		/* IP14_13_11 [3] */
6267 		FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6268 		0, 0, 0,
6269 		/* IP14_10_8 [3] */
6270 		FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6271 		0, 0, 0,
6272 		/* IP14_7 [1] */
6273 		FN_SD2_DATA3, FN_MMC_D3,
6274 		/* IP14_6 [1] */
6275 		FN_SD2_DATA2, FN_MMC_D2,
6276 		/* IP14_5 [1] */
6277 		FN_SD2_DATA1, FN_MMC_D1,
6278 		/* IP14_4 [1] */
6279 		FN_SD2_DATA0, FN_MMC_D0,
6280 		/* IP14_3 [1] */
6281 		FN_SD2_CMD, FN_MMC_CMD,
6282 		/* IP14_2 [1] */
6283 		FN_SD2_CLK, FN_MMC_CLK,
6284 		/* IP14_1_0 [2] */
6285 		FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
6286 	},
6287 	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6288 			     2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6289 		/* IP15_31_30 [2] */
6290 		0, 0, 0, 0,
6291 		/* IP15_29_27 [3] */
6292 		FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6293 		FN_CAN0_TX_B, FN_VI1_DATA5_C,
6294 		0, 0,
6295 		/* IP15_26_24 [3] */
6296 		FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6297 		FN_CAN0_RX_B, FN_VI1_DATA4_C,
6298 		0, 0,
6299 		/* IP15_23_21 [3] */
6300 		FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6301 		FN_TCLK2, FN_VI1_DATA3_C, 0,
6302 		/* IP15_20_18 [3] */
6303 		FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6304 		0, 0, 0,
6305 		/* IP15_17_15 [3] */
6306 		FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6307 		FN_TCLK1, FN_VI1_DATA1_C,
6308 		0, 0,
6309 		/* IP15_14_12 [3] */
6310 		FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6311 		FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6312 		0, 0,
6313 		/* IP15_11_9 [3] */
6314 		FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6315 		FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6316 		0, 0,
6317 		/* IP15_8_6 [3] */
6318 		FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6319 		FN_PWM5_B, FN_SCIFA3_TXD_C,
6320 		0, 0, 0,
6321 		/* IP15_5_4 [2] */
6322 		FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6323 		/* IP15_3_2 [2] */
6324 		FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6325 		/* IP15_1_0 [2] */
6326 		FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
6327 	},
6328 	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6329 			     4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6330 		/* IP16_31_28 [4] */
6331 		0, 0, 0, 0, 0, 0, 0, 0,
6332 		0, 0, 0, 0, 0, 0, 0, 0,
6333 		/* IP16_27_24 [4] */
6334 		0, 0, 0, 0, 0, 0, 0, 0,
6335 		0, 0, 0, 0, 0, 0, 0, 0,
6336 		/* IP16_23_20 [4] */
6337 		0, 0, 0, 0, 0, 0, 0, 0,
6338 		0, 0, 0, 0, 0, 0, 0, 0,
6339 		/* IP16_19_16 [4] */
6340 		0, 0, 0, 0, 0, 0, 0, 0,
6341 		0, 0, 0, 0, 0, 0, 0, 0,
6342 		/* IP16_15_12 [4] */
6343 		0, 0, 0, 0, 0, 0, 0, 0,
6344 		0, 0, 0, 0, 0, 0, 0, 0,
6345 		/* IP16_11_10 [2] */
6346 		FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6347 		/* IP16_9_8 [2] */
6348 		FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6349 		/* IP16_7_6 [2] */
6350 		FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6351 		/* IP16_5_3 [3] */
6352 		FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6353 		FN_GLO_SS_C, FN_VI1_DATA7_C,
6354 		0, 0, 0,
6355 		/* IP16_2_0 [3] */
6356 		FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6357 		FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6358 		0, 0, 0, }
6359 	},
6360 	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6361 			     1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6362 			     3, 2, 2, 2, 1, 2, 2, 2) {
6363 		/* RESERVED [1] */
6364 		0, 0,
6365 		/* SEL_SCIF1 [2] */
6366 		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6367 		/* SEL_SCIFB [2] */
6368 		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6369 		/* SEL_SCIFB2 [2] */
6370 		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6371 		FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6372 		/* SEL_SCIFB1 [3] */
6373 		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6374 		FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6375 		0, 0, 0, 0,
6376 		/* SEL_SCIFA1 [2] */
6377 		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6378 		/* SEL_SSI9 [1] */
6379 		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6380 		/* SEL_SCFA [1] */
6381 		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6382 		/* SEL_QSP [1] */
6383 		FN_SEL_QSP_0, FN_SEL_QSP_1,
6384 		/* SEL_SSI7 [1] */
6385 		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6386 		/* SEL_HSCIF1 [3] */
6387 		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6388 		FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6389 		0, 0, 0,
6390 		/* RESERVED [2] */
6391 		0, 0, 0, 0,
6392 		/* SEL_VI1 [2] */
6393 		FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6394 		/* RESERVED [2] */
6395 		0, 0, 0, 0,
6396 		/* SEL_TMU [1] */
6397 		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6398 		/* SEL_LBS [2] */
6399 		FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6400 		/* SEL_TSIF0 [2] */
6401 		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6402 		/* SEL_SOF0 [2] */
6403 		FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
6404 	},
6405 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6406 			     3, 1, 1, 3, 2, 1, 1, 2, 2,
6407 			     1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6408 		/* SEL_SCIF0 [3] */
6409 		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6410 		FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6411 		0, 0, 0,
6412 		/* RESERVED [1] */
6413 		0, 0,
6414 		/* SEL_SCIF [1] */
6415 		FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6416 		/* SEL_CAN0 [3] */
6417 		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6418 		FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6419 		0, 0,
6420 		/* SEL_CAN1 [2] */
6421 		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6422 		/* RESERVED [1] */
6423 		0, 0,
6424 		/* SEL_SCIFA2 [1] */
6425 		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6426 		/* SEL_SCIF4 [2] */
6427 		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6428 		/* RESERVED [2] */
6429 		0, 0, 0, 0,
6430 		/* SEL_ADG [1] */
6431 		FN_SEL_ADG_0, FN_SEL_ADG_1,
6432 		/* SEL_FM [3] */
6433 		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6434 		FN_SEL_FM_3, FN_SEL_FM_4,
6435 		0, 0, 0,
6436 		/* SEL_SCIFA5 [2] */
6437 		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6438 		/* RESERVED [1] */
6439 		0, 0,
6440 		/* SEL_GPS [2] */
6441 		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6442 		/* SEL_SCIFA4 [2] */
6443 		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6444 		/* SEL_SCIFA3 [2] */
6445 		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6446 		/* SEL_SIM [1] */
6447 		FN_SEL_SIM_0, FN_SEL_SIM_1,
6448 		/* RESERVED [1] */
6449 		0, 0,
6450 		/* SEL_SSI8 [1] */
6451 		FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
6452 	},
6453 	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6454 			     2, 2, 2, 2, 2, 2, 2, 2,
6455 			     1, 1, 2, 2, 3, 2, 2, 2, 1) {
6456 		/* SEL_HSCIF2 [2] */
6457 		FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6458 		FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6459 		/* SEL_CANCLK [2] */
6460 		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6461 		FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6462 		/* SEL_IIC1 [2] */
6463 		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6464 		/* SEL_IIC0 [2] */
6465 		FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6466 		/* SEL_I2C4 [2] */
6467 		FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6468 		/* SEL_I2C3 [2] */
6469 		FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
6470 		/* SEL_SCIF3 [2] */
6471 		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6472 		/* SEL_IEB [2] */
6473 		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6474 		/* SEL_MMC [1] */
6475 		FN_SEL_MMC_0, FN_SEL_MMC_1,
6476 		/* SEL_SCIF5 [1] */
6477 		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6478 		/* RESERVED [2] */
6479 		0, 0, 0, 0,
6480 		/* SEL_I2C2 [2] */
6481 		FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
6482 		/* SEL_I2C1 [3] */
6483 		FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
6484 		FN_SEL_I2C1_4,
6485 		0, 0, 0,
6486 		/* SEL_I2C0 [2] */
6487 		FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6488 		/* RESERVED [2] */
6489 		0, 0, 0, 0,
6490 		/* RESERVED [2] */
6491 		0, 0, 0, 0,
6492 		/* RESERVED [1] */
6493 		0, 0, }
6494 	},
6495 	{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6496 			     3, 2, 2, 1, 1, 1, 1, 3, 2,
6497 			     2, 3, 1, 1, 1, 2, 2, 2, 2) {
6498 		/* SEL_SOF1 [3] */
6499 		FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6500 		FN_SEL_SOF1_4,
6501 		0, 0, 0,
6502 		/* SEL_HSCIF0 [2] */
6503 		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6504 		/* SEL_DIS [2] */
6505 		FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6506 		/* RESERVED [1] */
6507 		0, 0,
6508 		/* SEL_RAD [1] */
6509 		FN_SEL_RAD_0, FN_SEL_RAD_1,
6510 		/* SEL_RCN [1] */
6511 		FN_SEL_RCN_0, FN_SEL_RCN_1,
6512 		/* SEL_RSP [1] */
6513 		FN_SEL_RSP_0, FN_SEL_RSP_1,
6514 		/* SEL_SCIF2 [3] */
6515 		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6516 		FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6517 		0, 0, 0,
6518 		/* RESERVED [2] */
6519 		0, 0, 0, 0,
6520 		/* RESERVED [2] */
6521 		0, 0, 0, 0,
6522 		/* SEL_SOF2 [3] */
6523 		FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6524 		FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6525 		0, 0, 0,
6526 		/* RESERVED [1] */
6527 		0, 0,
6528 		/* SEL_SSI1 [1] */
6529 		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6530 		/* SEL_SSI0 [1] */
6531 		FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6532 		/* SEL_SSP [2] */
6533 		FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6534 		/* RESERVED [2] */
6535 		0, 0, 0, 0,
6536 		/* RESERVED [2] */
6537 		0, 0, 0, 0,
6538 		/* RESERVED [2] */
6539 		0, 0, 0, 0, }
6540 	},
6541 	{ },
6542 };
6543 
6544 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6545 {
6546 	if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6547 		return -EINVAL;
6548 
6549 	*pocctrl = 0xe606008c;
6550 
6551 	return 31 - (pin & 0x1f);
6552 }
6553 
6554 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6555 	.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6556 };
6557 
6558 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6559 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6560 	.name = "r8a77910_pfc",
6561 	.ops = &r8a7791_pinmux_ops,
6562 	.unlock_reg = 0xe6060000, /* PMMR */
6563 
6564 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6565 
6566 	.pins = pinmux_pins,
6567 	.nr_pins = ARRAY_SIZE(pinmux_pins),
6568 	.groups = pinmux_groups.common,
6569 	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6570 		     ARRAY_SIZE(pinmux_groups.r8a779x),
6571 	.functions = pinmux_functions.common,
6572 	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6573 			ARRAY_SIZE(pinmux_functions.r8a779x),
6574 
6575 	.cfg_regs = pinmux_config_regs,
6576 
6577 	.pinmux_data = pinmux_data,
6578 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6579 };
6580 #endif
6581 
6582 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6583 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6584 	.name = "r8a77930_pfc",
6585 	.ops = &r8a7791_pinmux_ops,
6586 	.unlock_reg = 0xe6060000, /* PMMR */
6587 
6588 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6589 
6590 	.pins = pinmux_pins,
6591 	.nr_pins = ARRAY_SIZE(pinmux_pins),
6592 	.groups = pinmux_groups.common,
6593 	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6594 		     ARRAY_SIZE(pinmux_groups.r8a779x),
6595 	.functions = pinmux_functions.common,
6596 	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6597 			ARRAY_SIZE(pinmux_functions.r8a779x),
6598 
6599 	.cfg_regs = pinmux_config_regs,
6600 
6601 	.pinmux_data = pinmux_data,
6602 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6603 };
6604 #endif
6605