1 /* 2 * R8A7790 processor support 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * Copyright (C) 2013 Magnus Damm 6 * Copyright (C) 2012 Renesas Solutions Corp. 7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <dm/pinctrl.h> 16 #include <linux/kernel.h> 17 18 #include "sh_pfc.h" 19 20 /* 21 * All pins assigned to GPIO bank 3 can be used for SD interfaces in 22 * which case they support both 3.3V and 1.8V signalling. 23 */ 24 #define CPU_ALL_PORT(fn, sfx) \ 25 PORT_GP_32(0, fn, sfx), \ 26 PORT_GP_30(1, fn, sfx), \ 27 PORT_GP_30(2, fn, sfx), \ 28 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 29 PORT_GP_32(4, fn, sfx), \ 30 PORT_GP_32(5, fn, sfx) 31 32 enum { 33 PINMUX_RESERVED = 0, 34 35 PINMUX_DATA_BEGIN, 36 GP_ALL(DATA), 37 PINMUX_DATA_END, 38 39 PINMUX_FUNCTION_BEGIN, 40 GP_ALL(FN), 41 42 /* GPSR0 */ 43 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, 44 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, 45 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, 46 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, 47 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, 48 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, 49 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, 50 FN_IP3_14_12, FN_IP3_17_15, 51 52 /* GPSR1 */ 53 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, 54 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, 55 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, 56 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, 57 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, 58 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, 59 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, 60 61 /* GPSR2 */ 62 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, 63 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, 64 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, 65 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, 66 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, 67 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, 68 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, 69 70 /* GPSR3 */ 71 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, 72 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, 73 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, 74 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, 75 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, 76 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, 77 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, 78 79 /* GPSR4 */ 80 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, 81 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, 82 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, 83 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, 84 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, 85 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, 86 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, 87 FN_IP14_15_12, FN_IP14_18_16, 88 89 /* GPSR5 */ 90 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, 91 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, 92 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, 93 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, 94 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, 95 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, 96 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, 97 98 /* IPSR0 */ 99 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 100 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, 101 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, 102 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, 103 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, 104 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 105 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, 106 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 107 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, 108 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 109 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 110 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1, 111 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 112 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 113 114 /* IPSR1 */ 115 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 116 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, 117 FN_SCIFA1_TXD_C, FN_AVB_TXD2, 118 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, 119 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 120 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 121 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 122 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 123 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 124 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, 125 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 126 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 127 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 128 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 129 FN_A0, FN_PWM3, FN_A1, FN_PWM4, 130 131 /* IPSR2 */ 132 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, 133 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, 134 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 135 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, 136 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 137 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 138 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 139 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 140 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 141 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 142 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 143 144 /* IPSR3 */ 145 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 146 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 147 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 148 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 149 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 150 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 151 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, 152 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, 153 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, 154 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, 155 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, 156 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, 157 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 158 159 /* IPSR4 */ 160 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 161 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, 162 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, 163 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, 164 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 165 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, 166 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, 167 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 168 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 169 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, 170 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, 171 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, 172 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, 173 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 174 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 175 176 /* IPSR5 */ 177 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 178 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 179 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 180 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, 181 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, 182 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 183 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, 184 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, 185 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, 186 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 187 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, 188 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 189 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 190 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, 191 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 192 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 193 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, 194 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, 195 FN_SSI_WS78_B, 196 197 /* IPSR6 */ 198 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 199 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 200 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 201 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, 202 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 203 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, 204 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 205 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 206 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, 207 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 208 FN_I2C2_SCL_E, FN_ETH_RX_ER, 209 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, 210 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, 211 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, 212 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, 213 FN_HRX0_E, FN_STP_ISSYNC_0_B, 214 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, 215 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, 216 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 217 FN_ETH_REF_CLK, FN_HCTS0_N_E, 218 FN_STP_IVCXO27_1_B, FN_HRX0_F, 219 220 /* IPSR7 */ 221 FN_ETH_MDIO, FN_HRTS0_N_E, 222 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, 223 FN_HTX0_F, FN_BPFCLK_G, 224 FN_ETH_TX_EN, FN_SIM0_CLK_C, 225 FN_HRTS0_N_F, FN_ETH_MAGIC, 226 FN_SIM0_RST_C, FN_ETH_TXD0, 227 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, 228 FN_ETH_MDC, FN_STP_ISD_1_B, 229 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, 230 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 231 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, 232 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, 233 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, 234 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1, 235 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, 236 FN_ATACS00_N, FN_AVB_RXD1, 237 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 238 239 /* IPSR8 */ 240 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 241 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, 242 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, 243 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, 244 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, 245 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 246 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 247 FN_VI1_CLK, FN_AVB_RX_DV, 248 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, 249 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, 250 FN_SCIFA1_RXD_D, FN_AVB_MDC, 251 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 252 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, 253 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 254 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, 255 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 256 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, 257 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 258 259 /* IPSR9 */ 260 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 261 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 262 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 263 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 264 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 265 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 266 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, 267 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 268 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 269 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, 270 FN_AVB_TX_EN, FN_SD1_CMD, 271 FN_AVB_TX_ER, FN_SCIFB0_SCK_B, 272 FN_SD1_DAT0, FN_AVB_TX_CLK, 273 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, 274 FN_SCIFB0_TXD_B, FN_SD1_DAT2, 275 FN_AVB_COL, FN_SCIFB0_CTS_N_B, 276 FN_SD1_DAT3, FN_AVB_RXD0, 277 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, 278 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, 279 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, 280 FN_VI3_CLK_B, 281 282 /* IPSR10 */ 283 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 284 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 285 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 286 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 287 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 288 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 289 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 290 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 291 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 292 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 293 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 294 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 295 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 296 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 297 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 298 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, 299 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 300 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, 301 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, 302 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 303 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 304 FN_GLO_I0_B, FN_VI3_DATA6_B, 305 306 /* IPSR11 */ 307 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 308 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 309 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 310 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, 311 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 312 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, 313 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, 314 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 315 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, 316 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 317 FN_FMIN_E, FN_FMIN_F, 318 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 319 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, 320 FN_I2C2_SDA_B, FN_MLB_DAT, 321 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 322 FN_SSI_SCK0129, FN_CAN_CLK_B, 323 FN_MOUT0, 324 325 /* IPSR12 */ 326 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 327 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 328 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 329 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 330 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 331 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, 332 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 333 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, 334 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 335 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 336 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 337 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 338 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 339 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 340 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, 341 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 342 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, 343 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 344 FN_CAN_DEBUGOUT4, 345 346 /* IPSR13 */ 347 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 348 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, 349 FN_SCIFB1_CTS_N, FN_BPFCLK_D, 350 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 351 FN_BPFCLK_F, FN_SSI_WS6, 352 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 353 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, 354 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5, 355 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, 356 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, 357 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, 358 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, 359 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, 360 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 361 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, 362 FN_BPFCLK_E, FN_SSI_SDATA7_B, 363 FN_FMIN_G, FN_SSI_SDATA8, 364 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 365 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, 366 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 367 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, 368 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 369 370 /* IPSR14 */ 371 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 372 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 373 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, 374 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, 375 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, 376 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, 377 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, 378 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, 379 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 380 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 381 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 382 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 383 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 384 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 385 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, 386 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, 387 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 388 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 389 FN_HRTS0_N_C, 390 391 /* IPSR15 */ 392 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 393 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, 394 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, 395 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 396 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, 397 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, 398 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, 399 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, 400 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, 401 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 402 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, 403 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, 404 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0, 405 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, 406 FN_DU2_DG6, FN_LCDOUT14, 407 408 /* IPSR16 */ 409 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 410 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 411 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 412 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 413 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, 414 FN_TCLK1_B, 415 416 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 417 FN_SEL_SCIF1_4, 418 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 419 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 420 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 421 FN_SEL_SCIFB1_4, 422 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, 423 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, 424 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 425 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 426 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 427 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 428 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 429 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 430 FN_SEL_VI3_0, FN_SEL_VI3_1, 431 FN_SEL_VI2_0, FN_SEL_VI2_1, 432 FN_SEL_VI1_0, FN_SEL_VI1_1, 433 FN_SEL_VI0_0, FN_SEL_VI0_1, 434 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 435 FN_SEL_LBS_0, FN_SEL_LBS_1, 436 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 437 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 438 FN_SEL_SOF0_0, FN_SEL_SOF0_1, 439 440 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 441 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 442 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 443 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 444 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 445 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 446 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 447 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 448 FN_SEL_ADI_0, FN_SEL_ADI_1, 449 FN_SEL_SSP_0, FN_SEL_SSP_1, 450 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 451 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 452 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, 453 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 454 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 455 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 456 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 457 458 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 459 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 460 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 461 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 462 FN_SEL_IIC2_4, 463 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 464 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 465 FN_SEL_I2C2_4, 466 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 467 PINMUX_FUNCTION_END, 468 469 PINMUX_MARK_BEGIN, 470 471 VI1_DATA7_VI1_B7_MARK, 472 473 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 474 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, 475 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, 476 477 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, 478 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, 479 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, 480 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, 481 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, 482 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, 483 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, 484 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, 485 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, 486 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, 487 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, 488 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK, 489 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, 490 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, 491 492 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, 493 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, 494 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, 495 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, 496 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, 497 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, 498 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, 499 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, 500 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, 501 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, 502 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, 503 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, 504 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, 505 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, 506 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, 507 508 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, 509 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, 510 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, 511 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, 512 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, 513 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, 514 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, 515 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, 516 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, 517 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, 518 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, 519 520 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, 521 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, 522 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, 523 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, 524 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, 525 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, 526 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, 527 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, 528 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, 529 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, 530 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, 531 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, 532 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, 533 534 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, 535 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, 536 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, 537 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, 538 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, 539 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, 540 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, 541 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, 542 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, 543 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, 544 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, 545 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, 546 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, 547 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, 548 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, 549 550 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, 551 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, 552 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, 553 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, 554 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, 555 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, 556 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, 557 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, 558 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, 559 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, 560 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, 561 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, 562 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, 563 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, 564 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, 565 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, 566 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, 567 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, 568 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, 569 SSI_WS78_B_MARK, 570 571 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, 572 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, 573 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, 574 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, 575 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, 576 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, 577 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, 578 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, 579 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, 580 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, 581 I2C2_SCL_E_MARK, ETH_RX_ER_MARK, 582 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, 583 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, 584 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, 585 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, 586 HRX0_E_MARK, STP_ISSYNC_0_B_MARK, 587 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, 588 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, 589 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, 590 ETH_REF_CLK_MARK, HCTS0_N_E_MARK, 591 STP_IVCXO27_1_B_MARK, HRX0_F_MARK, 592 593 ETH_MDIO_MARK, HRTS0_N_E_MARK, 594 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, 595 HTX0_F_MARK, BPFCLK_G_MARK, 596 ETH_TX_EN_MARK, SIM0_CLK_C_MARK, 597 HRTS0_N_F_MARK, ETH_MAGIC_MARK, 598 SIM0_RST_C_MARK, ETH_TXD0_MARK, 599 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, 600 ETH_MDC_MARK, STP_ISD_1_B_MARK, 601 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, 602 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, 603 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, 604 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, 605 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, 606 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK, 607 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, 608 ATACS00_N_MARK, AVB_RXD1_MARK, 609 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, 610 611 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, 612 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, 613 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, 614 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, 615 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, 616 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, 617 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, 618 VI1_CLK_MARK, AVB_RX_DV_MARK, 619 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, 620 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, 621 SCIFA1_RXD_D_MARK, AVB_MDC_MARK, 622 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, 623 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, 624 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, 625 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, 626 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, 627 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, 628 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, 629 630 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, 631 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, 632 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, 633 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, 634 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, 635 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, 636 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, 637 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, 638 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, 639 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, 640 AVB_TX_EN_MARK, SD1_CMD_MARK, 641 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, 642 SD1_DAT0_MARK, AVB_TX_CLK_MARK, 643 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, 644 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, 645 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, 646 SD1_DAT3_MARK, AVB_RXD0_MARK, 647 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, 648 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, 649 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, 650 VI3_CLK_B_MARK, 651 652 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, 653 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, 654 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, 655 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, 656 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, 657 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, 658 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, 659 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, 660 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, 661 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, 662 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, 663 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, 664 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, 665 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, 666 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, 667 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, 668 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, 669 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, 670 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, 671 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, 672 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, 673 GLO_I0_B_MARK, VI3_DATA6_B_MARK, 674 675 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, 676 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, 677 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, 678 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, 679 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, 680 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, 681 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, 682 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, 683 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, 684 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, 685 FMIN_E_MARK, FMIN_F_MARK, 686 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, 687 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, 688 I2C2_SDA_B_MARK, MLB_DAT_MARK, 689 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, 690 SSI_SCK0129_MARK, CAN_CLK_B_MARK, 691 MOUT0_MARK, 692 693 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, 694 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, 695 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, 696 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, 697 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, 698 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, 699 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, 700 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, 701 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, 702 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, 703 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, 704 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, 705 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, 706 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, 707 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, 708 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, 709 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, 710 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, 711 CAN_DEBUGOUT4_MARK, 712 713 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, 714 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, 715 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, 716 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, 717 BPFCLK_F_MARK, SSI_WS6_MARK, 718 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, 719 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, 720 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK, 721 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, 722 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, 723 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, 724 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, 725 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, 726 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, 727 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, 728 BPFCLK_E_MARK, SSI_SDATA7_B_MARK, 729 FMIN_G_MARK, SSI_SDATA8_MARK, 730 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, 731 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, 732 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, 733 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, 734 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, 735 736 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, 737 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, 738 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, 739 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, 740 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, 741 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, 742 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, 743 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, 744 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, 745 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, 746 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, 747 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, 748 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 749 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, 750 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, 751 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, 752 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, 753 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, 754 HRTS0_N_C_MARK, 755 756 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, 757 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, 758 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, 759 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, 760 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, 761 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, 762 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, 763 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, 764 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, 765 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, 766 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, 767 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, 768 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, 769 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, 770 DU2_DG6_MARK, LCDOUT14_MARK, 771 772 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, 773 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, 774 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, 775 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, 776 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, 777 TCLK1_B_MARK, 778 779 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK, 780 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK, 781 PINMUX_MARK_END, 782 }; 783 784 static const u16 pinmux_data[] = { 785 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 786 787 PINMUX_SINGLE(VI1_DATA7_VI1_B7), 788 PINMUX_SINGLE(USB0_PWEN), 789 PINMUX_SINGLE(USB0_OVC_VBUS), 790 PINMUX_SINGLE(USB2_PWEN), 791 PINMUX_SINGLE(USB2_OVC), 792 PINMUX_SINGLE(AVS1), 793 PINMUX_SINGLE(AVS2), 794 PINMUX_SINGLE(DU_DOTCLKIN0), 795 PINMUX_SINGLE(DU_DOTCLKIN2), 796 797 PINMUX_IPSR_GPSR(IP0_2_0, D0), 798 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), 799 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0), 800 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0), 801 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1), 802 PINMUX_IPSR_GPSR(IP0_5_3, D1), 803 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), 804 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0), 805 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0), 806 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1), 807 PINMUX_IPSR_GPSR(IP0_8_6, D2), 808 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), 809 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0), 810 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0), 811 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1), 812 PINMUX_IPSR_GPSR(IP0_11_9, D3), 813 PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), 814 PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0), 815 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0), 816 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1), 817 PINMUX_IPSR_GPSR(IP0_15_12, D4), 818 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), 819 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), 820 PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0), 821 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0), 822 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1), 823 PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1), 824 PINMUX_IPSR_GPSR(IP0_19_16, D5), 825 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), 826 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), 827 PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0), 828 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0), 829 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1), 830 PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1), 831 PINMUX_IPSR_GPSR(IP0_22_20, D6), 832 PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), 833 PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0), 834 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0), 835 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1), 836 PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), 837 PINMUX_IPSR_GPSR(IP0_26_23, D7), 838 PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1), 839 PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), 840 PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0), 841 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0), 842 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1), 843 PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), 844 PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0), 845 PINMUX_IPSR_GPSR(IP0_30_27, D8), 846 PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), 847 PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0), 848 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0), 849 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1), 850 PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), 851 852 PINMUX_IPSR_GPSR(IP1_3_0, D9), 853 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), 854 PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1), 855 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0), 856 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1), 857 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), 858 PINMUX_IPSR_GPSR(IP1_7_4, D10), 859 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), 860 PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2), 861 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0), 862 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1), 863 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), 864 PINMUX_IPSR_GPSR(IP1_11_8, D11), 865 PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), 866 PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3), 867 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0), 868 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1), 869 PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), 870 PINMUX_IPSR_GPSR(IP1_14_12, D12), 871 PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), 872 PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4), 873 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), 874 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), 875 PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), 876 PINMUX_IPSR_GPSR(IP1_17_15, D13), 877 PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5), 878 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), 879 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), 880 PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), 881 PINMUX_IPSR_GPSR(IP1_21_18, D14), 882 PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), 883 PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6), 884 PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1), 885 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0), 886 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), 887 PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), 888 PINMUX_IPSR_GPSR(IP1_25_22, D15), 889 PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), 890 PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7), 891 PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1), 892 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0), 893 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), 894 PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), 895 PINMUX_IPSR_GPSR(IP1_27_26, A0), 896 PINMUX_IPSR_GPSR(IP1_27_26, PWM3), 897 PINMUX_IPSR_GPSR(IP1_29_28, A1), 898 PINMUX_IPSR_GPSR(IP1_29_28, PWM4), 899 900 PINMUX_IPSR_GPSR(IP2_2_0, A2), 901 PINMUX_IPSR_GPSR(IP2_2_0, PWM5), 902 PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), 903 PINMUX_IPSR_GPSR(IP2_5_3, A3), 904 PINMUX_IPSR_GPSR(IP2_5_3, PWM6), 905 PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), 906 PINMUX_IPSR_GPSR(IP2_8_6, A4), 907 PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), 908 PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0), 909 PINMUX_IPSR_GPSR(IP2_11_9, A5), 910 PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), 911 PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1), 912 PINMUX_IPSR_GPSR(IP2_14_12, A6), 913 PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), 914 PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2), 915 PINMUX_IPSR_GPSR(IP2_17_15, A7), 916 PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), 917 PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B), 918 PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3), 919 PINMUX_IPSR_GPSR(IP2_21_18, A8), 920 PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), 921 PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), 922 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0), 923 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1), 924 PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), 925 PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1), 926 PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), 927 PINMUX_IPSR_GPSR(IP2_25_22, A9), 928 PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), 929 PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), 930 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0), 931 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1), 932 PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), 933 PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1), 934 PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), 935 PINMUX_IPSR_GPSR(IP2_28_26, A10), 936 PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), 937 PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC), 938 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0), 939 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1), 940 PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), 941 942 PINMUX_IPSR_GPSR(IP3_3_0, A11), 943 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 944 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK), 945 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0), 946 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1), 947 PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0), 948 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), 949 PINMUX_IPSR_GPSR(IP3_7_4, A12), 950 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), 951 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), 952 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0), 953 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1), 954 PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1), 955 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), 956 PINMUX_IPSR_GPSR(IP3_11_8, A13), 957 PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 958 PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2), 959 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD), 960 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0), 961 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1), 962 PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2), 963 PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), 964 PINMUX_IPSR_GPSR(IP3_14_12, A14), 965 PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), 966 PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N), 967 PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1), 968 PINMUX_IPSR_GPSR(IP3_17_15, A15), 969 PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), 970 PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N), 971 PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2), 972 PINMUX_IPSR_GPSR(IP3_19_18, A16), 973 PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N), 974 PINMUX_IPSR_GPSR(IP3_22_20, A17), 975 PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1), 976 PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N), 977 PINMUX_IPSR_GPSR(IP3_25_23, A18), 978 PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1), 979 PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N), 980 PINMUX_IPSR_GPSR(IP3_28_26, A19), 981 PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), 982 PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N), 983 PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), 984 PINMUX_IPSR_GPSR(IP3_31_29, A20), 985 PINMUX_IPSR_GPSR(IP3_31_29, SPCLK), 986 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0), 987 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1), 988 PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4), 989 990 PINMUX_IPSR_GPSR(IP4_2_0, A21), 991 PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0), 992 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0), 993 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1), 994 PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5), 995 PINMUX_IPSR_GPSR(IP4_5_3, A22), 996 PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1), 997 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0), 998 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1), 999 PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6), 1000 PINMUX_IPSR_GPSR(IP4_8_6, A23), 1001 PINMUX_IPSR_GPSR(IP4_8_6, IO2), 1002 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0), 1003 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1), 1004 PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7), 1005 PINMUX_IPSR_GPSR(IP4_11_9, A24), 1006 PINMUX_IPSR_GPSR(IP4_11_9, IO3), 1007 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0), 1008 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1), 1009 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0), 1010 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), 1011 PINMUX_IPSR_GPSR(IP4_14_12, A25), 1012 PINMUX_IPSR_GPSR(IP4_14_12, SSL), 1013 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0), 1014 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1), 1015 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0), 1016 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), 1017 PINMUX_IPSR_GPSR(IP4_17_15, CS0_N), 1018 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0), 1019 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1), 1020 PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3), 1021 PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), 1022 PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26), 1023 PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN), 1024 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0), 1025 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1), 1026 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0), 1027 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1), 1028 PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N), 1029 PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1), 1030 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0), 1031 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1), 1032 PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0), 1033 PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1), 1034 PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), 1035 PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N), 1036 PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK), 1037 PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), 1038 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0), 1039 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), 1040 PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1), 1041 PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N), 1042 PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN), 1043 PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), 1044 PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB), 1045 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0), 1046 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1), 1047 PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2), 1048 1049 PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N), 1050 PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG), 1051 PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD), 1052 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0), 1053 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1), 1054 PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3), 1055 PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N), 1056 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), 1057 PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N), 1058 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), 1059 PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0), 1060 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), 1061 PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N), 1062 PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0), 1063 PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N), 1064 PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0), 1065 PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), 1066 PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N), 1067 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0), 1068 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1), 1069 PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4), 1070 PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0), 1071 PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N), 1072 PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0), 1073 PINMUX_IPSR_GPSR(IP5_12_10, BS_N), 1074 PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0), 1075 PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1), 1076 PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0), 1077 PINMUX_IPSR_GPSR(IP5_12_10, DRACK0), 1078 PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2), 1079 PINMUX_IPSR_GPSR(IP5_14_13, RD_N), 1080 PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0), 1081 PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), 1082 PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N), 1083 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0), 1084 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), 1085 PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5), 1086 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), 1087 PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N), 1088 PINMUX_IPSR_GPSR(IP5_20_18, WE0_N), 1089 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), 1090 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), 1091 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), 1092 PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), 1093 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), 1094 PINMUX_IPSR_GPSR(IP5_23_21, WE1_N), 1095 PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0), 1096 PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0), 1097 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0), 1098 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1), 1099 PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6), 1100 PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), 1101 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), 1102 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), 1103 PINMUX_IPSR_GPSR(IP5_26_24, IRQ3), 1104 PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N), 1105 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), 1106 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), 1107 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), 1108 PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), 1109 PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N), 1110 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), 1111 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), 1112 PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7), 1113 PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), 1114 PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), 1115 1116 PINMUX_IPSR_GPSR(IP6_2_0, DACK0), 1117 PINMUX_IPSR_GPSR(IP6_2_0, IRQ0), 1118 PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N), 1119 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), 1120 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), 1121 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), 1122 PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), 1123 PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N), 1124 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0), 1125 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), 1126 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), 1127 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), 1128 PINMUX_IPSR_GPSR(IP6_8_6, DACK1), 1129 PINMUX_IPSR_GPSR(IP6_8_6, IRQ1), 1130 PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N), 1131 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), 1132 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), 1133 PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N), 1134 PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), 1135 PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), 1136 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), 1137 PINMUX_IPSR_GPSR(IP6_13_11, DACK2), 1138 PINMUX_IPSR_GPSR(IP6_13_11, IRQ2), 1139 PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N), 1140 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), 1141 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), 1142 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), 1143 PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV), 1144 PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), 1145 PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), 1146 PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2), 1147 PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), 1148 PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), 1149 PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER), 1150 PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), 1151 PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), 1152 PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2), 1153 PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), 1154 PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), 1155 PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0), 1156 PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), 1157 PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), 1158 PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2), 1159 PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), 1160 PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4), 1161 PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1), 1162 PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4), 1163 PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), 1164 PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), 1165 PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2), 1166 PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), 1167 PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4), 1168 PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK), 1169 PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4), 1170 PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), 1171 PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), 1172 PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4), 1173 PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK), 1174 PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), 1175 PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), 1176 PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5), 1177 1178 PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO), 1179 PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), 1180 PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2), 1181 PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), 1182 PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1), 1183 PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5), 1184 PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6), 1185 PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN), 1186 PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), 1187 PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), 1188 PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC), 1189 PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2), 1190 PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0), 1191 PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), 1192 PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), 1193 PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), 1194 PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC), 1195 PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), 1196 PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), 1197 PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), 1198 PINMUX_IPSR_GPSR(IP7_18_16, PWM0), 1199 PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), 1200 PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), 1201 PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), 1202 PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2), 1203 PINMUX_IPSR_GPSR(IP7_21_19, PWM1), 1204 PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), 1205 PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), 1206 PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), 1207 PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2), 1208 PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N), 1209 PINMUX_IPSR_GPSR(IP7_24_22, PWM2), 1210 PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0), 1211 PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), 1212 PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N), 1213 PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2), 1214 PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1), 1215 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC), 1216 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C), 1217 PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0), 1218 PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N), 1219 PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1), 1220 PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), 1221 PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N), 1222 PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2), 1223 1224 PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), 1225 PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N), 1226 PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3), 1227 PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), 1228 PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N), 1229 PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4), 1230 PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), 1231 PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N), 1232 PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5), 1233 PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), 1234 PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N), 1235 PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6), 1236 PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), 1237 PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1), 1238 PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7), 1239 PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), 1240 PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER), 1241 PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), 1242 PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK), 1243 PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0), 1244 PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV), 1245 PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), 1246 PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), 1247 PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS), 1248 PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), 1249 PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), 1250 PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC), 1251 PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), 1252 PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), 1253 PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO), 1254 PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), 1255 PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), 1256 PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK), 1257 PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), 1258 PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), 1259 PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC), 1260 PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), 1261 PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT), 1262 PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), 1263 PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK), 1264 PINMUX_IPSR_GPSR(IP8_28, SD0_CLK), 1265 PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), 1266 PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD), 1267 PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), 1268 PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), 1269 1270 PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0), 1271 PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), 1272 PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), 1273 PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1), 1274 PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), 1275 PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), 1276 PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2), 1277 PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), 1278 PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), 1279 PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3), 1280 PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), 1281 PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), 1282 PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD), 1283 PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6), 1284 PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), 1285 PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP), 1286 PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0), 1287 PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), 1288 PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), 1289 PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), 1290 PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), 1291 PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP), 1292 PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7), 1293 PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), 1294 PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN), 1295 PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0), 1296 PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), 1297 PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), 1298 PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), 1299 PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), 1300 PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK), 1301 PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN), 1302 PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD), 1303 PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER), 1304 PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), 1305 PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0), 1306 PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK), 1307 PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), 1308 PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1), 1309 PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK), 1310 PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), 1311 PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2), 1312 PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL), 1313 PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), 1314 PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3), 1315 PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0), 1316 PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), 1317 PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD), 1318 PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6), 1319 PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), 1320 PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP), 1321 PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0), 1322 PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1), 1323 PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), 1324 PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), 1325 PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), 1326 PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1), 1327 1328 PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP), 1329 PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7), 1330 PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), 1331 PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN), 1332 PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0), 1333 PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1), 1334 PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), 1335 PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), 1336 PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1), 1337 PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK), 1338 PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK), 1339 PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0), 1340 PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), 1341 PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), 1342 PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), 1343 PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), 1344 PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD), 1345 PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD), 1346 PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0), 1347 PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), 1348 PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), 1349 PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3), 1350 PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), 1351 PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), 1352 PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), 1353 PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0), 1354 PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0), 1355 PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1), 1356 PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), 1357 PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), 1358 PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3), 1359 PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), 1360 PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1), 1361 PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), 1362 PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1), 1363 PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1), 1364 PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1), 1365 PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), 1366 PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), 1367 PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3), 1368 PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), 1369 PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1), 1370 PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), 1371 PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2), 1372 PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2), 1373 PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1), 1374 PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), 1375 PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3), 1376 PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), 1377 PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1), 1378 PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), 1379 PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3), 1380 PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3), 1381 PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0), 1382 PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), 1383 PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3), 1384 PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), 1385 PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1), 1386 PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), 1387 PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD), 1388 PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4), 1389 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), 1390 PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP), 1391 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0), 1392 PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), 1393 PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), 1394 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), 1395 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1), 1396 PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), 1397 1398 PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP), 1399 PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5), 1400 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), 1401 PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN), 1402 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0), 1403 PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), 1404 PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), 1405 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), 1406 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1), 1407 PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), 1408 PINMUX_IPSR_GPSR(IP11_4, SD3_CLK), 1409 PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK), 1410 PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD), 1411 PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD), 1412 PINMUX_IPSR_GPSR(IP11_6_5, MTS_N), 1413 PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0), 1414 PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0), 1415 PINMUX_IPSR_GPSR(IP11_8_7, STM_N), 1416 PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1), 1417 PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1), 1418 PINMUX_IPSR_GPSR(IP11_10_9, MDATA), 1419 PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2), 1420 PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2), 1421 PINMUX_IPSR_GPSR(IP11_12_11, SDATA), 1422 PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3), 1423 PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3), 1424 PINMUX_IPSR_GPSR(IP11_14_13, SCKZ), 1425 PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD), 1426 PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4), 1427 PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), 1428 PINMUX_IPSR_GPSR(IP11_17_15, VSP), 1429 PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0), 1430 PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1), 1431 PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP), 1432 PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5), 1433 PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0), 1434 PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0), 1435 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2), 1436 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4), 1437 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5), 1438 PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK), 1439 PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), 1440 PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), 1441 PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG), 1442 PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), 1443 PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2), 1444 PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), 1445 PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), 1446 PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT), 1447 PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), 1448 PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2), 1449 PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2), 1450 PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129), 1451 PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), 1452 PINMUX_IPSR_GPSR(IP11_31_30, MOUT0), 1453 1454 PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129), 1455 PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), 1456 PINMUX_IPSR_GPSR(IP12_1_0, MOUT1), 1457 PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0), 1458 PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), 1459 PINMUX_IPSR_GPSR(IP12_3_2, MOUT2), 1460 PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1), 1461 PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), 1462 PINMUX_IPSR_GPSR(IP12_5_4, MOUT5), 1463 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2), 1464 PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), 1465 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1), 1466 PINMUX_IPSR_GPSR(IP12_7_6, MOUT6), 1467 PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34), 1468 PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0), 1469 PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), 1470 PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), 1471 PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER), 1472 PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34), 1473 PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), 1474 PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), 1475 PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC), 1476 PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0), 1477 PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3), 1478 PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), 1479 PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), 1480 PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), 1481 PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK), 1482 PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4), 1483 PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0), 1484 PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), 1485 PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), 1486 PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), 1487 PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0), 1488 PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4), 1489 PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0), 1490 PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), 1491 PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), 1492 PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), 1493 PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1), 1494 PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4), 1495 PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), 1496 PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), 1497 PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2), 1498 PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0), 1499 PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), 1500 PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1), 1501 PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), 1502 PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS), 1503 PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3), 1504 PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0), 1505 PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), 1506 PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1), 1507 PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), 1508 PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE), 1509 PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4), 1510 1511 PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), 1512 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), 1513 PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1), 1514 PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2), 1515 PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2), 1516 PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5), 1517 PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0), 1518 PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), 1519 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3), 1520 PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3), 1521 PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3), 1522 PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6), 1523 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5), 1524 PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0), 1525 PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), 1526 PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), 1527 PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4), 1528 PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4), 1529 PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7), 1530 PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), 1531 PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3), 1532 PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5), 1533 PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5), 1534 PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8), 1535 PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0), 1536 PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), 1537 PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0), 1538 PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), 1539 PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6), 1540 PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6), 1541 PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9), 1542 PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0), 1543 PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), 1544 PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), 1545 PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N), 1546 PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7), 1547 PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7), 1548 PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10), 1549 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), 1550 PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0), 1551 PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), 1552 PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N), 1553 PINMUX_IPSR_GPSR(IP13_22_19, TCLK2), 1554 PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS), 1555 PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11), 1556 PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4), 1557 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), 1558 PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6), 1559 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), 1560 PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0), 1561 PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), 1562 PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), 1563 PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12), 1564 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), 1565 PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9), 1566 PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), 1567 PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), 1568 PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1), 1569 PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), 1570 PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13), 1571 PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA), 1572 PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), 1573 PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14), 1574 1575 PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB), 1576 PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), 1577 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), 1578 PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE), 1579 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), 1580 PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15), 1581 PINMUX_IPSR_GPSR(IP14_2_0, REMOCON), 1582 PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), 1583 PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0), 1584 PINMUX_IPSR_GPSR(IP14_5_3, SCK0), 1585 PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2), 1586 PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2), 1587 PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10), 1588 PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), 1589 PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), 1590 PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), 1591 PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0), 1592 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0), 1593 PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0), 1594 PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0), 1595 PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), 1596 PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0), 1597 PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0), 1598 PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1), 1599 PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1), 1600 PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), 1601 PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), 1602 PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N), 1603 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), 1604 PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3), 1605 PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11), 1606 PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B), 1607 PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), 1608 PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), 1609 PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), 1610 PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), 1611 PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N), 1612 PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1), 1613 PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0), 1614 PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8), 1615 PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B), 1616 PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), 1617 PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0), 1618 PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0), 1619 PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), 1620 PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE), 1621 PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), 1622 PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0), 1623 PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0), 1624 PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1), 1625 PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9), 1626 PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), 1627 PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0), 1628 PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N), 1629 PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), 1630 PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT), 1631 PINMUX_IPSR_GPSR(IP14_27_25, QCLK), 1632 PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), 1633 PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0), 1634 PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N), 1635 PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), 1636 PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT), 1637 PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE), 1638 PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), 1639 1640 PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), 1641 PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0), 1642 PINMUX_IPSR_GPSR(IP15_2_0, SCK2), 1643 PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), 1644 PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7), 1645 PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15), 1646 PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), 1647 PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1648 PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0), 1649 PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0), 1650 PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0), 1651 PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16), 1652 PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0), 1653 PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0), 1654 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), 1655 PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0), 1656 PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0), 1657 PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1), 1658 PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17), 1659 PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0), 1660 PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0), 1661 PINMUX_IPSR_GPSR(IP15_11_9, HSCK0), 1662 PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), 1663 PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4), 1664 PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12), 1665 PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), 1666 PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0), 1667 PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2), 1668 PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18), 1669 PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0), 1670 PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3), 1671 PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19), 1672 PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), 1673 PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9), 1674 PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4), 1675 PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20), 1676 PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), 1677 PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9), 1678 PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5), 1679 PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21), 1680 PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), 1681 PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), 1682 PINMUX_IPSR_GPSR(IP15_22_20, ADICLK), 1683 PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6), 1684 PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22), 1685 PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC), 1686 PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0), 1687 PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2), 1688 PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA), 1689 PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7), 1690 PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23), 1691 PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1), 1692 PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), 1693 PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0), 1694 PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5), 1695 PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13), 1696 PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), 1697 PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1), 1698 PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6), 1699 PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14), 1700 1701 PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), 1702 PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT), 1703 PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2), 1704 PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP), 1705 PINMUX_IPSR_GPSR(IP16_2_0, QPOLA), 1706 PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2), 1707 PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), 1708 PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), 1709 PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), 1710 PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2), 1711 PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP), 1712 PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE), 1713 PINMUX_IPSR_GPSR(IP16_5_3, QPOLB), 1714 PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), 1715 PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN), 1716 PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D), 1717 PINMUX_IPSR_GPSR(IP16_7, USB1_OVC), 1718 PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1), 1719 1720 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0), 1721 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0), 1722 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1), 1723 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1), 1724 1725 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0), 1726 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0), 1727 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1), 1728 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), 1729 }; 1730 1731 /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */ 1732 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) 1733 #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) 1734 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) 1735 1736 static const struct sh_pfc_pin pinmux_pins[] = { 1737 PINMUX_GPIO_GP_ALL(), 1738 1739 /* Pins not associated with a GPIO port */ 1740 SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15), 1741 SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15), 1742 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), 1743 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15), 1744 }; 1745 1746 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1747 static const unsigned int audio_clk_a_pins[] = { 1748 /* CLK A */ 1749 RCAR_GP_PIN(4, 25), 1750 }; 1751 static const unsigned int audio_clk_a_mux[] = { 1752 AUDIO_CLKA_MARK, 1753 }; 1754 static const unsigned int audio_clk_b_pins[] = { 1755 /* CLK B */ 1756 RCAR_GP_PIN(4, 26), 1757 }; 1758 static const unsigned int audio_clk_b_mux[] = { 1759 AUDIO_CLKB_MARK, 1760 }; 1761 static const unsigned int audio_clk_c_pins[] = { 1762 /* CLK C */ 1763 RCAR_GP_PIN(5, 27), 1764 }; 1765 static const unsigned int audio_clk_c_mux[] = { 1766 AUDIO_CLKC_MARK, 1767 }; 1768 static const unsigned int audio_clkout_pins[] = { 1769 /* CLK OUT */ 1770 RCAR_GP_PIN(5, 16), 1771 }; 1772 static const unsigned int audio_clkout_mux[] = { 1773 AUDIO_CLKOUT_MARK, 1774 }; 1775 static const unsigned int audio_clkout_b_pins[] = { 1776 /* CLK OUT B */ 1777 RCAR_GP_PIN(0, 23), 1778 }; 1779 static const unsigned int audio_clkout_b_mux[] = { 1780 AUDIO_CLKOUT_B_MARK, 1781 }; 1782 static const unsigned int audio_clkout_c_pins[] = { 1783 /* CLK OUT C */ 1784 RCAR_GP_PIN(5, 27), 1785 }; 1786 static const unsigned int audio_clkout_c_mux[] = { 1787 AUDIO_CLKOUT_C_MARK, 1788 }; 1789 static const unsigned int audio_clkout_d_pins[] = { 1790 /* CLK OUT D */ 1791 RCAR_GP_PIN(5, 20), 1792 }; 1793 static const unsigned int audio_clkout_d_mux[] = { 1794 AUDIO_CLKOUT_D_MARK, 1795 }; 1796 /* - AVB -------------------------------------------------------------------- */ 1797 static const unsigned int avb_link_pins[] = { 1798 RCAR_GP_PIN(3, 11), 1799 }; 1800 static const unsigned int avb_link_mux[] = { 1801 AVB_LINK_MARK, 1802 }; 1803 static const unsigned int avb_magic_pins[] = { 1804 RCAR_GP_PIN(2, 14), 1805 }; 1806 static const unsigned int avb_magic_mux[] = { 1807 AVB_MAGIC_MARK, 1808 }; 1809 static const unsigned int avb_phy_int_pins[] = { 1810 RCAR_GP_PIN(2, 15), 1811 }; 1812 static const unsigned int avb_phy_int_mux[] = { 1813 AVB_PHY_INT_MARK, 1814 }; 1815 static const unsigned int avb_mdio_pins[] = { 1816 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 1817 }; 1818 static const unsigned int avb_mdio_mux[] = { 1819 AVB_MDC_MARK, AVB_MDIO_MARK, 1820 }; 1821 static const unsigned int avb_mii_pins[] = { 1822 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1823 RCAR_GP_PIN(0, 11), 1824 1825 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1826 RCAR_GP_PIN(2, 2), 1827 1828 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1829 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10), 1830 RCAR_GP_PIN(3, 12), 1831 }; 1832 static const unsigned int avb_mii_mux[] = { 1833 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1834 AVB_TXD3_MARK, 1835 1836 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1837 AVB_RXD3_MARK, 1838 1839 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1840 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK, 1841 AVB_COL_MARK, 1842 }; 1843 static const unsigned int avb_gmii_pins[] = { 1844 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1845 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1846 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 1847 1848 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1849 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 1850 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 1851 1852 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1853 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16), 1854 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 1855 RCAR_GP_PIN(3, 12), 1856 }; 1857 static const unsigned int avb_gmii_mux[] = { 1858 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1859 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1860 AVB_TXD6_MARK, AVB_TXD7_MARK, 1861 1862 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1863 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1864 AVB_RXD6_MARK, AVB_RXD7_MARK, 1865 1866 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1867 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1868 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1869 AVB_COL_MARK, 1870 }; 1871 /* - DU RGB ----------------------------------------------------------------- */ 1872 static const unsigned int du_rgb666_pins[] = { 1873 /* R[7:2], G[7:2], B[7:2] */ 1874 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1875 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1876 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), 1877 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 1878 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), 1879 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), 1880 }; 1881 static const unsigned int du_rgb666_mux[] = { 1882 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1883 DU2_DR3_MARK, DU2_DR2_MARK, 1884 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1885 DU2_DG3_MARK, DU2_DG2_MARK, 1886 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1887 DU2_DB3_MARK, DU2_DB2_MARK, 1888 }; 1889 static const unsigned int du_rgb888_pins[] = { 1890 /* R[7:0], G[7:0], B[7:0] */ 1891 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1892 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1893 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4), 1894 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7), 1895 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1), 1896 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), 1897 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), 1898 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 1899 }; 1900 static const unsigned int du_rgb888_mux[] = { 1901 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1902 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK, 1903 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1904 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK, 1905 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1906 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK, 1907 }; 1908 static const unsigned int du_clk_out_0_pins[] = { 1909 /* CLKOUT */ 1910 RCAR_GP_PIN(5, 2), 1911 }; 1912 static const unsigned int du_clk_out_0_mux[] = { 1913 DU0_DOTCLKOUT_MARK 1914 }; 1915 static const unsigned int du_clk_out_1_pins[] = { 1916 /* CLKOUT */ 1917 RCAR_GP_PIN(5, 3), 1918 }; 1919 static const unsigned int du_clk_out_1_mux[] = { 1920 DU1_DOTCLKOUT_MARK 1921 }; 1922 static const unsigned int du_sync_0_pins[] = { 1923 /* VSYNC, HSYNC, DISP */ 1924 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0), 1925 }; 1926 static const unsigned int du_sync_0_mux[] = { 1927 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 1928 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK 1929 }; 1930 static const unsigned int du_sync_1_pins[] = { 1931 /* VSYNC, HSYNC, DISP */ 1932 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16), 1933 }; 1934 static const unsigned int du_sync_1_mux[] = { 1935 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 1936 DU2_DISP_MARK 1937 }; 1938 static const unsigned int du_cde_pins[] = { 1939 /* CDE */ 1940 RCAR_GP_PIN(5, 17), 1941 }; 1942 static const unsigned int du_cde_mux[] = { 1943 DU2_CDE_MARK, 1944 }; 1945 /* - DU0 -------------------------------------------------------------------- */ 1946 static const unsigned int du0_clk_in_pins[] = { 1947 /* CLKIN */ 1948 RCAR_GP_PIN(5, 26), 1949 }; 1950 static const unsigned int du0_clk_in_mux[] = { 1951 DU_DOTCLKIN0_MARK 1952 }; 1953 /* - DU1 -------------------------------------------------------------------- */ 1954 static const unsigned int du1_clk_in_pins[] = { 1955 /* CLKIN */ 1956 RCAR_GP_PIN(5, 27), 1957 }; 1958 static const unsigned int du1_clk_in_mux[] = { 1959 DU_DOTCLKIN1_MARK, 1960 }; 1961 /* - DU2 -------------------------------------------------------------------- */ 1962 static const unsigned int du2_clk_in_pins[] = { 1963 /* CLKIN */ 1964 RCAR_GP_PIN(5, 28), 1965 }; 1966 static const unsigned int du2_clk_in_mux[] = { 1967 DU_DOTCLKIN2_MARK, 1968 }; 1969 /* - ETH -------------------------------------------------------------------- */ 1970 static const unsigned int eth_link_pins[] = { 1971 /* LINK */ 1972 RCAR_GP_PIN(2, 22), 1973 }; 1974 static const unsigned int eth_link_mux[] = { 1975 ETH_LINK_MARK, 1976 }; 1977 static const unsigned int eth_magic_pins[] = { 1978 /* MAGIC */ 1979 RCAR_GP_PIN(2, 27), 1980 }; 1981 static const unsigned int eth_magic_mux[] = { 1982 ETH_MAGIC_MARK, 1983 }; 1984 static const unsigned int eth_mdio_pins[] = { 1985 /* MDC, MDIO */ 1986 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), 1987 }; 1988 static const unsigned int eth_mdio_mux[] = { 1989 ETH_MDC_MARK, ETH_MDIO_MARK, 1990 }; 1991 static const unsigned int eth_rmii_pins[] = { 1992 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 1993 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), 1994 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), 1995 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), 1996 }; 1997 static const unsigned int eth_rmii_mux[] = { 1998 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 1999 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, 2000 }; 2001 /* - HSCIF0 ----------------------------------------------------------------- */ 2002 static const unsigned int hscif0_data_pins[] = { 2003 /* RX, TX */ 2004 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 2005 }; 2006 static const unsigned int hscif0_data_mux[] = { 2007 HRX0_MARK, HTX0_MARK, 2008 }; 2009 static const unsigned int hscif0_clk_pins[] = { 2010 /* SCK */ 2011 RCAR_GP_PIN(5, 7), 2012 }; 2013 static const unsigned int hscif0_clk_mux[] = { 2014 HSCK0_MARK, 2015 }; 2016 static const unsigned int hscif0_ctrl_pins[] = { 2017 /* RTS, CTS */ 2018 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2019 }; 2020 static const unsigned int hscif0_ctrl_mux[] = { 2021 HRTS0_N_MARK, HCTS0_N_MARK, 2022 }; 2023 static const unsigned int hscif0_data_b_pins[] = { 2024 /* RX, TX */ 2025 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), 2026 }; 2027 static const unsigned int hscif0_data_b_mux[] = { 2028 HRX0_B_MARK, HTX0_B_MARK, 2029 }; 2030 static const unsigned int hscif0_ctrl_b_pins[] = { 2031 /* RTS, CTS */ 2032 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), 2033 }; 2034 static const unsigned int hscif0_ctrl_b_mux[] = { 2035 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 2036 }; 2037 static const unsigned int hscif0_data_c_pins[] = { 2038 /* RX, TX */ 2039 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 2040 }; 2041 static const unsigned int hscif0_data_c_mux[] = { 2042 HRX0_C_MARK, HTX0_C_MARK, 2043 }; 2044 static const unsigned int hscif0_ctrl_c_pins[] = { 2045 /* RTS, CTS */ 2046 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), 2047 }; 2048 static const unsigned int hscif0_ctrl_c_mux[] = { 2049 HRTS0_N_C_MARK, HCTS0_N_C_MARK, 2050 }; 2051 static const unsigned int hscif0_data_d_pins[] = { 2052 /* RX, TX */ 2053 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2054 }; 2055 static const unsigned int hscif0_data_d_mux[] = { 2056 HRX0_D_MARK, HTX0_D_MARK, 2057 }; 2058 static const unsigned int hscif0_ctrl_d_pins[] = { 2059 /* RTS, CTS */ 2060 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), 2061 }; 2062 static const unsigned int hscif0_ctrl_d_mux[] = { 2063 HRTS0_N_D_MARK, HCTS0_N_D_MARK, 2064 }; 2065 static const unsigned int hscif0_data_e_pins[] = { 2066 /* RX, TX */ 2067 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2068 }; 2069 static const unsigned int hscif0_data_e_mux[] = { 2070 HRX0_E_MARK, HTX0_E_MARK, 2071 }; 2072 static const unsigned int hscif0_ctrl_e_pins[] = { 2073 /* RTS, CTS */ 2074 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), 2075 }; 2076 static const unsigned int hscif0_ctrl_e_mux[] = { 2077 HRTS0_N_E_MARK, HCTS0_N_E_MARK, 2078 }; 2079 static const unsigned int hscif0_data_f_pins[] = { 2080 /* RX, TX */ 2081 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), 2082 }; 2083 static const unsigned int hscif0_data_f_mux[] = { 2084 HRX0_F_MARK, HTX0_F_MARK, 2085 }; 2086 static const unsigned int hscif0_ctrl_f_pins[] = { 2087 /* RTS, CTS */ 2088 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), 2089 }; 2090 static const unsigned int hscif0_ctrl_f_mux[] = { 2091 HRTS0_N_F_MARK, HCTS0_N_F_MARK, 2092 }; 2093 /* - HSCIF1 ----------------------------------------------------------------- */ 2094 static const unsigned int hscif1_data_pins[] = { 2095 /* RX, TX */ 2096 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2097 }; 2098 static const unsigned int hscif1_data_mux[] = { 2099 HRX1_MARK, HTX1_MARK, 2100 }; 2101 static const unsigned int hscif1_clk_pins[] = { 2102 /* SCK */ 2103 RCAR_GP_PIN(4, 27), 2104 }; 2105 static const unsigned int hscif1_clk_mux[] = { 2106 HSCK1_MARK, 2107 }; 2108 static const unsigned int hscif1_ctrl_pins[] = { 2109 /* RTS, CTS */ 2110 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2111 }; 2112 static const unsigned int hscif1_ctrl_mux[] = { 2113 HRTS1_N_MARK, HCTS1_N_MARK, 2114 }; 2115 static const unsigned int hscif1_data_b_pins[] = { 2116 /* RX, TX */ 2117 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), 2118 }; 2119 static const unsigned int hscif1_data_b_mux[] = { 2120 HRX1_B_MARK, HTX1_B_MARK, 2121 }; 2122 static const unsigned int hscif1_clk_b_pins[] = { 2123 /* SCK */ 2124 RCAR_GP_PIN(1, 28), 2125 }; 2126 static const unsigned int hscif1_clk_b_mux[] = { 2127 HSCK1_B_MARK, 2128 }; 2129 static const unsigned int hscif1_ctrl_b_pins[] = { 2130 /* RTS, CTS */ 2131 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2132 }; 2133 static const unsigned int hscif1_ctrl_b_mux[] = { 2134 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2135 }; 2136 /* - I2C0 ------------------------------------------------------------------- */ 2137 static const unsigned int i2c0_pins[] = { 2138 /* SCL, SDA */ 2139 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), 2140 }; 2141 static const unsigned int i2c0_mux[] = { 2142 I2C0_SCL_MARK, I2C0_SDA_MARK, 2143 }; 2144 /* - I2C1 ------------------------------------------------------------------- */ 2145 static const unsigned int i2c1_pins[] = { 2146 /* SCL, SDA */ 2147 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2148 }; 2149 static const unsigned int i2c1_mux[] = { 2150 I2C1_SCL_MARK, I2C1_SDA_MARK, 2151 }; 2152 static const unsigned int i2c1_b_pins[] = { 2153 /* SCL, SDA */ 2154 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2155 }; 2156 static const unsigned int i2c1_b_mux[] = { 2157 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 2158 }; 2159 static const unsigned int i2c1_c_pins[] = { 2160 /* SCL, SDA */ 2161 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2162 }; 2163 static const unsigned int i2c1_c_mux[] = { 2164 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 2165 }; 2166 /* - I2C2 ------------------------------------------------------------------- */ 2167 static const unsigned int i2c2_pins[] = { 2168 /* SCL, SDA */ 2169 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2170 }; 2171 static const unsigned int i2c2_mux[] = { 2172 I2C2_SCL_MARK, I2C2_SDA_MARK, 2173 }; 2174 static const unsigned int i2c2_b_pins[] = { 2175 /* SCL, SDA */ 2176 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2177 }; 2178 static const unsigned int i2c2_b_mux[] = { 2179 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2180 }; 2181 static const unsigned int i2c2_c_pins[] = { 2182 /* SCL, SDA */ 2183 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2184 }; 2185 static const unsigned int i2c2_c_mux[] = { 2186 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2187 }; 2188 static const unsigned int i2c2_d_pins[] = { 2189 /* SCL, SDA */ 2190 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2191 }; 2192 static const unsigned int i2c2_d_mux[] = { 2193 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2194 }; 2195 static const unsigned int i2c2_e_pins[] = { 2196 /* SCL, SDA */ 2197 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2198 }; 2199 static const unsigned int i2c2_e_mux[] = { 2200 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, 2201 }; 2202 /* - I2C3 ------------------------------------------------------------------- */ 2203 static const unsigned int i2c3_pins[] = { 2204 /* SCL, SDA */ 2205 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), 2206 }; 2207 static const unsigned int i2c3_mux[] = { 2208 I2C3_SCL_MARK, I2C3_SDA_MARK, 2209 }; 2210 /* - IIC0 (I2C4) ------------------------------------------------------------ */ 2211 static const unsigned int iic0_pins[] = { 2212 /* SCL, SDA */ 2213 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), 2214 }; 2215 static const unsigned int iic0_mux[] = { 2216 IIC0_SCL_MARK, IIC0_SDA_MARK, 2217 }; 2218 /* - IIC1 (I2C5) ------------------------------------------------------------ */ 2219 static const unsigned int iic1_pins[] = { 2220 /* SCL, SDA */ 2221 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2222 }; 2223 static const unsigned int iic1_mux[] = { 2224 IIC1_SCL_MARK, IIC1_SDA_MARK, 2225 }; 2226 static const unsigned int iic1_b_pins[] = { 2227 /* SCL, SDA */ 2228 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2229 }; 2230 static const unsigned int iic1_b_mux[] = { 2231 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, 2232 }; 2233 static const unsigned int iic1_c_pins[] = { 2234 /* SCL, SDA */ 2235 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2236 }; 2237 static const unsigned int iic1_c_mux[] = { 2238 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, 2239 }; 2240 /* - IIC2 (I2C6) ------------------------------------------------------------ */ 2241 static const unsigned int iic2_pins[] = { 2242 /* SCL, SDA */ 2243 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2244 }; 2245 static const unsigned int iic2_mux[] = { 2246 IIC2_SCL_MARK, IIC2_SDA_MARK, 2247 }; 2248 static const unsigned int iic2_b_pins[] = { 2249 /* SCL, SDA */ 2250 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2251 }; 2252 static const unsigned int iic2_b_mux[] = { 2253 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK, 2254 }; 2255 static const unsigned int iic2_c_pins[] = { 2256 /* SCL, SDA */ 2257 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2258 }; 2259 static const unsigned int iic2_c_mux[] = { 2260 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK, 2261 }; 2262 static const unsigned int iic2_d_pins[] = { 2263 /* SCL, SDA */ 2264 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2265 }; 2266 static const unsigned int iic2_d_mux[] = { 2267 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK, 2268 }; 2269 static const unsigned int iic2_e_pins[] = { 2270 /* SCL, SDA */ 2271 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2272 }; 2273 static const unsigned int iic2_e_mux[] = { 2274 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK, 2275 }; 2276 /* - IIC3 (I2C7) ------------------------------------------------------------ */ 2277 static const unsigned int iic3_pins[] = { 2278 /* SCL, SDA */ 2279 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), 2280 }; 2281 static const unsigned int iic3_mux[] = { 2282 IIC3_SCL_MARK, IIC3_SDA_MARK, 2283 }; 2284 /* - INTC ------------------------------------------------------------------- */ 2285 static const unsigned int intc_irq0_pins[] = { 2286 /* IRQ */ 2287 RCAR_GP_PIN(1, 25), 2288 }; 2289 static const unsigned int intc_irq0_mux[] = { 2290 IRQ0_MARK, 2291 }; 2292 static const unsigned int intc_irq1_pins[] = { 2293 /* IRQ */ 2294 RCAR_GP_PIN(1, 27), 2295 }; 2296 static const unsigned int intc_irq1_mux[] = { 2297 IRQ1_MARK, 2298 }; 2299 static const unsigned int intc_irq2_pins[] = { 2300 /* IRQ */ 2301 RCAR_GP_PIN(1, 29), 2302 }; 2303 static const unsigned int intc_irq2_mux[] = { 2304 IRQ2_MARK, 2305 }; 2306 static const unsigned int intc_irq3_pins[] = { 2307 /* IRQ */ 2308 RCAR_GP_PIN(1, 23), 2309 }; 2310 static const unsigned int intc_irq3_mux[] = { 2311 IRQ3_MARK, 2312 }; 2313 /* - MLB+ ------------------------------------------------------------------- */ 2314 static const unsigned int mlb_3pin_pins[] = { 2315 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2316 }; 2317 static const unsigned int mlb_3pin_mux[] = { 2318 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2319 }; 2320 /* - MMCIF0 ----------------------------------------------------------------- */ 2321 static const unsigned int mmc0_data1_pins[] = { 2322 /* D[0] */ 2323 RCAR_GP_PIN(3, 18), 2324 }; 2325 static const unsigned int mmc0_data1_mux[] = { 2326 MMC0_D0_MARK, 2327 }; 2328 static const unsigned int mmc0_data4_pins[] = { 2329 /* D[0:3] */ 2330 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2331 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2332 }; 2333 static const unsigned int mmc0_data4_mux[] = { 2334 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2335 }; 2336 static const unsigned int mmc0_data8_pins[] = { 2337 /* D[0:7] */ 2338 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2339 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2340 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2341 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2342 }; 2343 static const unsigned int mmc0_data8_mux[] = { 2344 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2345 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, 2346 }; 2347 static const unsigned int mmc0_ctrl_pins[] = { 2348 /* CLK, CMD */ 2349 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 2350 }; 2351 static const unsigned int mmc0_ctrl_mux[] = { 2352 MMC0_CLK_MARK, MMC0_CMD_MARK, 2353 }; 2354 /* - MMCIF1 ----------------------------------------------------------------- */ 2355 static const unsigned int mmc1_data1_pins[] = { 2356 /* D[0] */ 2357 RCAR_GP_PIN(3, 26), 2358 }; 2359 static const unsigned int mmc1_data1_mux[] = { 2360 MMC1_D0_MARK, 2361 }; 2362 static const unsigned int mmc1_data4_pins[] = { 2363 /* D[0:3] */ 2364 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2365 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2366 }; 2367 static const unsigned int mmc1_data4_mux[] = { 2368 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2369 }; 2370 static const unsigned int mmc1_data8_pins[] = { 2371 /* D[0:7] */ 2372 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2373 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2374 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2375 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2376 }; 2377 static const unsigned int mmc1_data8_mux[] = { 2378 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2379 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, 2380 }; 2381 static const unsigned int mmc1_ctrl_pins[] = { 2382 /* CLK, CMD */ 2383 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 2384 }; 2385 static const unsigned int mmc1_ctrl_mux[] = { 2386 MMC1_CLK_MARK, MMC1_CMD_MARK, 2387 }; 2388 /* - MSIOF0 ----------------------------------------------------------------- */ 2389 static const unsigned int msiof0_clk_pins[] = { 2390 /* SCK */ 2391 RCAR_GP_PIN(5, 12), 2392 }; 2393 static const unsigned int msiof0_clk_mux[] = { 2394 MSIOF0_SCK_MARK, 2395 }; 2396 static const unsigned int msiof0_sync_pins[] = { 2397 /* SYNC */ 2398 RCAR_GP_PIN(5, 13), 2399 }; 2400 static const unsigned int msiof0_sync_mux[] = { 2401 MSIOF0_SYNC_MARK, 2402 }; 2403 static const unsigned int msiof0_ss1_pins[] = { 2404 /* SS1 */ 2405 RCAR_GP_PIN(5, 14), 2406 }; 2407 static const unsigned int msiof0_ss1_mux[] = { 2408 MSIOF0_SS1_MARK, 2409 }; 2410 static const unsigned int msiof0_ss2_pins[] = { 2411 /* SS2 */ 2412 RCAR_GP_PIN(5, 16), 2413 }; 2414 static const unsigned int msiof0_ss2_mux[] = { 2415 MSIOF0_SS2_MARK, 2416 }; 2417 static const unsigned int msiof0_rx_pins[] = { 2418 /* RXD */ 2419 RCAR_GP_PIN(5, 17), 2420 }; 2421 static const unsigned int msiof0_rx_mux[] = { 2422 MSIOF0_RXD_MARK, 2423 }; 2424 static const unsigned int msiof0_tx_pins[] = { 2425 /* TXD */ 2426 RCAR_GP_PIN(5, 15), 2427 }; 2428 static const unsigned int msiof0_tx_mux[] = { 2429 MSIOF0_TXD_MARK, 2430 }; 2431 2432 static const unsigned int msiof0_clk_b_pins[] = { 2433 /* SCK */ 2434 RCAR_GP_PIN(1, 23), 2435 }; 2436 static const unsigned int msiof0_clk_b_mux[] = { 2437 MSIOF0_SCK_B_MARK, 2438 }; 2439 static const unsigned int msiof0_ss1_b_pins[] = { 2440 /* SS1 */ 2441 RCAR_GP_PIN(1, 12), 2442 }; 2443 static const unsigned int msiof0_ss1_b_mux[] = { 2444 MSIOF0_SS1_B_MARK, 2445 }; 2446 static const unsigned int msiof0_ss2_b_pins[] = { 2447 /* SS2 */ 2448 RCAR_GP_PIN(1, 10), 2449 }; 2450 static const unsigned int msiof0_ss2_b_mux[] = { 2451 MSIOF0_SS2_B_MARK, 2452 }; 2453 static const unsigned int msiof0_rx_b_pins[] = { 2454 /* RXD */ 2455 RCAR_GP_PIN(1, 29), 2456 }; 2457 static const unsigned int msiof0_rx_b_mux[] = { 2458 MSIOF0_RXD_B_MARK, 2459 }; 2460 static const unsigned int msiof0_tx_b_pins[] = { 2461 /* TXD */ 2462 RCAR_GP_PIN(1, 28), 2463 }; 2464 static const unsigned int msiof0_tx_b_mux[] = { 2465 MSIOF0_TXD_B_MARK, 2466 }; 2467 /* - MSIOF1 ----------------------------------------------------------------- */ 2468 static const unsigned int msiof1_clk_pins[] = { 2469 /* SCK */ 2470 RCAR_GP_PIN(4, 8), 2471 }; 2472 static const unsigned int msiof1_clk_mux[] = { 2473 MSIOF1_SCK_MARK, 2474 }; 2475 static const unsigned int msiof1_sync_pins[] = { 2476 /* SYNC */ 2477 RCAR_GP_PIN(4, 9), 2478 }; 2479 static const unsigned int msiof1_sync_mux[] = { 2480 MSIOF1_SYNC_MARK, 2481 }; 2482 static const unsigned int msiof1_ss1_pins[] = { 2483 /* SS1 */ 2484 RCAR_GP_PIN(4, 10), 2485 }; 2486 static const unsigned int msiof1_ss1_mux[] = { 2487 MSIOF1_SS1_MARK, 2488 }; 2489 static const unsigned int msiof1_ss2_pins[] = { 2490 /* SS2 */ 2491 RCAR_GP_PIN(4, 11), 2492 }; 2493 static const unsigned int msiof1_ss2_mux[] = { 2494 MSIOF1_SS2_MARK, 2495 }; 2496 static const unsigned int msiof1_rx_pins[] = { 2497 /* RXD */ 2498 RCAR_GP_PIN(4, 13), 2499 }; 2500 static const unsigned int msiof1_rx_mux[] = { 2501 MSIOF1_RXD_MARK, 2502 }; 2503 static const unsigned int msiof1_tx_pins[] = { 2504 /* TXD */ 2505 RCAR_GP_PIN(4, 12), 2506 }; 2507 static const unsigned int msiof1_tx_mux[] = { 2508 MSIOF1_TXD_MARK, 2509 }; 2510 2511 static const unsigned int msiof1_clk_b_pins[] = { 2512 /* SCK */ 2513 RCAR_GP_PIN(1, 16), 2514 }; 2515 static const unsigned int msiof1_clk_b_mux[] = { 2516 MSIOF1_SCK_B_MARK, 2517 }; 2518 static const unsigned int msiof1_ss1_b_pins[] = { 2519 /* SS1 */ 2520 RCAR_GP_PIN(0, 18), 2521 }; 2522 static const unsigned int msiof1_ss1_b_mux[] = { 2523 MSIOF1_SS1_B_MARK, 2524 }; 2525 static const unsigned int msiof1_ss2_b_pins[] = { 2526 /* SS2 */ 2527 RCAR_GP_PIN(0, 19), 2528 }; 2529 static const unsigned int msiof1_ss2_b_mux[] = { 2530 MSIOF1_SS2_B_MARK, 2531 }; 2532 static const unsigned int msiof1_rx_b_pins[] = { 2533 /* RXD */ 2534 RCAR_GP_PIN(1, 17), 2535 }; 2536 static const unsigned int msiof1_rx_b_mux[] = { 2537 MSIOF1_RXD_B_MARK, 2538 }; 2539 static const unsigned int msiof1_tx_b_pins[] = { 2540 /* TXD */ 2541 RCAR_GP_PIN(0, 20), 2542 }; 2543 static const unsigned int msiof1_tx_b_mux[] = { 2544 MSIOF1_TXD_B_MARK, 2545 }; 2546 /* - MSIOF2 ----------------------------------------------------------------- */ 2547 static const unsigned int msiof2_clk_pins[] = { 2548 /* SCK */ 2549 RCAR_GP_PIN(0, 27), 2550 }; 2551 static const unsigned int msiof2_clk_mux[] = { 2552 MSIOF2_SCK_MARK, 2553 }; 2554 static const unsigned int msiof2_sync_pins[] = { 2555 /* SYNC */ 2556 RCAR_GP_PIN(0, 26), 2557 }; 2558 static const unsigned int msiof2_sync_mux[] = { 2559 MSIOF2_SYNC_MARK, 2560 }; 2561 static const unsigned int msiof2_ss1_pins[] = { 2562 /* SS1 */ 2563 RCAR_GP_PIN(0, 30), 2564 }; 2565 static const unsigned int msiof2_ss1_mux[] = { 2566 MSIOF2_SS1_MARK, 2567 }; 2568 static const unsigned int msiof2_ss2_pins[] = { 2569 /* SS2 */ 2570 RCAR_GP_PIN(0, 31), 2571 }; 2572 static const unsigned int msiof2_ss2_mux[] = { 2573 MSIOF2_SS2_MARK, 2574 }; 2575 static const unsigned int msiof2_rx_pins[] = { 2576 /* RXD */ 2577 RCAR_GP_PIN(0, 29), 2578 }; 2579 static const unsigned int msiof2_rx_mux[] = { 2580 MSIOF2_RXD_MARK, 2581 }; 2582 static const unsigned int msiof2_tx_pins[] = { 2583 /* TXD */ 2584 RCAR_GP_PIN(0, 28), 2585 }; 2586 static const unsigned int msiof2_tx_mux[] = { 2587 MSIOF2_TXD_MARK, 2588 }; 2589 /* - MSIOF3 ----------------------------------------------------------------- */ 2590 static const unsigned int msiof3_clk_pins[] = { 2591 /* SCK */ 2592 RCAR_GP_PIN(5, 4), 2593 }; 2594 static const unsigned int msiof3_clk_mux[] = { 2595 MSIOF3_SCK_MARK, 2596 }; 2597 static const unsigned int msiof3_sync_pins[] = { 2598 /* SYNC */ 2599 RCAR_GP_PIN(4, 30), 2600 }; 2601 static const unsigned int msiof3_sync_mux[] = { 2602 MSIOF3_SYNC_MARK, 2603 }; 2604 static const unsigned int msiof3_ss1_pins[] = { 2605 /* SS1 */ 2606 RCAR_GP_PIN(4, 31), 2607 }; 2608 static const unsigned int msiof3_ss1_mux[] = { 2609 MSIOF3_SS1_MARK, 2610 }; 2611 static const unsigned int msiof3_ss2_pins[] = { 2612 /* SS2 */ 2613 RCAR_GP_PIN(4, 27), 2614 }; 2615 static const unsigned int msiof3_ss2_mux[] = { 2616 MSIOF3_SS2_MARK, 2617 }; 2618 static const unsigned int msiof3_rx_pins[] = { 2619 /* RXD */ 2620 RCAR_GP_PIN(5, 2), 2621 }; 2622 static const unsigned int msiof3_rx_mux[] = { 2623 MSIOF3_RXD_MARK, 2624 }; 2625 static const unsigned int msiof3_tx_pins[] = { 2626 /* TXD */ 2627 RCAR_GP_PIN(5, 3), 2628 }; 2629 static const unsigned int msiof3_tx_mux[] = { 2630 MSIOF3_TXD_MARK, 2631 }; 2632 2633 static const unsigned int msiof3_clk_b_pins[] = { 2634 /* SCK */ 2635 RCAR_GP_PIN(0, 0), 2636 }; 2637 static const unsigned int msiof3_clk_b_mux[] = { 2638 MSIOF3_SCK_B_MARK, 2639 }; 2640 static const unsigned int msiof3_sync_b_pins[] = { 2641 /* SYNC */ 2642 RCAR_GP_PIN(0, 1), 2643 }; 2644 static const unsigned int msiof3_sync_b_mux[] = { 2645 MSIOF3_SYNC_B_MARK, 2646 }; 2647 static const unsigned int msiof3_rx_b_pins[] = { 2648 /* RXD */ 2649 RCAR_GP_PIN(0, 2), 2650 }; 2651 static const unsigned int msiof3_rx_b_mux[] = { 2652 MSIOF3_RXD_B_MARK, 2653 }; 2654 static const unsigned int msiof3_tx_b_pins[] = { 2655 /* TXD */ 2656 RCAR_GP_PIN(0, 3), 2657 }; 2658 static const unsigned int msiof3_tx_b_mux[] = { 2659 MSIOF3_TXD_B_MARK, 2660 }; 2661 /* - PWM -------------------------------------------------------------------- */ 2662 static const unsigned int pwm0_pins[] = { 2663 RCAR_GP_PIN(5, 29), 2664 }; 2665 static const unsigned int pwm0_mux[] = { 2666 PWM0_MARK, 2667 }; 2668 static const unsigned int pwm0_b_pins[] = { 2669 RCAR_GP_PIN(4, 30), 2670 }; 2671 static const unsigned int pwm0_b_mux[] = { 2672 PWM0_B_MARK, 2673 }; 2674 static const unsigned int pwm1_pins[] = { 2675 RCAR_GP_PIN(5, 30), 2676 }; 2677 static const unsigned int pwm1_mux[] = { 2678 PWM1_MARK, 2679 }; 2680 static const unsigned int pwm1_b_pins[] = { 2681 RCAR_GP_PIN(4, 31), 2682 }; 2683 static const unsigned int pwm1_b_mux[] = { 2684 PWM1_B_MARK, 2685 }; 2686 static const unsigned int pwm2_pins[] = { 2687 RCAR_GP_PIN(5, 31), 2688 }; 2689 static const unsigned int pwm2_mux[] = { 2690 PWM2_MARK, 2691 }; 2692 static const unsigned int pwm3_pins[] = { 2693 RCAR_GP_PIN(0, 16), 2694 }; 2695 static const unsigned int pwm3_mux[] = { 2696 PWM3_MARK, 2697 }; 2698 static const unsigned int pwm4_pins[] = { 2699 RCAR_GP_PIN(0, 17), 2700 }; 2701 static const unsigned int pwm4_mux[] = { 2702 PWM4_MARK, 2703 }; 2704 static const unsigned int pwm5_pins[] = { 2705 RCAR_GP_PIN(0, 18), 2706 }; 2707 static const unsigned int pwm5_mux[] = { 2708 PWM5_MARK, 2709 }; 2710 static const unsigned int pwm6_pins[] = { 2711 RCAR_GP_PIN(0, 19), 2712 }; 2713 static const unsigned int pwm6_mux[] = { 2714 PWM6_MARK, 2715 }; 2716 /* - QSPI ------------------------------------------------------------------- */ 2717 static const unsigned int qspi_ctrl_pins[] = { 2718 /* SPCLK, SSL */ 2719 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 2720 }; 2721 static const unsigned int qspi_ctrl_mux[] = { 2722 SPCLK_MARK, SSL_MARK, 2723 }; 2724 static const unsigned int qspi_data2_pins[] = { 2725 /* MOSI_IO0, MISO_IO1 */ 2726 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 2727 }; 2728 static const unsigned int qspi_data2_mux[] = { 2729 MOSI_IO0_MARK, MISO_IO1_MARK, 2730 }; 2731 static const unsigned int qspi_data4_pins[] = { 2732 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2733 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 2734 RCAR_GP_PIN(1, 8), 2735 }; 2736 static const unsigned int qspi_data4_mux[] = { 2737 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 2738 }; 2739 /* - SCIF0 ------------------------------------------------------------------ */ 2740 static const unsigned int scif0_data_pins[] = { 2741 /* RX, TX */ 2742 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2743 }; 2744 static const unsigned int scif0_data_mux[] = { 2745 RX0_MARK, TX0_MARK, 2746 }; 2747 static const unsigned int scif0_clk_pins[] = { 2748 /* SCK */ 2749 RCAR_GP_PIN(4, 27), 2750 }; 2751 static const unsigned int scif0_clk_mux[] = { 2752 SCK0_MARK, 2753 }; 2754 static const unsigned int scif0_ctrl_pins[] = { 2755 /* RTS, CTS */ 2756 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2757 }; 2758 static const unsigned int scif0_ctrl_mux[] = { 2759 RTS0_N_MARK, CTS0_N_MARK, 2760 }; 2761 static const unsigned int scif0_data_b_pins[] = { 2762 /* RX, TX */ 2763 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 2764 }; 2765 static const unsigned int scif0_data_b_mux[] = { 2766 RX0_B_MARK, TX0_B_MARK, 2767 }; 2768 /* - SCIF1 ------------------------------------------------------------------ */ 2769 static const unsigned int scif1_data_pins[] = { 2770 /* RX, TX */ 2771 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2772 }; 2773 static const unsigned int scif1_data_mux[] = { 2774 RX1_MARK, TX1_MARK, 2775 }; 2776 static const unsigned int scif1_clk_pins[] = { 2777 /* SCK */ 2778 RCAR_GP_PIN(4, 20), 2779 }; 2780 static const unsigned int scif1_clk_mux[] = { 2781 SCK1_MARK, 2782 }; 2783 static const unsigned int scif1_ctrl_pins[] = { 2784 /* RTS, CTS */ 2785 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 2786 }; 2787 static const unsigned int scif1_ctrl_mux[] = { 2788 RTS1_N_MARK, CTS1_N_MARK, 2789 }; 2790 static const unsigned int scif1_data_b_pins[] = { 2791 /* RX, TX */ 2792 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2793 }; 2794 static const unsigned int scif1_data_b_mux[] = { 2795 RX1_B_MARK, TX1_B_MARK, 2796 }; 2797 static const unsigned int scif1_data_c_pins[] = { 2798 /* RX, TX */ 2799 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2800 }; 2801 static const unsigned int scif1_data_c_mux[] = { 2802 RX1_C_MARK, TX1_C_MARK, 2803 }; 2804 static const unsigned int scif1_data_d_pins[] = { 2805 /* RX, TX */ 2806 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2807 }; 2808 static const unsigned int scif1_data_d_mux[] = { 2809 RX1_D_MARK, TX1_D_MARK, 2810 }; 2811 static const unsigned int scif1_clk_d_pins[] = { 2812 /* SCK */ 2813 RCAR_GP_PIN(3, 17), 2814 }; 2815 static const unsigned int scif1_clk_d_mux[] = { 2816 SCK1_D_MARK, 2817 }; 2818 static const unsigned int scif1_data_e_pins[] = { 2819 /* RX, TX */ 2820 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2821 }; 2822 static const unsigned int scif1_data_e_mux[] = { 2823 RX1_E_MARK, TX1_E_MARK, 2824 }; 2825 static const unsigned int scif1_clk_e_pins[] = { 2826 /* SCK */ 2827 RCAR_GP_PIN(2, 20), 2828 }; 2829 static const unsigned int scif1_clk_e_mux[] = { 2830 SCK1_E_MARK, 2831 }; 2832 /* - SCIF2 ------------------------------------------------------------------ */ 2833 static const unsigned int scif2_data_pins[] = { 2834 /* RX, TX */ 2835 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 2836 }; 2837 static const unsigned int scif2_data_mux[] = { 2838 RX2_MARK, TX2_MARK, 2839 }; 2840 static const unsigned int scif2_clk_pins[] = { 2841 /* SCK */ 2842 RCAR_GP_PIN(5, 4), 2843 }; 2844 static const unsigned int scif2_clk_mux[] = { 2845 SCK2_MARK, 2846 }; 2847 static const unsigned int scif2_data_b_pins[] = { 2848 /* RX, TX */ 2849 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2850 }; 2851 static const unsigned int scif2_data_b_mux[] = { 2852 RX2_B_MARK, TX2_B_MARK, 2853 }; 2854 /* - SCIFA0 ----------------------------------------------------------------- */ 2855 static const unsigned int scifa0_data_pins[] = { 2856 /* RXD, TXD */ 2857 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2858 }; 2859 static const unsigned int scifa0_data_mux[] = { 2860 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 2861 }; 2862 static const unsigned int scifa0_clk_pins[] = { 2863 /* SCK */ 2864 RCAR_GP_PIN(4, 27), 2865 }; 2866 static const unsigned int scifa0_clk_mux[] = { 2867 SCIFA0_SCK_MARK, 2868 }; 2869 static const unsigned int scifa0_ctrl_pins[] = { 2870 /* RTS, CTS */ 2871 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2872 }; 2873 static const unsigned int scifa0_ctrl_mux[] = { 2874 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, 2875 }; 2876 static const unsigned int scifa0_data_b_pins[] = { 2877 /* RXD, TXD */ 2878 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), 2879 }; 2880 static const unsigned int scifa0_data_b_mux[] = { 2881 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 2882 }; 2883 static const unsigned int scifa0_clk_b_pins[] = { 2884 /* SCK */ 2885 RCAR_GP_PIN(1, 19), 2886 }; 2887 static const unsigned int scifa0_clk_b_mux[] = { 2888 SCIFA0_SCK_B_MARK, 2889 }; 2890 static const unsigned int scifa0_ctrl_b_pins[] = { 2891 /* RTS, CTS */ 2892 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), 2893 }; 2894 static const unsigned int scifa0_ctrl_b_mux[] = { 2895 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, 2896 }; 2897 /* - SCIFA1 ----------------------------------------------------------------- */ 2898 static const unsigned int scifa1_data_pins[] = { 2899 /* RXD, TXD */ 2900 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2901 }; 2902 static const unsigned int scifa1_data_mux[] = { 2903 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 2904 }; 2905 static const unsigned int scifa1_clk_pins[] = { 2906 /* SCK */ 2907 RCAR_GP_PIN(4, 20), 2908 }; 2909 static const unsigned int scifa1_clk_mux[] = { 2910 SCIFA1_SCK_MARK, 2911 }; 2912 static const unsigned int scifa1_ctrl_pins[] = { 2913 /* RTS, CTS */ 2914 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 2915 }; 2916 static const unsigned int scifa1_ctrl_mux[] = { 2917 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, 2918 }; 2919 static const unsigned int scifa1_data_b_pins[] = { 2920 /* RXD, TXD */ 2921 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), 2922 }; 2923 static const unsigned int scifa1_data_b_mux[] = { 2924 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 2925 }; 2926 static const unsigned int scifa1_clk_b_pins[] = { 2927 /* SCK */ 2928 RCAR_GP_PIN(0, 23), 2929 }; 2930 static const unsigned int scifa1_clk_b_mux[] = { 2931 SCIFA1_SCK_B_MARK, 2932 }; 2933 static const unsigned int scifa1_ctrl_b_pins[] = { 2934 /* RTS, CTS */ 2935 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), 2936 }; 2937 static const unsigned int scifa1_ctrl_b_mux[] = { 2938 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, 2939 }; 2940 static const unsigned int scifa1_data_c_pins[] = { 2941 /* RXD, TXD */ 2942 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 2943 }; 2944 static const unsigned int scifa1_data_c_mux[] = { 2945 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 2946 }; 2947 static const unsigned int scifa1_clk_c_pins[] = { 2948 /* SCK */ 2949 RCAR_GP_PIN(0, 8), 2950 }; 2951 static const unsigned int scifa1_clk_c_mux[] = { 2952 SCIFA1_SCK_C_MARK, 2953 }; 2954 static const unsigned int scifa1_ctrl_c_pins[] = { 2955 /* RTS, CTS */ 2956 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), 2957 }; 2958 static const unsigned int scifa1_ctrl_c_mux[] = { 2959 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, 2960 }; 2961 static const unsigned int scifa1_data_d_pins[] = { 2962 /* RXD, TXD */ 2963 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 2964 }; 2965 static const unsigned int scifa1_data_d_mux[] = { 2966 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, 2967 }; 2968 static const unsigned int scifa1_clk_d_pins[] = { 2969 /* SCK */ 2970 RCAR_GP_PIN(2, 10), 2971 }; 2972 static const unsigned int scifa1_clk_d_mux[] = { 2973 SCIFA1_SCK_D_MARK, 2974 }; 2975 static const unsigned int scifa1_ctrl_d_pins[] = { 2976 /* RTS, CTS */ 2977 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 2978 }; 2979 static const unsigned int scifa1_ctrl_d_mux[] = { 2980 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, 2981 }; 2982 /* - SCIFA2 ----------------------------------------------------------------- */ 2983 static const unsigned int scifa2_data_pins[] = { 2984 /* RXD, TXD */ 2985 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2986 }; 2987 static const unsigned int scifa2_data_mux[] = { 2988 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 2989 }; 2990 static const unsigned int scifa2_clk_pins[] = { 2991 /* SCK */ 2992 RCAR_GP_PIN(5, 4), 2993 }; 2994 static const unsigned int scifa2_clk_mux[] = { 2995 SCIFA2_SCK_MARK, 2996 }; 2997 static const unsigned int scifa2_ctrl_pins[] = { 2998 /* RTS, CTS */ 2999 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), 3000 }; 3001 static const unsigned int scifa2_ctrl_mux[] = { 3002 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, 3003 }; 3004 static const unsigned int scifa2_data_b_pins[] = { 3005 /* RXD, TXD */ 3006 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 3007 }; 3008 static const unsigned int scifa2_data_b_mux[] = { 3009 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 3010 }; 3011 static const unsigned int scifa2_data_c_pins[] = { 3012 /* RXD, TXD */ 3013 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), 3014 }; 3015 static const unsigned int scifa2_data_c_mux[] = { 3016 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, 3017 }; 3018 static const unsigned int scifa2_clk_c_pins[] = { 3019 /* SCK */ 3020 RCAR_GP_PIN(5, 29), 3021 }; 3022 static const unsigned int scifa2_clk_c_mux[] = { 3023 SCIFA2_SCK_C_MARK, 3024 }; 3025 /* - SCIFB0 ----------------------------------------------------------------- */ 3026 static const unsigned int scifb0_data_pins[] = { 3027 /* RXD, TXD */ 3028 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3029 }; 3030 static const unsigned int scifb0_data_mux[] = { 3031 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 3032 }; 3033 static const unsigned int scifb0_clk_pins[] = { 3034 /* SCK */ 3035 RCAR_GP_PIN(4, 8), 3036 }; 3037 static const unsigned int scifb0_clk_mux[] = { 3038 SCIFB0_SCK_MARK, 3039 }; 3040 static const unsigned int scifb0_ctrl_pins[] = { 3041 /* RTS, CTS */ 3042 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), 3043 }; 3044 static const unsigned int scifb0_ctrl_mux[] = { 3045 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 3046 }; 3047 static const unsigned int scifb0_data_b_pins[] = { 3048 /* RXD, TXD */ 3049 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3050 }; 3051 static const unsigned int scifb0_data_b_mux[] = { 3052 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, 3053 }; 3054 static const unsigned int scifb0_clk_b_pins[] = { 3055 /* SCK */ 3056 RCAR_GP_PIN(3, 9), 3057 }; 3058 static const unsigned int scifb0_clk_b_mux[] = { 3059 SCIFB0_SCK_B_MARK, 3060 }; 3061 static const unsigned int scifb0_ctrl_b_pins[] = { 3062 /* RTS, CTS */ 3063 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 3064 }; 3065 static const unsigned int scifb0_ctrl_b_mux[] = { 3066 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, 3067 }; 3068 static const unsigned int scifb0_data_c_pins[] = { 3069 /* RXD, TXD */ 3070 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3071 }; 3072 static const unsigned int scifb0_data_c_mux[] = { 3073 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, 3074 }; 3075 /* - SCIFB1 ----------------------------------------------------------------- */ 3076 static const unsigned int scifb1_data_pins[] = { 3077 /* RXD, TXD */ 3078 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3079 }; 3080 static const unsigned int scifb1_data_mux[] = { 3081 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3082 }; 3083 static const unsigned int scifb1_clk_pins[] = { 3084 /* SCK */ 3085 RCAR_GP_PIN(4, 14), 3086 }; 3087 static const unsigned int scifb1_clk_mux[] = { 3088 SCIFB1_SCK_MARK, 3089 }; 3090 static const unsigned int scifb1_ctrl_pins[] = { 3091 /* RTS, CTS */ 3092 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), 3093 }; 3094 static const unsigned int scifb1_ctrl_mux[] = { 3095 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, 3096 }; 3097 static const unsigned int scifb1_data_b_pins[] = { 3098 /* RXD, TXD */ 3099 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3100 }; 3101 static const unsigned int scifb1_data_b_mux[] = { 3102 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, 3103 }; 3104 static const unsigned int scifb1_clk_b_pins[] = { 3105 /* SCK */ 3106 RCAR_GP_PIN(3, 1), 3107 }; 3108 static const unsigned int scifb1_clk_b_mux[] = { 3109 SCIFB1_SCK_B_MARK, 3110 }; 3111 static const unsigned int scifb1_ctrl_b_pins[] = { 3112 /* RTS, CTS */ 3113 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), 3114 }; 3115 static const unsigned int scifb1_ctrl_b_mux[] = { 3116 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, 3117 }; 3118 static const unsigned int scifb1_data_c_pins[] = { 3119 /* RXD, TXD */ 3120 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3121 }; 3122 static const unsigned int scifb1_data_c_mux[] = { 3123 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, 3124 }; 3125 static const unsigned int scifb1_data_d_pins[] = { 3126 /* RXD, TXD */ 3127 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 3128 }; 3129 static const unsigned int scifb1_data_d_mux[] = { 3130 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, 3131 }; 3132 static const unsigned int scifb1_data_e_pins[] = { 3133 /* RXD, TXD */ 3134 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 3135 }; 3136 static const unsigned int scifb1_data_e_mux[] = { 3137 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, 3138 }; 3139 static const unsigned int scifb1_clk_e_pins[] = { 3140 /* SCK */ 3141 RCAR_GP_PIN(3, 17), 3142 }; 3143 static const unsigned int scifb1_clk_e_mux[] = { 3144 SCIFB1_SCK_E_MARK, 3145 }; 3146 static const unsigned int scifb1_data_f_pins[] = { 3147 /* RXD, TXD */ 3148 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3149 }; 3150 static const unsigned int scifb1_data_f_mux[] = { 3151 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, 3152 }; 3153 static const unsigned int scifb1_data_g_pins[] = { 3154 /* RXD, TXD */ 3155 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 3156 }; 3157 static const unsigned int scifb1_data_g_mux[] = { 3158 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, 3159 }; 3160 static const unsigned int scifb1_clk_g_pins[] = { 3161 /* SCK */ 3162 RCAR_GP_PIN(2, 20), 3163 }; 3164 static const unsigned int scifb1_clk_g_mux[] = { 3165 SCIFB1_SCK_G_MARK, 3166 }; 3167 /* - SCIFB2 ----------------------------------------------------------------- */ 3168 static const unsigned int scifb2_data_pins[] = { 3169 /* RXD, TXD */ 3170 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 3171 }; 3172 static const unsigned int scifb2_data_mux[] = { 3173 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3174 }; 3175 static const unsigned int scifb2_clk_pins[] = { 3176 /* SCK */ 3177 RCAR_GP_PIN(4, 21), 3178 }; 3179 static const unsigned int scifb2_clk_mux[] = { 3180 SCIFB2_SCK_MARK, 3181 }; 3182 static const unsigned int scifb2_ctrl_pins[] = { 3183 /* RTS, CTS */ 3184 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), 3185 }; 3186 static const unsigned int scifb2_ctrl_mux[] = { 3187 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3188 }; 3189 static const unsigned int scifb2_data_b_pins[] = { 3190 /* RXD, TXD */ 3191 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), 3192 }; 3193 static const unsigned int scifb2_data_b_mux[] = { 3194 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, 3195 }; 3196 static const unsigned int scifb2_clk_b_pins[] = { 3197 /* SCK */ 3198 RCAR_GP_PIN(0, 31), 3199 }; 3200 static const unsigned int scifb2_clk_b_mux[] = { 3201 SCIFB2_SCK_B_MARK, 3202 }; 3203 static const unsigned int scifb2_ctrl_b_pins[] = { 3204 /* RTS, CTS */ 3205 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), 3206 }; 3207 static const unsigned int scifb2_ctrl_b_mux[] = { 3208 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, 3209 }; 3210 static const unsigned int scifb2_data_c_pins[] = { 3211 /* RXD, TXD */ 3212 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3213 }; 3214 static const unsigned int scifb2_data_c_mux[] = { 3215 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 3216 }; 3217 /* - SCIF Clock ------------------------------------------------------------- */ 3218 static const unsigned int scif_clk_pins[] = { 3219 /* SCIF_CLK */ 3220 RCAR_GP_PIN(4, 26), 3221 }; 3222 static const unsigned int scif_clk_mux[] = { 3223 SCIF_CLK_MARK, 3224 }; 3225 static const unsigned int scif_clk_b_pins[] = { 3226 /* SCIF_CLK */ 3227 RCAR_GP_PIN(5, 4), 3228 }; 3229 static const unsigned int scif_clk_b_mux[] = { 3230 SCIF_CLK_B_MARK, 3231 }; 3232 /* - SDHI0 ------------------------------------------------------------------ */ 3233 static const unsigned int sdhi0_data1_pins[] = { 3234 /* D0 */ 3235 RCAR_GP_PIN(3, 2), 3236 }; 3237 static const unsigned int sdhi0_data1_mux[] = { 3238 SD0_DAT0_MARK, 3239 }; 3240 static const unsigned int sdhi0_data4_pins[] = { 3241 /* D[0:3] */ 3242 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3243 }; 3244 static const unsigned int sdhi0_data4_mux[] = { 3245 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, 3246 }; 3247 static const unsigned int sdhi0_ctrl_pins[] = { 3248 /* CLK, CMD */ 3249 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3250 }; 3251 static const unsigned int sdhi0_ctrl_mux[] = { 3252 SD0_CLK_MARK, SD0_CMD_MARK, 3253 }; 3254 static const unsigned int sdhi0_cd_pins[] = { 3255 /* CD */ 3256 RCAR_GP_PIN(3, 6), 3257 }; 3258 static const unsigned int sdhi0_cd_mux[] = { 3259 SD0_CD_MARK, 3260 }; 3261 static const unsigned int sdhi0_wp_pins[] = { 3262 /* WP */ 3263 RCAR_GP_PIN(3, 7), 3264 }; 3265 static const unsigned int sdhi0_wp_mux[] = { 3266 SD0_WP_MARK, 3267 }; 3268 /* - SDHI1 ------------------------------------------------------------------ */ 3269 static const unsigned int sdhi1_data1_pins[] = { 3270 /* D0 */ 3271 RCAR_GP_PIN(3, 10), 3272 }; 3273 static const unsigned int sdhi1_data1_mux[] = { 3274 SD1_DAT0_MARK, 3275 }; 3276 static const unsigned int sdhi1_data4_pins[] = { 3277 /* D[0:3] */ 3278 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3279 }; 3280 static const unsigned int sdhi1_data4_mux[] = { 3281 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, 3282 }; 3283 static const unsigned int sdhi1_ctrl_pins[] = { 3284 /* CLK, CMD */ 3285 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3286 }; 3287 static const unsigned int sdhi1_ctrl_mux[] = { 3288 SD1_CLK_MARK, SD1_CMD_MARK, 3289 }; 3290 static const unsigned int sdhi1_cd_pins[] = { 3291 /* CD */ 3292 RCAR_GP_PIN(3, 14), 3293 }; 3294 static const unsigned int sdhi1_cd_mux[] = { 3295 SD1_CD_MARK, 3296 }; 3297 static const unsigned int sdhi1_wp_pins[] = { 3298 /* WP */ 3299 RCAR_GP_PIN(3, 15), 3300 }; 3301 static const unsigned int sdhi1_wp_mux[] = { 3302 SD1_WP_MARK, 3303 }; 3304 /* - SDHI2 ------------------------------------------------------------------ */ 3305 static const unsigned int sdhi2_data1_pins[] = { 3306 /* D0 */ 3307 RCAR_GP_PIN(3, 18), 3308 }; 3309 static const unsigned int sdhi2_data1_mux[] = { 3310 SD2_DAT0_MARK, 3311 }; 3312 static const unsigned int sdhi2_data4_pins[] = { 3313 /* D[0:3] */ 3314 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 3315 }; 3316 static const unsigned int sdhi2_data4_mux[] = { 3317 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, 3318 }; 3319 static const unsigned int sdhi2_ctrl_pins[] = { 3320 /* CLK, CMD */ 3321 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 3322 }; 3323 static const unsigned int sdhi2_ctrl_mux[] = { 3324 SD2_CLK_MARK, SD2_CMD_MARK, 3325 }; 3326 static const unsigned int sdhi2_cd_pins[] = { 3327 /* CD */ 3328 RCAR_GP_PIN(3, 22), 3329 }; 3330 static const unsigned int sdhi2_cd_mux[] = { 3331 SD2_CD_MARK, 3332 }; 3333 static const unsigned int sdhi2_wp_pins[] = { 3334 /* WP */ 3335 RCAR_GP_PIN(3, 23), 3336 }; 3337 static const unsigned int sdhi2_wp_mux[] = { 3338 SD2_WP_MARK, 3339 }; 3340 /* - SDHI3 ------------------------------------------------------------------ */ 3341 static const unsigned int sdhi3_data1_pins[] = { 3342 /* D0 */ 3343 RCAR_GP_PIN(3, 26), 3344 }; 3345 static const unsigned int sdhi3_data1_mux[] = { 3346 SD3_DAT0_MARK, 3347 }; 3348 static const unsigned int sdhi3_data4_pins[] = { 3349 /* D[0:3] */ 3350 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 3351 }; 3352 static const unsigned int sdhi3_data4_mux[] = { 3353 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, 3354 }; 3355 static const unsigned int sdhi3_ctrl_pins[] = { 3356 /* CLK, CMD */ 3357 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 3358 }; 3359 static const unsigned int sdhi3_ctrl_mux[] = { 3360 SD3_CLK_MARK, SD3_CMD_MARK, 3361 }; 3362 static const unsigned int sdhi3_cd_pins[] = { 3363 /* CD */ 3364 RCAR_GP_PIN(3, 30), 3365 }; 3366 static const unsigned int sdhi3_cd_mux[] = { 3367 SD3_CD_MARK, 3368 }; 3369 static const unsigned int sdhi3_wp_pins[] = { 3370 /* WP */ 3371 RCAR_GP_PIN(3, 31), 3372 }; 3373 static const unsigned int sdhi3_wp_mux[] = { 3374 SD3_WP_MARK, 3375 }; 3376 /* - SSI -------------------------------------------------------------------- */ 3377 static const unsigned int ssi0_data_pins[] = { 3378 /* SDATA0 */ 3379 RCAR_GP_PIN(4, 5), 3380 }; 3381 static const unsigned int ssi0_data_mux[] = { 3382 SSI_SDATA0_MARK, 3383 }; 3384 static const unsigned int ssi0129_ctrl_pins[] = { 3385 /* SCK, WS */ 3386 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), 3387 }; 3388 static const unsigned int ssi0129_ctrl_mux[] = { 3389 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3390 }; 3391 static const unsigned int ssi1_data_pins[] = { 3392 /* SDATA1 */ 3393 RCAR_GP_PIN(4, 6), 3394 }; 3395 static const unsigned int ssi1_data_mux[] = { 3396 SSI_SDATA1_MARK, 3397 }; 3398 static const unsigned int ssi1_ctrl_pins[] = { 3399 /* SCK, WS */ 3400 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24), 3401 }; 3402 static const unsigned int ssi1_ctrl_mux[] = { 3403 SSI_SCK1_MARK, SSI_WS1_MARK, 3404 }; 3405 static const unsigned int ssi2_data_pins[] = { 3406 /* SDATA2 */ 3407 RCAR_GP_PIN(4, 7), 3408 }; 3409 static const unsigned int ssi2_data_mux[] = { 3410 SSI_SDATA2_MARK, 3411 }; 3412 static const unsigned int ssi2_ctrl_pins[] = { 3413 /* SCK, WS */ 3414 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17), 3415 }; 3416 static const unsigned int ssi2_ctrl_mux[] = { 3417 SSI_SCK2_MARK, SSI_WS2_MARK, 3418 }; 3419 static const unsigned int ssi3_data_pins[] = { 3420 /* SDATA3 */ 3421 RCAR_GP_PIN(4, 10), 3422 }; 3423 static const unsigned int ssi3_data_mux[] = { 3424 SSI_SDATA3_MARK 3425 }; 3426 static const unsigned int ssi34_ctrl_pins[] = { 3427 /* SCK, WS */ 3428 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 3429 }; 3430 static const unsigned int ssi34_ctrl_mux[] = { 3431 SSI_SCK34_MARK, SSI_WS34_MARK, 3432 }; 3433 static const unsigned int ssi4_data_pins[] = { 3434 /* SDATA4 */ 3435 RCAR_GP_PIN(4, 13), 3436 }; 3437 static const unsigned int ssi4_data_mux[] = { 3438 SSI_SDATA4_MARK, 3439 }; 3440 static const unsigned int ssi4_ctrl_pins[] = { 3441 /* SCK, WS */ 3442 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3443 }; 3444 static const unsigned int ssi4_ctrl_mux[] = { 3445 SSI_SCK4_MARK, SSI_WS4_MARK, 3446 }; 3447 static const unsigned int ssi5_pins[] = { 3448 /* SDATA5, SCK, WS */ 3449 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 3450 }; 3451 static const unsigned int ssi5_mux[] = { 3452 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK, 3453 }; 3454 static const unsigned int ssi5_b_pins[] = { 3455 /* SDATA5, SCK, WS */ 3456 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3457 }; 3458 static const unsigned int ssi5_b_mux[] = { 3459 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK 3460 }; 3461 static const unsigned int ssi5_c_pins[] = { 3462 /* SDATA5, SCK, WS */ 3463 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3464 }; 3465 static const unsigned int ssi5_c_mux[] = { 3466 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK, 3467 }; 3468 static const unsigned int ssi6_pins[] = { 3469 /* SDATA6, SCK, WS */ 3470 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 3471 }; 3472 static const unsigned int ssi6_mux[] = { 3473 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK, 3474 }; 3475 static const unsigned int ssi6_b_pins[] = { 3476 /* SDATA6, SCK, WS */ 3477 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27), 3478 }; 3479 static const unsigned int ssi6_b_mux[] = { 3480 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK, 3481 }; 3482 static const unsigned int ssi7_data_pins[] = { 3483 /* SDATA7 */ 3484 RCAR_GP_PIN(4, 22), 3485 }; 3486 static const unsigned int ssi7_data_mux[] = { 3487 SSI_SDATA7_MARK, 3488 }; 3489 static const unsigned int ssi7_b_data_pins[] = { 3490 /* SDATA7 */ 3491 RCAR_GP_PIN(4, 22), 3492 }; 3493 static const unsigned int ssi7_b_data_mux[] = { 3494 SSI_SDATA7_B_MARK, 3495 }; 3496 static const unsigned int ssi7_c_data_pins[] = { 3497 /* SDATA7 */ 3498 RCAR_GP_PIN(1, 26), 3499 }; 3500 static const unsigned int ssi7_c_data_mux[] = { 3501 SSI_SDATA7_C_MARK, 3502 }; 3503 static const unsigned int ssi78_ctrl_pins[] = { 3504 /* SCK, WS */ 3505 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 3506 }; 3507 static const unsigned int ssi78_ctrl_mux[] = { 3508 SSI_SCK78_MARK, SSI_WS78_MARK, 3509 }; 3510 static const unsigned int ssi78_b_ctrl_pins[] = { 3511 /* SCK, WS */ 3512 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24), 3513 }; 3514 static const unsigned int ssi78_b_ctrl_mux[] = { 3515 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 3516 }; 3517 static const unsigned int ssi78_c_ctrl_pins[] = { 3518 /* SCK, WS */ 3519 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), 3520 }; 3521 static const unsigned int ssi78_c_ctrl_mux[] = { 3522 SSI_SCK78_C_MARK, SSI_WS78_C_MARK, 3523 }; 3524 static const unsigned int ssi8_data_pins[] = { 3525 /* SDATA8 */ 3526 RCAR_GP_PIN(4, 23), 3527 }; 3528 static const unsigned int ssi8_data_mux[] = { 3529 SSI_SDATA8_MARK, 3530 }; 3531 static const unsigned int ssi8_b_data_pins[] = { 3532 /* SDATA8 */ 3533 RCAR_GP_PIN(4, 23), 3534 }; 3535 static const unsigned int ssi8_b_data_mux[] = { 3536 SSI_SDATA8_B_MARK, 3537 }; 3538 static const unsigned int ssi8_c_data_pins[] = { 3539 /* SDATA8 */ 3540 RCAR_GP_PIN(1, 27), 3541 }; 3542 static const unsigned int ssi8_c_data_mux[] = { 3543 SSI_SDATA8_C_MARK, 3544 }; 3545 static const unsigned int ssi9_data_pins[] = { 3546 /* SDATA9 */ 3547 RCAR_GP_PIN(4, 24), 3548 }; 3549 static const unsigned int ssi9_data_mux[] = { 3550 SSI_SDATA9_MARK, 3551 }; 3552 static const unsigned int ssi9_ctrl_pins[] = { 3553 /* SCK, WS */ 3554 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 3555 }; 3556 static const unsigned int ssi9_ctrl_mux[] = { 3557 SSI_SCK9_MARK, SSI_WS9_MARK, 3558 }; 3559 /* - TPU0 ------------------------------------------------------------------- */ 3560 static const unsigned int tpu0_to0_pins[] = { 3561 /* TO */ 3562 RCAR_GP_PIN(0, 20), 3563 }; 3564 static const unsigned int tpu0_to0_mux[] = { 3565 TPU0TO0_MARK, 3566 }; 3567 static const unsigned int tpu0_to1_pins[] = { 3568 /* TO */ 3569 RCAR_GP_PIN(0, 21), 3570 }; 3571 static const unsigned int tpu0_to1_mux[] = { 3572 TPU0TO1_MARK, 3573 }; 3574 static const unsigned int tpu0_to2_pins[] = { 3575 /* TO */ 3576 RCAR_GP_PIN(0, 22), 3577 }; 3578 static const unsigned int tpu0_to2_mux[] = { 3579 TPU0TO2_MARK, 3580 }; 3581 static const unsigned int tpu0_to3_pins[] = { 3582 /* TO */ 3583 RCAR_GP_PIN(0, 23), 3584 }; 3585 static const unsigned int tpu0_to3_mux[] = { 3586 TPU0TO3_MARK, 3587 }; 3588 /* - USB0 ------------------------------------------------------------------- */ 3589 static const unsigned int usb0_pins[] = { 3590 /* PWEN, OVC/VBUS */ 3591 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 3592 }; 3593 static const unsigned int usb0_mux[] = { 3594 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 3595 }; 3596 static const unsigned int usb0_ovc_vbus_pins[] = { 3597 /* OVC/VBUS */ 3598 RCAR_GP_PIN(5, 19), 3599 }; 3600 static const unsigned int usb0_ovc_vbus_mux[] = { 3601 USB0_OVC_VBUS_MARK, 3602 }; 3603 /* - USB1 ------------------------------------------------------------------- */ 3604 static const unsigned int usb1_pins[] = { 3605 /* PWEN, OVC */ 3606 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), 3607 }; 3608 static const unsigned int usb1_mux[] = { 3609 USB1_PWEN_MARK, USB1_OVC_MARK, 3610 }; 3611 /* - USB2 ------------------------------------------------------------------- */ 3612 static const unsigned int usb2_pins[] = { 3613 /* PWEN, OVC */ 3614 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 3615 }; 3616 static const unsigned int usb2_mux[] = { 3617 USB2_PWEN_MARK, USB2_OVC_MARK, 3618 }; 3619 /* - VIN0 ------------------------------------------------------------------- */ 3620 static const union vin_data vin0_data_pins = { 3621 .data24 = { 3622 /* B */ 3623 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 3624 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3625 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3626 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3627 /* G */ 3628 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3629 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3630 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3631 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3632 /* R */ 3633 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3634 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3635 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3636 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3637 }, 3638 }; 3639 static const union vin_data vin0_data_mux = { 3640 .data24 = { 3641 /* B */ 3642 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 3643 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3644 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3645 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3646 /* G */ 3647 VI0_G0_MARK, VI0_G1_MARK, 3648 VI0_G2_MARK, VI0_G3_MARK, 3649 VI0_G4_MARK, VI0_G5_MARK, 3650 VI0_G6_MARK, VI0_G7_MARK, 3651 /* R */ 3652 VI0_R0_MARK, VI0_R1_MARK, 3653 VI0_R2_MARK, VI0_R3_MARK, 3654 VI0_R4_MARK, VI0_R5_MARK, 3655 VI0_R6_MARK, VI0_R7_MARK, 3656 }, 3657 }; 3658 static const unsigned int vin0_data18_pins[] = { 3659 /* B */ 3660 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3661 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3662 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3663 /* G */ 3664 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3665 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3666 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3667 /* R */ 3668 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3669 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3670 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3671 }; 3672 static const unsigned int vin0_data18_mux[] = { 3673 /* B */ 3674 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3675 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3676 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3677 /* G */ 3678 VI0_G2_MARK, VI0_G3_MARK, 3679 VI0_G4_MARK, VI0_G5_MARK, 3680 VI0_G6_MARK, VI0_G7_MARK, 3681 /* R */ 3682 VI0_R2_MARK, VI0_R3_MARK, 3683 VI0_R4_MARK, VI0_R5_MARK, 3684 VI0_R6_MARK, VI0_R7_MARK, 3685 }; 3686 static const unsigned int vin0_sync_pins[] = { 3687 RCAR_GP_PIN(0, 12), /* HSYNC */ 3688 RCAR_GP_PIN(0, 13), /* VSYNC */ 3689 }; 3690 static const unsigned int vin0_sync_mux[] = { 3691 VI0_HSYNC_N_MARK, 3692 VI0_VSYNC_N_MARK, 3693 }; 3694 static const unsigned int vin0_field_pins[] = { 3695 RCAR_GP_PIN(0, 15), 3696 }; 3697 static const unsigned int vin0_field_mux[] = { 3698 VI0_FIELD_MARK, 3699 }; 3700 static const unsigned int vin0_clkenb_pins[] = { 3701 RCAR_GP_PIN(0, 14), 3702 }; 3703 static const unsigned int vin0_clkenb_mux[] = { 3704 VI0_CLKENB_MARK, 3705 }; 3706 static const unsigned int vin0_clk_pins[] = { 3707 RCAR_GP_PIN(2, 0), 3708 }; 3709 static const unsigned int vin0_clk_mux[] = { 3710 VI0_CLK_MARK, 3711 }; 3712 /* - VIN1 ------------------------------------------------------------------- */ 3713 static const union vin_data vin1_data_pins = { 3714 .data24 = { 3715 /* B */ 3716 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3717 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3718 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3719 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3720 /* G */ 3721 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3722 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3723 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3724 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3725 /* R */ 3726 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3727 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3728 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3729 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3730 }, 3731 }; 3732 static const union vin_data vin1_data_mux = { 3733 .data24 = { 3734 /* B */ 3735 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, 3736 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3737 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3738 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3739 /* G */ 3740 VI1_G0_MARK, VI1_G1_MARK, 3741 VI1_G2_MARK, VI1_G3_MARK, 3742 VI1_G4_MARK, VI1_G5_MARK, 3743 VI1_G6_MARK, VI1_G7_MARK, 3744 /* R */ 3745 VI1_R0_MARK, VI1_R1_MARK, 3746 VI1_R2_MARK, VI1_R3_MARK, 3747 VI1_R4_MARK, VI1_R5_MARK, 3748 VI1_R6_MARK, VI1_R7_MARK, 3749 }, 3750 }; 3751 static const unsigned int vin1_data18_pins[] = { 3752 /* B */ 3753 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3754 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3755 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3756 /* G */ 3757 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3758 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3759 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3760 /* R */ 3761 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3762 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3763 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3764 }; 3765 static const unsigned int vin1_data18_mux[] = { 3766 /* B */ 3767 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3768 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3769 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3770 /* G */ 3771 VI1_G2_MARK, VI1_G3_MARK, 3772 VI1_G4_MARK, VI1_G5_MARK, 3773 VI1_G6_MARK, VI1_G7_MARK, 3774 /* R */ 3775 VI1_R2_MARK, VI1_R3_MARK, 3776 VI1_R4_MARK, VI1_R5_MARK, 3777 VI1_R6_MARK, VI1_R7_MARK, 3778 }; 3779 static const unsigned int vin1_sync_pins[] = { 3780 RCAR_GP_PIN(1, 24), /* HSYNC */ 3781 RCAR_GP_PIN(1, 25), /* VSYNC */ 3782 }; 3783 static const unsigned int vin1_sync_mux[] = { 3784 VI1_HSYNC_N_MARK, 3785 VI1_VSYNC_N_MARK, 3786 }; 3787 static const unsigned int vin1_field_pins[] = { 3788 RCAR_GP_PIN(1, 13), 3789 }; 3790 static const unsigned int vin1_field_mux[] = { 3791 VI1_FIELD_MARK, 3792 }; 3793 static const unsigned int vin1_clkenb_pins[] = { 3794 RCAR_GP_PIN(1, 26), 3795 }; 3796 static const unsigned int vin1_clkenb_mux[] = { 3797 VI1_CLKENB_MARK, 3798 }; 3799 static const unsigned int vin1_clk_pins[] = { 3800 RCAR_GP_PIN(2, 9), 3801 }; 3802 static const unsigned int vin1_clk_mux[] = { 3803 VI1_CLK_MARK, 3804 }; 3805 /* - VIN2 ----------------------------------------------------------------- */ 3806 static const union vin_data vin2_data_pins = { 3807 .data24 = { 3808 /* B */ 3809 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3810 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3811 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3812 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3813 /* G */ 3814 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3815 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 3816 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3817 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3818 /* R */ 3819 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 3820 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3821 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3822 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 3823 }, 3824 }; 3825 static const union vin_data vin2_data_mux = { 3826 .data24 = { 3827 /* B */ 3828 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, 3829 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 3830 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 3831 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 3832 /* G */ 3833 VI2_G0_MARK, VI2_G1_MARK, 3834 VI2_G2_MARK, VI2_G3_MARK, 3835 VI2_G4_MARK, VI2_G5_MARK, 3836 VI2_G6_MARK, VI2_G7_MARK, 3837 /* R */ 3838 VI2_R0_MARK, VI2_R1_MARK, 3839 VI2_R2_MARK, VI2_R3_MARK, 3840 VI2_R4_MARK, VI2_R5_MARK, 3841 VI2_R6_MARK, VI2_R7_MARK, 3842 }, 3843 }; 3844 static const unsigned int vin2_data18_pins[] = { 3845 /* B */ 3846 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3847 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3848 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3849 /* G */ 3850 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 3851 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3852 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3853 /* R */ 3854 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3855 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3856 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 3857 }; 3858 static const unsigned int vin2_data18_mux[] = { 3859 /* B */ 3860 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 3861 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 3862 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 3863 /* G */ 3864 VI2_G2_MARK, VI2_G3_MARK, 3865 VI2_G4_MARK, VI2_G5_MARK, 3866 VI2_G6_MARK, VI2_G7_MARK, 3867 /* R */ 3868 VI2_R2_MARK, VI2_R3_MARK, 3869 VI2_R4_MARK, VI2_R5_MARK, 3870 VI2_R6_MARK, VI2_R7_MARK, 3871 }; 3872 static const unsigned int vin2_sync_pins[] = { 3873 RCAR_GP_PIN(1, 16), /* HSYNC */ 3874 RCAR_GP_PIN(1, 21), /* VSYNC */ 3875 }; 3876 static const unsigned int vin2_sync_mux[] = { 3877 VI2_HSYNC_N_MARK, 3878 VI2_VSYNC_N_MARK, 3879 }; 3880 static const unsigned int vin2_field_pins[] = { 3881 RCAR_GP_PIN(1, 9), 3882 }; 3883 static const unsigned int vin2_field_mux[] = { 3884 VI2_FIELD_MARK, 3885 }; 3886 static const unsigned int vin2_clkenb_pins[] = { 3887 RCAR_GP_PIN(1, 8), 3888 }; 3889 static const unsigned int vin2_clkenb_mux[] = { 3890 VI2_CLKENB_MARK, 3891 }; 3892 static const unsigned int vin2_clk_pins[] = { 3893 RCAR_GP_PIN(1, 11), 3894 }; 3895 static const unsigned int vin2_clk_mux[] = { 3896 VI2_CLK_MARK, 3897 }; 3898 /* - VIN3 ----------------------------------------------------------------- */ 3899 static const unsigned int vin3_data8_pins[] = { 3900 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3901 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3902 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3903 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3904 }; 3905 static const unsigned int vin3_data8_mux[] = { 3906 VI3_DATA0_MARK, VI3_DATA1_MARK, 3907 VI3_DATA2_MARK, VI3_DATA3_MARK, 3908 VI3_DATA4_MARK, VI3_DATA5_MARK, 3909 VI3_DATA6_MARK, VI3_DATA7_MARK, 3910 }; 3911 static const unsigned int vin3_sync_pins[] = { 3912 RCAR_GP_PIN(1, 16), /* HSYNC */ 3913 RCAR_GP_PIN(1, 17), /* VSYNC */ 3914 }; 3915 static const unsigned int vin3_sync_mux[] = { 3916 VI3_HSYNC_N_MARK, 3917 VI3_VSYNC_N_MARK, 3918 }; 3919 static const unsigned int vin3_field_pins[] = { 3920 RCAR_GP_PIN(1, 15), 3921 }; 3922 static const unsigned int vin3_field_mux[] = { 3923 VI3_FIELD_MARK, 3924 }; 3925 static const unsigned int vin3_clkenb_pins[] = { 3926 RCAR_GP_PIN(1, 14), 3927 }; 3928 static const unsigned int vin3_clkenb_mux[] = { 3929 VI3_CLKENB_MARK, 3930 }; 3931 static const unsigned int vin3_clk_pins[] = { 3932 RCAR_GP_PIN(1, 23), 3933 }; 3934 static const unsigned int vin3_clk_mux[] = { 3935 VI3_CLK_MARK, 3936 }; 3937 3938 static const struct sh_pfc_pin_group pinmux_groups[] = { 3939 SH_PFC_PIN_GROUP(audio_clk_a), 3940 SH_PFC_PIN_GROUP(audio_clk_b), 3941 SH_PFC_PIN_GROUP(audio_clk_c), 3942 SH_PFC_PIN_GROUP(audio_clkout), 3943 SH_PFC_PIN_GROUP(audio_clkout_b), 3944 SH_PFC_PIN_GROUP(audio_clkout_c), 3945 SH_PFC_PIN_GROUP(audio_clkout_d), 3946 SH_PFC_PIN_GROUP(avb_link), 3947 SH_PFC_PIN_GROUP(avb_magic), 3948 SH_PFC_PIN_GROUP(avb_phy_int), 3949 SH_PFC_PIN_GROUP(avb_mdio), 3950 SH_PFC_PIN_GROUP(avb_mii), 3951 SH_PFC_PIN_GROUP(avb_gmii), 3952 SH_PFC_PIN_GROUP(du_rgb666), 3953 SH_PFC_PIN_GROUP(du_rgb888), 3954 SH_PFC_PIN_GROUP(du_clk_out_0), 3955 SH_PFC_PIN_GROUP(du_clk_out_1), 3956 SH_PFC_PIN_GROUP(du_sync_0), 3957 SH_PFC_PIN_GROUP(du_sync_1), 3958 SH_PFC_PIN_GROUP(du_cde), 3959 SH_PFC_PIN_GROUP(du0_clk_in), 3960 SH_PFC_PIN_GROUP(du1_clk_in), 3961 SH_PFC_PIN_GROUP(du2_clk_in), 3962 SH_PFC_PIN_GROUP(eth_link), 3963 SH_PFC_PIN_GROUP(eth_magic), 3964 SH_PFC_PIN_GROUP(eth_mdio), 3965 SH_PFC_PIN_GROUP(eth_rmii), 3966 SH_PFC_PIN_GROUP(hscif0_data), 3967 SH_PFC_PIN_GROUP(hscif0_clk), 3968 SH_PFC_PIN_GROUP(hscif0_ctrl), 3969 SH_PFC_PIN_GROUP(hscif0_data_b), 3970 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 3971 SH_PFC_PIN_GROUP(hscif0_data_c), 3972 SH_PFC_PIN_GROUP(hscif0_ctrl_c), 3973 SH_PFC_PIN_GROUP(hscif0_data_d), 3974 SH_PFC_PIN_GROUP(hscif0_ctrl_d), 3975 SH_PFC_PIN_GROUP(hscif0_data_e), 3976 SH_PFC_PIN_GROUP(hscif0_ctrl_e), 3977 SH_PFC_PIN_GROUP(hscif0_data_f), 3978 SH_PFC_PIN_GROUP(hscif0_ctrl_f), 3979 SH_PFC_PIN_GROUP(hscif1_data), 3980 SH_PFC_PIN_GROUP(hscif1_clk), 3981 SH_PFC_PIN_GROUP(hscif1_ctrl), 3982 SH_PFC_PIN_GROUP(hscif1_data_b), 3983 SH_PFC_PIN_GROUP(hscif1_clk_b), 3984 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3985 SH_PFC_PIN_GROUP(i2c0), 3986 SH_PFC_PIN_GROUP(i2c1), 3987 SH_PFC_PIN_GROUP(i2c1_b), 3988 SH_PFC_PIN_GROUP(i2c1_c), 3989 SH_PFC_PIN_GROUP(i2c2), 3990 SH_PFC_PIN_GROUP(i2c2_b), 3991 SH_PFC_PIN_GROUP(i2c2_c), 3992 SH_PFC_PIN_GROUP(i2c2_d), 3993 SH_PFC_PIN_GROUP(i2c2_e), 3994 SH_PFC_PIN_GROUP(i2c3), 3995 SH_PFC_PIN_GROUP(iic0), 3996 SH_PFC_PIN_GROUP(iic1), 3997 SH_PFC_PIN_GROUP(iic1_b), 3998 SH_PFC_PIN_GROUP(iic1_c), 3999 SH_PFC_PIN_GROUP(iic2), 4000 SH_PFC_PIN_GROUP(iic2_b), 4001 SH_PFC_PIN_GROUP(iic2_c), 4002 SH_PFC_PIN_GROUP(iic2_d), 4003 SH_PFC_PIN_GROUP(iic2_e), 4004 SH_PFC_PIN_GROUP(iic3), 4005 SH_PFC_PIN_GROUP(intc_irq0), 4006 SH_PFC_PIN_GROUP(intc_irq1), 4007 SH_PFC_PIN_GROUP(intc_irq2), 4008 SH_PFC_PIN_GROUP(intc_irq3), 4009 SH_PFC_PIN_GROUP(mlb_3pin), 4010 SH_PFC_PIN_GROUP(mmc0_data1), 4011 SH_PFC_PIN_GROUP(mmc0_data4), 4012 SH_PFC_PIN_GROUP(mmc0_data8), 4013 SH_PFC_PIN_GROUP(mmc0_ctrl), 4014 SH_PFC_PIN_GROUP(mmc1_data1), 4015 SH_PFC_PIN_GROUP(mmc1_data4), 4016 SH_PFC_PIN_GROUP(mmc1_data8), 4017 SH_PFC_PIN_GROUP(mmc1_ctrl), 4018 SH_PFC_PIN_GROUP(msiof0_clk), 4019 SH_PFC_PIN_GROUP(msiof0_sync), 4020 SH_PFC_PIN_GROUP(msiof0_ss1), 4021 SH_PFC_PIN_GROUP(msiof0_ss2), 4022 SH_PFC_PIN_GROUP(msiof0_rx), 4023 SH_PFC_PIN_GROUP(msiof0_tx), 4024 SH_PFC_PIN_GROUP(msiof0_clk_b), 4025 SH_PFC_PIN_GROUP(msiof0_ss1_b), 4026 SH_PFC_PIN_GROUP(msiof0_ss2_b), 4027 SH_PFC_PIN_GROUP(msiof0_rx_b), 4028 SH_PFC_PIN_GROUP(msiof0_tx_b), 4029 SH_PFC_PIN_GROUP(msiof1_clk), 4030 SH_PFC_PIN_GROUP(msiof1_sync), 4031 SH_PFC_PIN_GROUP(msiof1_ss1), 4032 SH_PFC_PIN_GROUP(msiof1_ss2), 4033 SH_PFC_PIN_GROUP(msiof1_rx), 4034 SH_PFC_PIN_GROUP(msiof1_tx), 4035 SH_PFC_PIN_GROUP(msiof1_clk_b), 4036 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4037 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4038 SH_PFC_PIN_GROUP(msiof1_rx_b), 4039 SH_PFC_PIN_GROUP(msiof1_tx_b), 4040 SH_PFC_PIN_GROUP(msiof2_clk), 4041 SH_PFC_PIN_GROUP(msiof2_sync), 4042 SH_PFC_PIN_GROUP(msiof2_ss1), 4043 SH_PFC_PIN_GROUP(msiof2_ss2), 4044 SH_PFC_PIN_GROUP(msiof2_rx), 4045 SH_PFC_PIN_GROUP(msiof2_tx), 4046 SH_PFC_PIN_GROUP(msiof3_clk), 4047 SH_PFC_PIN_GROUP(msiof3_sync), 4048 SH_PFC_PIN_GROUP(msiof3_ss1), 4049 SH_PFC_PIN_GROUP(msiof3_ss2), 4050 SH_PFC_PIN_GROUP(msiof3_rx), 4051 SH_PFC_PIN_GROUP(msiof3_tx), 4052 SH_PFC_PIN_GROUP(msiof3_clk_b), 4053 SH_PFC_PIN_GROUP(msiof3_sync_b), 4054 SH_PFC_PIN_GROUP(msiof3_rx_b), 4055 SH_PFC_PIN_GROUP(msiof3_tx_b), 4056 SH_PFC_PIN_GROUP(pwm0), 4057 SH_PFC_PIN_GROUP(pwm0_b), 4058 SH_PFC_PIN_GROUP(pwm1), 4059 SH_PFC_PIN_GROUP(pwm1_b), 4060 SH_PFC_PIN_GROUP(pwm2), 4061 SH_PFC_PIN_GROUP(pwm3), 4062 SH_PFC_PIN_GROUP(pwm4), 4063 SH_PFC_PIN_GROUP(pwm5), 4064 SH_PFC_PIN_GROUP(pwm6), 4065 SH_PFC_PIN_GROUP(qspi_ctrl), 4066 SH_PFC_PIN_GROUP(qspi_data2), 4067 SH_PFC_PIN_GROUP(qspi_data4), 4068 SH_PFC_PIN_GROUP(scif0_data), 4069 SH_PFC_PIN_GROUP(scif0_clk), 4070 SH_PFC_PIN_GROUP(scif0_ctrl), 4071 SH_PFC_PIN_GROUP(scif0_data_b), 4072 SH_PFC_PIN_GROUP(scif1_data), 4073 SH_PFC_PIN_GROUP(scif1_clk), 4074 SH_PFC_PIN_GROUP(scif1_ctrl), 4075 SH_PFC_PIN_GROUP(scif1_data_b), 4076 SH_PFC_PIN_GROUP(scif1_data_c), 4077 SH_PFC_PIN_GROUP(scif1_data_d), 4078 SH_PFC_PIN_GROUP(scif1_clk_d), 4079 SH_PFC_PIN_GROUP(scif1_data_e), 4080 SH_PFC_PIN_GROUP(scif1_clk_e), 4081 SH_PFC_PIN_GROUP(scif2_data), 4082 SH_PFC_PIN_GROUP(scif2_clk), 4083 SH_PFC_PIN_GROUP(scif2_data_b), 4084 SH_PFC_PIN_GROUP(scifa0_data), 4085 SH_PFC_PIN_GROUP(scifa0_clk), 4086 SH_PFC_PIN_GROUP(scifa0_ctrl), 4087 SH_PFC_PIN_GROUP(scifa0_data_b), 4088 SH_PFC_PIN_GROUP(scifa0_clk_b), 4089 SH_PFC_PIN_GROUP(scifa0_ctrl_b), 4090 SH_PFC_PIN_GROUP(scifa1_data), 4091 SH_PFC_PIN_GROUP(scifa1_clk), 4092 SH_PFC_PIN_GROUP(scifa1_ctrl), 4093 SH_PFC_PIN_GROUP(scifa1_data_b), 4094 SH_PFC_PIN_GROUP(scifa1_clk_b), 4095 SH_PFC_PIN_GROUP(scifa1_ctrl_b), 4096 SH_PFC_PIN_GROUP(scifa1_data_c), 4097 SH_PFC_PIN_GROUP(scifa1_clk_c), 4098 SH_PFC_PIN_GROUP(scifa1_ctrl_c), 4099 SH_PFC_PIN_GROUP(scifa1_data_d), 4100 SH_PFC_PIN_GROUP(scifa1_clk_d), 4101 SH_PFC_PIN_GROUP(scifa1_ctrl_d), 4102 SH_PFC_PIN_GROUP(scifa2_data), 4103 SH_PFC_PIN_GROUP(scifa2_clk), 4104 SH_PFC_PIN_GROUP(scifa2_ctrl), 4105 SH_PFC_PIN_GROUP(scifa2_data_b), 4106 SH_PFC_PIN_GROUP(scifa2_data_c), 4107 SH_PFC_PIN_GROUP(scifa2_clk_c), 4108 SH_PFC_PIN_GROUP(scifb0_data), 4109 SH_PFC_PIN_GROUP(scifb0_clk), 4110 SH_PFC_PIN_GROUP(scifb0_ctrl), 4111 SH_PFC_PIN_GROUP(scifb0_data_b), 4112 SH_PFC_PIN_GROUP(scifb0_clk_b), 4113 SH_PFC_PIN_GROUP(scifb0_ctrl_b), 4114 SH_PFC_PIN_GROUP(scifb0_data_c), 4115 SH_PFC_PIN_GROUP(scifb1_data), 4116 SH_PFC_PIN_GROUP(scifb1_clk), 4117 SH_PFC_PIN_GROUP(scifb1_ctrl), 4118 SH_PFC_PIN_GROUP(scifb1_data_b), 4119 SH_PFC_PIN_GROUP(scifb1_clk_b), 4120 SH_PFC_PIN_GROUP(scifb1_ctrl_b), 4121 SH_PFC_PIN_GROUP(scifb1_data_c), 4122 SH_PFC_PIN_GROUP(scifb1_data_d), 4123 SH_PFC_PIN_GROUP(scifb1_data_e), 4124 SH_PFC_PIN_GROUP(scifb1_clk_e), 4125 SH_PFC_PIN_GROUP(scifb1_data_f), 4126 SH_PFC_PIN_GROUP(scifb1_data_g), 4127 SH_PFC_PIN_GROUP(scifb1_clk_g), 4128 SH_PFC_PIN_GROUP(scifb2_data), 4129 SH_PFC_PIN_GROUP(scifb2_clk), 4130 SH_PFC_PIN_GROUP(scifb2_ctrl), 4131 SH_PFC_PIN_GROUP(scifb2_data_b), 4132 SH_PFC_PIN_GROUP(scifb2_clk_b), 4133 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 4134 SH_PFC_PIN_GROUP(scifb2_data_c), 4135 SH_PFC_PIN_GROUP(scif_clk), 4136 SH_PFC_PIN_GROUP(scif_clk_b), 4137 SH_PFC_PIN_GROUP(sdhi0_data1), 4138 SH_PFC_PIN_GROUP(sdhi0_data4), 4139 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4140 SH_PFC_PIN_GROUP(sdhi0_cd), 4141 SH_PFC_PIN_GROUP(sdhi0_wp), 4142 SH_PFC_PIN_GROUP(sdhi1_data1), 4143 SH_PFC_PIN_GROUP(sdhi1_data4), 4144 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4145 SH_PFC_PIN_GROUP(sdhi1_cd), 4146 SH_PFC_PIN_GROUP(sdhi1_wp), 4147 SH_PFC_PIN_GROUP(sdhi2_data1), 4148 SH_PFC_PIN_GROUP(sdhi2_data4), 4149 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4150 SH_PFC_PIN_GROUP(sdhi2_cd), 4151 SH_PFC_PIN_GROUP(sdhi2_wp), 4152 SH_PFC_PIN_GROUP(sdhi3_data1), 4153 SH_PFC_PIN_GROUP(sdhi3_data4), 4154 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4155 SH_PFC_PIN_GROUP(sdhi3_cd), 4156 SH_PFC_PIN_GROUP(sdhi3_wp), 4157 SH_PFC_PIN_GROUP(ssi0_data), 4158 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4159 SH_PFC_PIN_GROUP(ssi1_data), 4160 SH_PFC_PIN_GROUP(ssi1_ctrl), 4161 SH_PFC_PIN_GROUP(ssi2_data), 4162 SH_PFC_PIN_GROUP(ssi2_ctrl), 4163 SH_PFC_PIN_GROUP(ssi3_data), 4164 SH_PFC_PIN_GROUP(ssi34_ctrl), 4165 SH_PFC_PIN_GROUP(ssi4_data), 4166 SH_PFC_PIN_GROUP(ssi4_ctrl), 4167 SH_PFC_PIN_GROUP(ssi5), 4168 SH_PFC_PIN_GROUP(ssi5_b), 4169 SH_PFC_PIN_GROUP(ssi5_c), 4170 SH_PFC_PIN_GROUP(ssi6), 4171 SH_PFC_PIN_GROUP(ssi6_b), 4172 SH_PFC_PIN_GROUP(ssi7_data), 4173 SH_PFC_PIN_GROUP(ssi7_b_data), 4174 SH_PFC_PIN_GROUP(ssi7_c_data), 4175 SH_PFC_PIN_GROUP(ssi78_ctrl), 4176 SH_PFC_PIN_GROUP(ssi78_b_ctrl), 4177 SH_PFC_PIN_GROUP(ssi78_c_ctrl), 4178 SH_PFC_PIN_GROUP(ssi8_data), 4179 SH_PFC_PIN_GROUP(ssi8_b_data), 4180 SH_PFC_PIN_GROUP(ssi8_c_data), 4181 SH_PFC_PIN_GROUP(ssi9_data), 4182 SH_PFC_PIN_GROUP(ssi9_ctrl), 4183 SH_PFC_PIN_GROUP(tpu0_to0), 4184 SH_PFC_PIN_GROUP(tpu0_to1), 4185 SH_PFC_PIN_GROUP(tpu0_to2), 4186 SH_PFC_PIN_GROUP(tpu0_to3), 4187 SH_PFC_PIN_GROUP(usb0), 4188 SH_PFC_PIN_GROUP(usb0_ovc_vbus), 4189 SH_PFC_PIN_GROUP(usb1), 4190 SH_PFC_PIN_GROUP(usb2), 4191 VIN_DATA_PIN_GROUP(vin0_data, 24), 4192 VIN_DATA_PIN_GROUP(vin0_data, 20), 4193 SH_PFC_PIN_GROUP(vin0_data18), 4194 VIN_DATA_PIN_GROUP(vin0_data, 16), 4195 VIN_DATA_PIN_GROUP(vin0_data, 12), 4196 VIN_DATA_PIN_GROUP(vin0_data, 10), 4197 VIN_DATA_PIN_GROUP(vin0_data, 8), 4198 VIN_DATA_PIN_GROUP(vin0_data, 4), 4199 SH_PFC_PIN_GROUP(vin0_sync), 4200 SH_PFC_PIN_GROUP(vin0_field), 4201 SH_PFC_PIN_GROUP(vin0_clkenb), 4202 SH_PFC_PIN_GROUP(vin0_clk), 4203 VIN_DATA_PIN_GROUP(vin1_data, 24), 4204 VIN_DATA_PIN_GROUP(vin1_data, 20), 4205 SH_PFC_PIN_GROUP(vin1_data18), 4206 VIN_DATA_PIN_GROUP(vin1_data, 16), 4207 VIN_DATA_PIN_GROUP(vin1_data, 12), 4208 VIN_DATA_PIN_GROUP(vin1_data, 10), 4209 VIN_DATA_PIN_GROUP(vin1_data, 8), 4210 VIN_DATA_PIN_GROUP(vin1_data, 4), 4211 SH_PFC_PIN_GROUP(vin1_sync), 4212 SH_PFC_PIN_GROUP(vin1_field), 4213 SH_PFC_PIN_GROUP(vin1_clkenb), 4214 SH_PFC_PIN_GROUP(vin1_clk), 4215 VIN_DATA_PIN_GROUP(vin2_data, 24), 4216 SH_PFC_PIN_GROUP(vin2_data18), 4217 VIN_DATA_PIN_GROUP(vin2_data, 16), 4218 VIN_DATA_PIN_GROUP(vin2_data, 8), 4219 VIN_DATA_PIN_GROUP(vin2_data, 4), 4220 SH_PFC_PIN_GROUP(vin2_sync), 4221 SH_PFC_PIN_GROUP(vin2_field), 4222 SH_PFC_PIN_GROUP(vin2_clkenb), 4223 SH_PFC_PIN_GROUP(vin2_clk), 4224 SH_PFC_PIN_GROUP(vin3_data8), 4225 SH_PFC_PIN_GROUP(vin3_sync), 4226 SH_PFC_PIN_GROUP(vin3_field), 4227 SH_PFC_PIN_GROUP(vin3_clkenb), 4228 SH_PFC_PIN_GROUP(vin3_clk), 4229 }; 4230 4231 static const char * const audio_clk_groups[] = { 4232 "audio_clk_a", 4233 "audio_clk_b", 4234 "audio_clk_c", 4235 "audio_clkout", 4236 "audio_clkout_b", 4237 "audio_clkout_c", 4238 "audio_clkout_d", 4239 }; 4240 4241 static const char * const avb_groups[] = { 4242 "avb_link", 4243 "avb_magic", 4244 "avb_phy_int", 4245 "avb_mdio", 4246 "avb_mii", 4247 "avb_gmii", 4248 }; 4249 4250 static const char * const du_groups[] = { 4251 "du_rgb666", 4252 "du_rgb888", 4253 "du_clk_out_0", 4254 "du_clk_out_1", 4255 "du_sync_0", 4256 "du_sync_1", 4257 "du_cde", 4258 }; 4259 4260 static const char * const du0_groups[] = { 4261 "du0_clk_in", 4262 }; 4263 4264 static const char * const du1_groups[] = { 4265 "du1_clk_in", 4266 }; 4267 4268 static const char * const du2_groups[] = { 4269 "du2_clk_in", 4270 }; 4271 4272 static const char * const eth_groups[] = { 4273 "eth_link", 4274 "eth_magic", 4275 "eth_mdio", 4276 "eth_rmii", 4277 }; 4278 4279 static const char * const hscif0_groups[] = { 4280 "hscif0_data", 4281 "hscif0_clk", 4282 "hscif0_ctrl", 4283 "hscif0_data_b", 4284 "hscif0_ctrl_b", 4285 "hscif0_data_c", 4286 "hscif0_ctrl_c", 4287 "hscif0_data_d", 4288 "hscif0_ctrl_d", 4289 "hscif0_data_e", 4290 "hscif0_ctrl_e", 4291 "hscif0_data_f", 4292 "hscif0_ctrl_f", 4293 }; 4294 4295 static const char * const hscif1_groups[] = { 4296 "hscif1_data", 4297 "hscif1_clk", 4298 "hscif1_ctrl", 4299 "hscif1_data_b", 4300 "hscif1_clk_b", 4301 "hscif1_ctrl_b", 4302 }; 4303 4304 static const char * const i2c0_groups[] = { 4305 "i2c0", 4306 }; 4307 4308 static const char * const i2c1_groups[] = { 4309 "i2c1", 4310 "i2c1_b", 4311 "i2c1_c", 4312 }; 4313 4314 static const char * const i2c2_groups[] = { 4315 "i2c2", 4316 "i2c2_b", 4317 "i2c2_c", 4318 "i2c2_d", 4319 "i2c2_e", 4320 }; 4321 4322 static const char * const i2c3_groups[] = { 4323 "i2c3", 4324 }; 4325 4326 static const char * const iic0_groups[] = { 4327 "iic0", 4328 }; 4329 4330 static const char * const iic1_groups[] = { 4331 "iic1", 4332 "iic1_b", 4333 "iic1_c", 4334 }; 4335 4336 static const char * const iic2_groups[] = { 4337 "iic2", 4338 "iic2_b", 4339 "iic2_c", 4340 "iic2_d", 4341 "iic2_e", 4342 }; 4343 4344 static const char * const iic3_groups[] = { 4345 "iic3", 4346 }; 4347 4348 static const char * const intc_groups[] = { 4349 "intc_irq0", 4350 "intc_irq1", 4351 "intc_irq2", 4352 "intc_irq3", 4353 }; 4354 4355 static const char * const mlb_groups[] = { 4356 "mlb_3pin", 4357 }; 4358 4359 static const char * const mmc0_groups[] = { 4360 "mmc0_data1", 4361 "mmc0_data4", 4362 "mmc0_data8", 4363 "mmc0_ctrl", 4364 }; 4365 4366 static const char * const mmc1_groups[] = { 4367 "mmc1_data1", 4368 "mmc1_data4", 4369 "mmc1_data8", 4370 "mmc1_ctrl", 4371 }; 4372 4373 static const char * const msiof0_groups[] = { 4374 "msiof0_clk", 4375 "msiof0_sync", 4376 "msiof0_ss1", 4377 "msiof0_ss2", 4378 "msiof0_rx", 4379 "msiof0_tx", 4380 "msiof0_clk_b", 4381 "msiof0_ss1_b", 4382 "msiof0_ss2_b", 4383 "msiof0_rx_b", 4384 "msiof0_tx_b", 4385 }; 4386 4387 static const char * const msiof1_groups[] = { 4388 "msiof1_clk", 4389 "msiof1_sync", 4390 "msiof1_ss1", 4391 "msiof1_ss2", 4392 "msiof1_rx", 4393 "msiof1_tx", 4394 "msiof1_clk_b", 4395 "msiof1_ss1_b", 4396 "msiof1_ss2_b", 4397 "msiof1_rx_b", 4398 "msiof1_tx_b", 4399 }; 4400 4401 static const char * const msiof2_groups[] = { 4402 "msiof2_clk", 4403 "msiof2_sync", 4404 "msiof2_ss1", 4405 "msiof2_ss2", 4406 "msiof2_rx", 4407 "msiof2_tx", 4408 }; 4409 4410 static const char * const msiof3_groups[] = { 4411 "msiof3_clk", 4412 "msiof3_sync", 4413 "msiof3_ss1", 4414 "msiof3_ss2", 4415 "msiof3_rx", 4416 "msiof3_tx", 4417 "msiof3_clk_b", 4418 "msiof3_sync_b", 4419 "msiof3_rx_b", 4420 "msiof3_tx_b", 4421 }; 4422 4423 static const char * const pwm0_groups[] = { 4424 "pwm0", 4425 "pwm0_b", 4426 }; 4427 4428 static const char * const pwm1_groups[] = { 4429 "pwm1", 4430 "pwm1_b", 4431 }; 4432 4433 static const char * const pwm2_groups[] = { 4434 "pwm2", 4435 }; 4436 4437 static const char * const pwm3_groups[] = { 4438 "pwm3", 4439 }; 4440 4441 static const char * const pwm4_groups[] = { 4442 "pwm4", 4443 }; 4444 4445 static const char * const pwm5_groups[] = { 4446 "pwm5", 4447 }; 4448 4449 static const char * const pwm6_groups[] = { 4450 "pwm6", 4451 }; 4452 4453 static const char * const qspi_groups[] = { 4454 "qspi_ctrl", 4455 "qspi_data2", 4456 "qspi_data4", 4457 }; 4458 4459 static const char * const scif0_groups[] = { 4460 "scif0_data", 4461 "scif0_clk", 4462 "scif0_ctrl", 4463 "scif0_data_b", 4464 }; 4465 4466 static const char * const scif1_groups[] = { 4467 "scif1_data", 4468 "scif1_clk", 4469 "scif1_ctrl", 4470 "scif1_data_b", 4471 "scif1_data_c", 4472 "scif1_data_d", 4473 "scif1_clk_d", 4474 "scif1_data_e", 4475 "scif1_clk_e", 4476 }; 4477 4478 static const char * const scif2_groups[] = { 4479 "scif2_data", 4480 "scif2_clk", 4481 "scif2_data_b", 4482 }; 4483 4484 static const char * const scifa0_groups[] = { 4485 "scifa0_data", 4486 "scifa0_clk", 4487 "scifa0_ctrl", 4488 "scifa0_data_b", 4489 "scifa0_clk_b", 4490 "scifa0_ctrl_b", 4491 }; 4492 4493 static const char * const scifa1_groups[] = { 4494 "scifa1_data", 4495 "scifa1_clk", 4496 "scifa1_ctrl", 4497 "scifa1_data_b", 4498 "scifa1_clk_b", 4499 "scifa1_ctrl_b", 4500 "scifa1_data_c", 4501 "scifa1_clk_c", 4502 "scifa1_ctrl_c", 4503 "scifa1_data_d", 4504 "scifa1_clk_d", 4505 "scifa1_ctrl_d", 4506 }; 4507 4508 static const char * const scifa2_groups[] = { 4509 "scifa2_data", 4510 "scifa2_clk", 4511 "scifa2_ctrl", 4512 "scifa2_data_b", 4513 "scifa2_data_c", 4514 "scifa2_clk_c", 4515 }; 4516 4517 static const char * const scifb0_groups[] = { 4518 "scifb0_data", 4519 "scifb0_clk", 4520 "scifb0_ctrl", 4521 "scifb0_data_b", 4522 "scifb0_clk_b", 4523 "scifb0_ctrl_b", 4524 "scifb0_data_c", 4525 }; 4526 4527 static const char * const scifb1_groups[] = { 4528 "scifb1_data", 4529 "scifb1_clk", 4530 "scifb1_ctrl", 4531 "scifb1_data_b", 4532 "scifb1_clk_b", 4533 "scifb1_ctrl_b", 4534 "scifb1_data_c", 4535 "scifb1_data_d", 4536 "scifb1_data_e", 4537 "scifb1_clk_e", 4538 "scifb1_data_f", 4539 "scifb1_data_g", 4540 "scifb1_clk_g", 4541 }; 4542 4543 static const char * const scifb2_groups[] = { 4544 "scifb2_data", 4545 "scifb2_clk", 4546 "scifb2_ctrl", 4547 "scifb2_data_b", 4548 "scifb2_clk_b", 4549 "scifb2_ctrl_b", 4550 "scifb2_data_c", 4551 }; 4552 4553 static const char * const scif_clk_groups[] = { 4554 "scif_clk", 4555 "scif_clk_b", 4556 }; 4557 4558 static const char * const sdhi0_groups[] = { 4559 "sdhi0_data1", 4560 "sdhi0_data4", 4561 "sdhi0_ctrl", 4562 "sdhi0_cd", 4563 "sdhi0_wp", 4564 }; 4565 4566 static const char * const sdhi1_groups[] = { 4567 "sdhi1_data1", 4568 "sdhi1_data4", 4569 "sdhi1_ctrl", 4570 "sdhi1_cd", 4571 "sdhi1_wp", 4572 }; 4573 4574 static const char * const sdhi2_groups[] = { 4575 "sdhi2_data1", 4576 "sdhi2_data4", 4577 "sdhi2_ctrl", 4578 "sdhi2_cd", 4579 "sdhi2_wp", 4580 }; 4581 4582 static const char * const sdhi3_groups[] = { 4583 "sdhi3_data1", 4584 "sdhi3_data4", 4585 "sdhi3_ctrl", 4586 "sdhi3_cd", 4587 "sdhi3_wp", 4588 }; 4589 4590 static const char * const ssi_groups[] = { 4591 "ssi0_data", 4592 "ssi0129_ctrl", 4593 "ssi1_data", 4594 "ssi1_ctrl", 4595 "ssi2_data", 4596 "ssi2_ctrl", 4597 "ssi3_data", 4598 "ssi34_ctrl", 4599 "ssi4_data", 4600 "ssi4_ctrl", 4601 "ssi5", 4602 "ssi5_b", 4603 "ssi5_c", 4604 "ssi6", 4605 "ssi6_b", 4606 "ssi7_data", 4607 "ssi7_b_data", 4608 "ssi7_c_data", 4609 "ssi78_ctrl", 4610 "ssi78_b_ctrl", 4611 "ssi78_c_ctrl", 4612 "ssi8_data", 4613 "ssi8_b_data", 4614 "ssi8_c_data", 4615 "ssi9_data", 4616 "ssi9_ctrl", 4617 }; 4618 4619 static const char * const tpu0_groups[] = { 4620 "tpu0_to0", 4621 "tpu0_to1", 4622 "tpu0_to2", 4623 "tpu0_to3", 4624 }; 4625 4626 static const char * const usb0_groups[] = { 4627 "usb0", 4628 "usb0_ovc_vbus", 4629 }; 4630 4631 static const char * const usb1_groups[] = { 4632 "usb1", 4633 }; 4634 4635 static const char * const usb2_groups[] = { 4636 "usb2", 4637 }; 4638 4639 static const char * const vin0_groups[] = { 4640 "vin0_data24", 4641 "vin0_data20", 4642 "vin0_data18", 4643 "vin0_data16", 4644 "vin0_data12", 4645 "vin0_data10", 4646 "vin0_data8", 4647 "vin0_data4", 4648 "vin0_sync", 4649 "vin0_field", 4650 "vin0_clkenb", 4651 "vin0_clk", 4652 }; 4653 4654 static const char * const vin1_groups[] = { 4655 "vin1_data24", 4656 "vin1_data20", 4657 "vin1_data18", 4658 "vin1_data16", 4659 "vin1_data12", 4660 "vin1_data10", 4661 "vin1_data8", 4662 "vin1_data4", 4663 "vin1_sync", 4664 "vin1_field", 4665 "vin1_clkenb", 4666 "vin1_clk", 4667 }; 4668 4669 static const char * const vin2_groups[] = { 4670 "vin2_data24", 4671 "vin2_data18", 4672 "vin2_data16", 4673 "vin2_data8", 4674 "vin2_data4", 4675 "vin2_sync", 4676 "vin2_field", 4677 "vin2_clkenb", 4678 "vin2_clk", 4679 }; 4680 4681 static const char * const vin3_groups[] = { 4682 "vin3_data8", 4683 "vin3_sync", 4684 "vin3_field", 4685 "vin3_clkenb", 4686 "vin3_clk", 4687 }; 4688 4689 static const struct sh_pfc_function pinmux_functions[] = { 4690 SH_PFC_FUNCTION(audio_clk), 4691 SH_PFC_FUNCTION(avb), 4692 SH_PFC_FUNCTION(du), 4693 SH_PFC_FUNCTION(du0), 4694 SH_PFC_FUNCTION(du1), 4695 SH_PFC_FUNCTION(du2), 4696 SH_PFC_FUNCTION(eth), 4697 SH_PFC_FUNCTION(hscif0), 4698 SH_PFC_FUNCTION(hscif1), 4699 SH_PFC_FUNCTION(i2c0), 4700 SH_PFC_FUNCTION(i2c1), 4701 SH_PFC_FUNCTION(i2c2), 4702 SH_PFC_FUNCTION(i2c3), 4703 SH_PFC_FUNCTION(iic0), 4704 SH_PFC_FUNCTION(iic1), 4705 SH_PFC_FUNCTION(iic2), 4706 SH_PFC_FUNCTION(iic3), 4707 SH_PFC_FUNCTION(intc), 4708 SH_PFC_FUNCTION(mlb), 4709 SH_PFC_FUNCTION(mmc0), 4710 SH_PFC_FUNCTION(mmc1), 4711 SH_PFC_FUNCTION(msiof0), 4712 SH_PFC_FUNCTION(msiof1), 4713 SH_PFC_FUNCTION(msiof2), 4714 SH_PFC_FUNCTION(msiof3), 4715 SH_PFC_FUNCTION(pwm0), 4716 SH_PFC_FUNCTION(pwm1), 4717 SH_PFC_FUNCTION(pwm2), 4718 SH_PFC_FUNCTION(pwm3), 4719 SH_PFC_FUNCTION(pwm4), 4720 SH_PFC_FUNCTION(pwm5), 4721 SH_PFC_FUNCTION(pwm6), 4722 SH_PFC_FUNCTION(qspi), 4723 SH_PFC_FUNCTION(scif0), 4724 SH_PFC_FUNCTION(scif1), 4725 SH_PFC_FUNCTION(scif2), 4726 SH_PFC_FUNCTION(scifa0), 4727 SH_PFC_FUNCTION(scifa1), 4728 SH_PFC_FUNCTION(scifa2), 4729 SH_PFC_FUNCTION(scifb0), 4730 SH_PFC_FUNCTION(scifb1), 4731 SH_PFC_FUNCTION(scifb2), 4732 SH_PFC_FUNCTION(scif_clk), 4733 SH_PFC_FUNCTION(sdhi0), 4734 SH_PFC_FUNCTION(sdhi1), 4735 SH_PFC_FUNCTION(sdhi2), 4736 SH_PFC_FUNCTION(sdhi3), 4737 SH_PFC_FUNCTION(ssi), 4738 SH_PFC_FUNCTION(tpu0), 4739 SH_PFC_FUNCTION(usb0), 4740 SH_PFC_FUNCTION(usb1), 4741 SH_PFC_FUNCTION(usb2), 4742 SH_PFC_FUNCTION(vin0), 4743 SH_PFC_FUNCTION(vin1), 4744 SH_PFC_FUNCTION(vin2), 4745 SH_PFC_FUNCTION(vin3), 4746 }; 4747 4748 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4749 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 4750 GP_0_31_FN, FN_IP3_17_15, 4751 GP_0_30_FN, FN_IP3_14_12, 4752 GP_0_29_FN, FN_IP3_11_8, 4753 GP_0_28_FN, FN_IP3_7_4, 4754 GP_0_27_FN, FN_IP3_3_0, 4755 GP_0_26_FN, FN_IP2_28_26, 4756 GP_0_25_FN, FN_IP2_25_22, 4757 GP_0_24_FN, FN_IP2_21_18, 4758 GP_0_23_FN, FN_IP2_17_15, 4759 GP_0_22_FN, FN_IP2_14_12, 4760 GP_0_21_FN, FN_IP2_11_9, 4761 GP_0_20_FN, FN_IP2_8_6, 4762 GP_0_19_FN, FN_IP2_5_3, 4763 GP_0_18_FN, FN_IP2_2_0, 4764 GP_0_17_FN, FN_IP1_29_28, 4765 GP_0_16_FN, FN_IP1_27_26, 4766 GP_0_15_FN, FN_IP1_25_22, 4767 GP_0_14_FN, FN_IP1_21_18, 4768 GP_0_13_FN, FN_IP1_17_15, 4769 GP_0_12_FN, FN_IP1_14_12, 4770 GP_0_11_FN, FN_IP1_11_8, 4771 GP_0_10_FN, FN_IP1_7_4, 4772 GP_0_9_FN, FN_IP1_3_0, 4773 GP_0_8_FN, FN_IP0_30_27, 4774 GP_0_7_FN, FN_IP0_26_23, 4775 GP_0_6_FN, FN_IP0_22_20, 4776 GP_0_5_FN, FN_IP0_19_16, 4777 GP_0_4_FN, FN_IP0_15_12, 4778 GP_0_3_FN, FN_IP0_11_9, 4779 GP_0_2_FN, FN_IP0_8_6, 4780 GP_0_1_FN, FN_IP0_5_3, 4781 GP_0_0_FN, FN_IP0_2_0 } 4782 }, 4783 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 4784 0, 0, 4785 0, 0, 4786 GP_1_29_FN, FN_IP6_13_11, 4787 GP_1_28_FN, FN_IP6_10_9, 4788 GP_1_27_FN, FN_IP6_8_6, 4789 GP_1_26_FN, FN_IP6_5_3, 4790 GP_1_25_FN, FN_IP6_2_0, 4791 GP_1_24_FN, FN_IP5_29_27, 4792 GP_1_23_FN, FN_IP5_26_24, 4793 GP_1_22_FN, FN_IP5_23_21, 4794 GP_1_21_FN, FN_IP5_20_18, 4795 GP_1_20_FN, FN_IP5_17_15, 4796 GP_1_19_FN, FN_IP5_14_13, 4797 GP_1_18_FN, FN_IP5_12_10, 4798 GP_1_17_FN, FN_IP5_9_6, 4799 GP_1_16_FN, FN_IP5_5_3, 4800 GP_1_15_FN, FN_IP5_2_0, 4801 GP_1_14_FN, FN_IP4_29_27, 4802 GP_1_13_FN, FN_IP4_26_24, 4803 GP_1_12_FN, FN_IP4_23_21, 4804 GP_1_11_FN, FN_IP4_20_18, 4805 GP_1_10_FN, FN_IP4_17_15, 4806 GP_1_9_FN, FN_IP4_14_12, 4807 GP_1_8_FN, FN_IP4_11_9, 4808 GP_1_7_FN, FN_IP4_8_6, 4809 GP_1_6_FN, FN_IP4_5_3, 4810 GP_1_5_FN, FN_IP4_2_0, 4811 GP_1_4_FN, FN_IP3_31_29, 4812 GP_1_3_FN, FN_IP3_28_26, 4813 GP_1_2_FN, FN_IP3_25_23, 4814 GP_1_1_FN, FN_IP3_22_20, 4815 GP_1_0_FN, FN_IP3_19_18, } 4816 }, 4817 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 4818 0, 0, 4819 0, 0, 4820 GP_2_29_FN, FN_IP7_15_13, 4821 GP_2_28_FN, FN_IP7_12_10, 4822 GP_2_27_FN, FN_IP7_9_8, 4823 GP_2_26_FN, FN_IP7_7_6, 4824 GP_2_25_FN, FN_IP7_5_3, 4825 GP_2_24_FN, FN_IP7_2_0, 4826 GP_2_23_FN, FN_IP6_31_29, 4827 GP_2_22_FN, FN_IP6_28_26, 4828 GP_2_21_FN, FN_IP6_25_23, 4829 GP_2_20_FN, FN_IP6_22_20, 4830 GP_2_19_FN, FN_IP6_19_17, 4831 GP_2_18_FN, FN_IP6_16_14, 4832 GP_2_17_FN, FN_VI1_DATA7_VI1_B7, 4833 GP_2_16_FN, FN_IP8_27, 4834 GP_2_15_FN, FN_IP8_26, 4835 GP_2_14_FN, FN_IP8_25_24, 4836 GP_2_13_FN, FN_IP8_23_22, 4837 GP_2_12_FN, FN_IP8_21_20, 4838 GP_2_11_FN, FN_IP8_19_18, 4839 GP_2_10_FN, FN_IP8_17_16, 4840 GP_2_9_FN, FN_IP8_15_14, 4841 GP_2_8_FN, FN_IP8_13_12, 4842 GP_2_7_FN, FN_IP8_11_10, 4843 GP_2_6_FN, FN_IP8_9_8, 4844 GP_2_5_FN, FN_IP8_7_6, 4845 GP_2_4_FN, FN_IP8_5_4, 4846 GP_2_3_FN, FN_IP8_3_2, 4847 GP_2_2_FN, FN_IP8_1_0, 4848 GP_2_1_FN, FN_IP7_30_29, 4849 GP_2_0_FN, FN_IP7_28_27 } 4850 }, 4851 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 4852 GP_3_31_FN, FN_IP11_21_18, 4853 GP_3_30_FN, FN_IP11_17_15, 4854 GP_3_29_FN, FN_IP11_14_13, 4855 GP_3_28_FN, FN_IP11_12_11, 4856 GP_3_27_FN, FN_IP11_10_9, 4857 GP_3_26_FN, FN_IP11_8_7, 4858 GP_3_25_FN, FN_IP11_6_5, 4859 GP_3_24_FN, FN_IP11_4, 4860 GP_3_23_FN, FN_IP11_3_0, 4861 GP_3_22_FN, FN_IP10_29_26, 4862 GP_3_21_FN, FN_IP10_25_23, 4863 GP_3_20_FN, FN_IP10_22_19, 4864 GP_3_19_FN, FN_IP10_18_15, 4865 GP_3_18_FN, FN_IP10_14_11, 4866 GP_3_17_FN, FN_IP10_10_7, 4867 GP_3_16_FN, FN_IP10_6_4, 4868 GP_3_15_FN, FN_IP10_3_0, 4869 GP_3_14_FN, FN_IP9_31_28, 4870 GP_3_13_FN, FN_IP9_27_26, 4871 GP_3_12_FN, FN_IP9_25_24, 4872 GP_3_11_FN, FN_IP9_23_22, 4873 GP_3_10_FN, FN_IP9_21_20, 4874 GP_3_9_FN, FN_IP9_19_18, 4875 GP_3_8_FN, FN_IP9_17_16, 4876 GP_3_7_FN, FN_IP9_15_12, 4877 GP_3_6_FN, FN_IP9_11_8, 4878 GP_3_5_FN, FN_IP9_7_6, 4879 GP_3_4_FN, FN_IP9_5_4, 4880 GP_3_3_FN, FN_IP9_3_2, 4881 GP_3_2_FN, FN_IP9_1_0, 4882 GP_3_1_FN, FN_IP8_30_29, 4883 GP_3_0_FN, FN_IP8_28 } 4884 }, 4885 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 4886 GP_4_31_FN, FN_IP14_18_16, 4887 GP_4_30_FN, FN_IP14_15_12, 4888 GP_4_29_FN, FN_IP14_11_9, 4889 GP_4_28_FN, FN_IP14_8_6, 4890 GP_4_27_FN, FN_IP14_5_3, 4891 GP_4_26_FN, FN_IP14_2_0, 4892 GP_4_25_FN, FN_IP13_30_29, 4893 GP_4_24_FN, FN_IP13_28_26, 4894 GP_4_23_FN, FN_IP13_25_23, 4895 GP_4_22_FN, FN_IP13_22_19, 4896 GP_4_21_FN, FN_IP13_18_16, 4897 GP_4_20_FN, FN_IP13_15_13, 4898 GP_4_19_FN, FN_IP13_12_10, 4899 GP_4_18_FN, FN_IP13_9_7, 4900 GP_4_17_FN, FN_IP13_6_3, 4901 GP_4_16_FN, FN_IP13_2_0, 4902 GP_4_15_FN, FN_IP12_30_28, 4903 GP_4_14_FN, FN_IP12_27_25, 4904 GP_4_13_FN, FN_IP12_24_23, 4905 GP_4_12_FN, FN_IP12_22_20, 4906 GP_4_11_FN, FN_IP12_19_17, 4907 GP_4_10_FN, FN_IP12_16_14, 4908 GP_4_9_FN, FN_IP12_13_11, 4909 GP_4_8_FN, FN_IP12_10_8, 4910 GP_4_7_FN, FN_IP12_7_6, 4911 GP_4_6_FN, FN_IP12_5_4, 4912 GP_4_5_FN, FN_IP12_3_2, 4913 GP_4_4_FN, FN_IP12_1_0, 4914 GP_4_3_FN, FN_IP11_31_30, 4915 GP_4_2_FN, FN_IP11_29_27, 4916 GP_4_1_FN, FN_IP11_26_24, 4917 GP_4_0_FN, FN_IP11_23_22 } 4918 }, 4919 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 4920 GP_5_31_FN, FN_IP7_24_22, 4921 GP_5_30_FN, FN_IP7_21_19, 4922 GP_5_29_FN, FN_IP7_18_16, 4923 GP_5_28_FN, FN_DU_DOTCLKIN2, 4924 GP_5_27_FN, FN_IP7_26_25, 4925 GP_5_26_FN, FN_DU_DOTCLKIN0, 4926 GP_5_25_FN, FN_AVS2, 4927 GP_5_24_FN, FN_AVS1, 4928 GP_5_23_FN, FN_USB2_OVC, 4929 GP_5_22_FN, FN_USB2_PWEN, 4930 GP_5_21_FN, FN_IP16_7, 4931 GP_5_20_FN, FN_IP16_6, 4932 GP_5_19_FN, FN_USB0_OVC_VBUS, 4933 GP_5_18_FN, FN_USB0_PWEN, 4934 GP_5_17_FN, FN_IP16_5_3, 4935 GP_5_16_FN, FN_IP16_2_0, 4936 GP_5_15_FN, FN_IP15_29_28, 4937 GP_5_14_FN, FN_IP15_27_26, 4938 GP_5_13_FN, FN_IP15_25_23, 4939 GP_5_12_FN, FN_IP15_22_20, 4940 GP_5_11_FN, FN_IP15_19_18, 4941 GP_5_10_FN, FN_IP15_17_16, 4942 GP_5_9_FN, FN_IP15_15_14, 4943 GP_5_8_FN, FN_IP15_13_12, 4944 GP_5_7_FN, FN_IP15_11_9, 4945 GP_5_6_FN, FN_IP15_8_6, 4946 GP_5_5_FN, FN_IP15_5_3, 4947 GP_5_4_FN, FN_IP15_2_0, 4948 GP_5_3_FN, FN_IP14_30_28, 4949 GP_5_2_FN, FN_IP14_27_25, 4950 GP_5_1_FN, FN_IP14_24_22, 4951 GP_5_0_FN, FN_IP14_21_19 } 4952 }, 4953 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 4954 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { 4955 /* IP0_31 [1] */ 4956 0, 0, 4957 /* IP0_30_27 [4] */ 4958 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, 4959 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 4960 0, 0, 0, 0, 0, 0, 0, 0, 0, 4961 /* IP0_26_23 [4] */ 4962 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 4963 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, 4964 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0, 4965 /* IP0_22_20 [3] */ 4966 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 4967 FN_I2C2_SCL_C, 0, 0, 4968 /* IP0_19_16 [4] */ 4969 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 4970 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, 4971 0, 0, 0, 0, 0, 0, 0, 0, 0, 4972 /* IP0_15_12 [4] */ 4973 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 4974 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, 4975 0, 0, 0, 0, 0, 0, 0, 0, 0, 4976 /* IP0_11_9 [3] */ 4977 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, 4978 0, 0, 0, 4979 /* IP0_8_6 [3] */ 4980 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, 4981 0, 0, 0, 4982 /* IP0_5_3 [3] */ 4983 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, 4984 0, 0, 0, 4985 /* IP0_2_0 [3] */ 4986 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 4987 0, 0, 0, } 4988 }, 4989 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 4990 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { 4991 /* IP1_31_30 [2] */ 4992 0, 0, 0, 0, 4993 /* IP1_29_28 [2] */ 4994 FN_A1, FN_PWM4, 0, 0, 4995 /* IP1_27_26 [2] */ 4996 FN_A0, FN_PWM3, 0, 0, 4997 /* IP1_25_22 [4] */ 4998 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 4999 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 5000 0, 0, 0, 0, 0, 0, 0, 0, 0, 5001 /* IP1_21_18 [4] */ 5002 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 5003 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 5004 0, 0, 0, 0, 0, 0, 0, 0, 0, 5005 /* IP1_17_15 [3] */ 5006 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 5007 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, 5008 0, 0, 0, 5009 /* IP1_14_12 [3] */ 5010 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 5011 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 5012 0, 0, 5013 /* IP1_11_8 [4] */ 5014 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, 5015 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 5016 0, 0, 0, 0, 0, 0, 0, 0, 0, 5017 /* IP1_7_4 [4] */ 5018 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, 5019 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, 5020 0, 0, 0, 0, 0, 0, 0, 0, 0, 5021 /* IP1_3_0 [4] */ 5022 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, 5023 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, 5024 0, 0, 0, 0, 0, 0, 0, 0, 0, } 5025 }, 5026 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5027 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { 5028 /* IP2_31_29 [3] */ 5029 0, 0, 0, 0, 0, 0, 0, 0, 5030 /* IP2_28_26 [3] */ 5031 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 5032 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, 5033 /* IP2_25_22 [4] */ 5034 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 5035 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 5036 0, 0, 0, 0, 0, 0, 0, 0, 5037 /* IP2_21_18 [4] */ 5038 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 5039 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 5040 0, 0, 0, 0, 0, 0, 0, 0, 5041 /* IP2_17_15 [3] */ 5042 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 5043 0, 0, 0, 0, 5044 /* IP2_14_12 [3] */ 5045 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, 5046 /* IP2_11_9 [3] */ 5047 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, 5048 /* IP2_8_6 [3] */ 5049 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, 5050 /* IP2_5_3 [3] */ 5051 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, 5052 /* IP2_2_0 [3] */ 5053 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } 5054 }, 5055 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5056 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { 5057 /* IP3_31_29 [3] */ 5058 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 5059 0, 0, 0, 5060 /* IP3_28_26 [3] */ 5061 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, 5062 0, 0, 0, 0, 5063 /* IP3_25_23 [3] */ 5064 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, 5065 /* IP3_22_20 [3] */ 5066 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, 5067 /* IP3_19_18 [2] */ 5068 FN_A16, FN_ATAWR1_N, 0, 0, 5069 /* IP3_17_15 [3] */ 5070 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, 5071 0, 0, 0, 0, 5072 /* IP3_14_12 [3] */ 5073 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, 5074 0, 0, 0, 0, 5075 /* IP3_11_8 [4] */ 5076 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 5077 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 5078 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, 5079 /* IP3_7_4 [4] */ 5080 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 5081 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 5082 0, 0, 0, 0, 0, 0, 0, 0, 0, 5083 /* IP3_3_0 [4] */ 5084 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 5085 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, 5086 0, 0, 0, 0, 0, 0, 0, 0, } 5087 }, 5088 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5089 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 5090 /* IP4_31_30 [2] */ 5091 0, 0, 0, 0, 5092 /* IP4_29_27 [3] */ 5093 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 5094 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, 5095 /* IP4_26_24 [3] */ 5096 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, 5097 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, 5098 /* IP4_23_21 [3] */ 5099 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, 5100 FN_HTX0_B, FN_MSIOF0_SS1_B, 0, 5101 /* IP4_20_18 [3] */ 5102 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 5103 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, 5104 /* IP4_17_15 [3] */ 5105 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 5106 0, 0, 0, 5107 /* IP4_14_12 [3] */ 5108 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, 5109 FN_VI2_FIELD_B, 0, 0, 5110 /* IP4_11_9 [3] */ 5111 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 5112 FN_VI2_CLKENB_B, 0, 0, 5113 /* IP4_8_6 [3] */ 5114 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, 5115 /* IP4_5_3 [3] */ 5116 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, 5117 /* IP4_2_0 [3] */ 5118 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, 5119 } 5120 }, 5121 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5122 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { 5123 /* IP5_31_30 [2] */ 5124 0, 0, 0, 0, 5125 /* IP5_29_27 [3] */ 5126 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, 5127 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, 5128 /* IP5_26_24 [3] */ 5129 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 5130 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 5131 FN_MSIOF0_SCK_B, 0, 5132 /* IP5_23_21 [3] */ 5133 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 5134 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, 5135 /* IP5_20_18 [3] */ 5136 FN_WE0_N, FN_IECLK, FN_CAN_CLK, 5137 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, 5138 /* IP5_17_15 [3] */ 5139 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 5140 FN_INTC_IRQ4_N, 0, 0, 5141 /* IP5_14_13 [2] */ 5142 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, 5143 /* IP5_12_10 [3] */ 5144 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, 5145 0, 0, 5146 /* IP5_9_6 [4] */ 5147 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, 5148 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 5149 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, 5150 /* IP5_5_3 [3] */ 5151 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 5152 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 5153 FN_INTC_EN0_N, FN_I2C1_SCL, 5154 /* IP5_2_0 [3] */ 5155 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 5156 FN_VI2_R3, 0, 0, } 5157 }, 5158 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5159 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { 5160 /* IP6_31_29 [3] */ 5161 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, 5162 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, 5163 /* IP6_28_26 [3] */ 5164 FN_ETH_LINK, 0, FN_HTX0_E, 5165 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, 5166 /* IP6_25_23 [3] */ 5167 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, 5168 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, 5169 /* IP6_22_20 [3] */ 5170 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, 5171 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, 5172 /* IP6_19_17 [3] */ 5173 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, 5174 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, 5175 /* IP6_16_14 [3] */ 5176 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, 5177 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 5178 FN_I2C2_SCL_E, 0, 5179 /* IP6_13_11 [3] */ 5180 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 5181 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, 5182 /* IP6_10_9 [2] */ 5183 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, 5184 /* IP6_8_6 [3] */ 5185 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, 5186 FN_SSI_SDATA8_C, 0, 0, 0, 5187 /* IP6_5_3 [3] */ 5188 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 5189 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, 5190 /* IP6_2_0 [3] */ 5191 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 5192 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } 5193 }, 5194 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 5195 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { 5196 /* IP7_31 [1] */ 5197 0, 0, 5198 /* IP7_30_29 [2] */ 5199 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, 5200 /* IP7_28_27 [2] */ 5201 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, 5202 /* IP7_26_25 [2] */ 5203 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, 5204 /* IP7_24_22 [3] */ 5205 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, 5206 0, 0, 0, 5207 /* IP7_21_19 [3] */ 5208 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, 5209 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, 5210 /* IP7_18_16 [3] */ 5211 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 5212 FN_GLO_SS_C, 0, 0, 0, 5213 /* IP7_15_13 [3] */ 5214 FN_ETH_MDC, 0, FN_STP_ISD_1_B, 5215 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, 5216 /* IP7_12_10 [3] */ 5217 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, 5218 FN_GLO_SCLK_C, 0, 0, 0, 5219 /* IP7_9_8 [2] */ 5220 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, 5221 /* IP7_7_6 [2] */ 5222 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, 5223 /* IP7_5_3 [3] */ 5224 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, 5225 /* IP7_2_0 [3] */ 5226 FN_ETH_MDIO, 0, FN_HRTS0_N_E, 5227 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } 5228 }, 5229 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 5230 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 5231 2, 2, 2, 2, 2, 2, 2) { 5232 /* IP8_31 [1] */ 5233 0, 0, 5234 /* IP8_30_29 [2] */ 5235 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, 5236 /* IP8_28 [1] */ 5237 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, 5238 /* IP8_27 [1] */ 5239 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 5240 /* IP8_26 [1] */ 5241 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, 5242 /* IP8_25_24 [2] */ 5243 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 5244 FN_AVB_MAGIC, 0, 5245 /* IP8_23_22 [2] */ 5246 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, 5247 /* IP8_21_20 [2] */ 5248 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, 5249 /* IP8_19_18 [2] */ 5250 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, 5251 /* IP8_17_16 [2] */ 5252 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, 5253 /* IP8_15_14 [2] */ 5254 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, 5255 /* IP8_13_12 [2] */ 5256 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, 5257 /* IP8_11_10 [2] */ 5258 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, 5259 /* IP8_9_8 [2] */ 5260 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, 5261 /* IP8_7_6 [2] */ 5262 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, 5263 /* IP8_5_4 [2] */ 5264 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, 5265 /* IP8_3_2 [2] */ 5266 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, 5267 /* IP8_1_0 [2] */ 5268 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } 5269 }, 5270 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 5271 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { 5272 /* IP9_31_28 [4] */ 5273 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, 5274 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, 5275 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, 5276 /* IP9_27_26 [2] */ 5277 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, 5278 /* IP9_25_24 [2] */ 5279 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, 5280 /* IP9_23_22 [2] */ 5281 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, 5282 /* IP9_21_20 [2] */ 5283 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, 5284 /* IP9_19_18 [2] */ 5285 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, 5286 /* IP9_17_16 [2] */ 5287 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, 5288 /* IP9_15_12 [4] */ 5289 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 5290 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 5291 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, 5292 /* IP9_11_8 [4] */ 5293 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 5294 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 5295 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, 5296 /* IP9_7_6 [2] */ 5297 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, 5298 /* IP9_5_4 [2] */ 5299 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, 5300 /* IP9_3_2 [2] */ 5301 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, 5302 /* IP9_1_0 [2] */ 5303 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } 5304 }, 5305 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 5306 2, 4, 3, 4, 4, 4, 4, 3, 4) { 5307 /* IP10_31_30 [2] */ 5308 0, 0, 0, 0, 5309 /* IP10_29_26 [4] */ 5310 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 5311 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 5312 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, 5313 /* IP10_25_23 [3] */ 5314 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 5315 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, 5316 /* IP10_22_19 [4] */ 5317 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0, 5318 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 5319 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, 5320 /* IP10_18_15 [4] */ 5321 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0, 5322 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 5323 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 5324 0, 0, 0, 0, 0, 0, 5325 /* IP10_14_11 [4] */ 5326 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 5327 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 5328 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 5329 0, 0, 0, 0, 0, 0, 0, 5330 /* IP10_10_7 [4] */ 5331 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 5332 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 5333 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 5334 0, 0, 0, 0, 0, 0, 0, 5335 /* IP10_6_4 [3] */ 5336 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 5337 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 5338 FN_VI3_DATA0_B, 0, 5339 /* IP10_3_0 [4] */ 5340 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 5341 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 5342 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } 5343 }, 5344 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 5345 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { 5346 /* IP11_31_30 [2] */ 5347 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, 5348 /* IP11_29_27 [3] */ 5349 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 5350 0, 0, 0, 5351 /* IP11_26_24 [3] */ 5352 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, 5353 0, 0, 0, 5354 /* IP11_23_22 [2] */ 5355 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, 5356 /* IP11_21_18 [4] */ 5357 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 5358 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0, 5359 /* IP11_17_15 [3] */ 5360 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 5361 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, 5362 /* IP11_14_13 [2] */ 5363 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, 5364 /* IP11_12_11 [2] */ 5365 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, 5366 /* IP11_10_9 [2] */ 5367 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, 5368 /* IP11_8_7 [2] */ 5369 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, 5370 /* IP11_6_5 [2] */ 5371 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, 5372 /* IP11_4 [1] */ 5373 FN_SD3_CLK, FN_MMC1_CLK, 5374 /* IP11_3_0 [4] */ 5375 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 5376 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 5377 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } 5378 }, 5379 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 5380 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { 5381 /* IP12_31 [1] */ 5382 0, 0, 5383 /* IP12_30_28 [3] */ 5384 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, 5385 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 5386 FN_CAN_DEBUGOUT4, 0, 0, 5387 /* IP12_27_25 [3] */ 5388 FN_SSI_SCK5, FN_SCIFB1_SCK, 5389 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 5390 FN_CAN_DEBUGOUT3, 0, 0, 5391 /* IP12_24_23 [2] */ 5392 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 5393 FN_CAN_DEBUGOUT2, 5394 /* IP12_22_20 [3] */ 5395 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 5396 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, 5397 /* IP12_19_17 [3] */ 5398 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 5399 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, 5400 /* IP12_16_14 [3] */ 5401 FN_SSI_SDATA3, FN_STP_ISCLK_0, 5402 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, 5403 /* IP12_13_11 [3] */ 5404 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 5405 FN_CAN_STEP0, 0, 0, 0, 5406 /* IP12_10_8 [3] */ 5407 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 5408 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, 5409 /* IP12_7_6 [2] */ 5410 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 5411 /* IP12_5_4 [2] */ 5412 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, 5413 /* IP12_3_2 [2] */ 5414 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, 5415 /* IP12_1_0 [2] */ 5416 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } 5417 }, 5418 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 5419 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { 5420 /* IP13_31 [1] */ 5421 0, 0, 5422 /* IP13_30_29 [2] */ 5423 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, 5424 /* IP13_28_26 [3] */ 5425 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 5426 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, 5427 /* IP13_25_23 [3] */ 5428 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 5429 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, 5430 /* IP13_22_19 [4] */ 5431 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 5432 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, 5433 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0, 5434 /* IP13_18_16 [3] */ 5435 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, 5436 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, 5437 /* IP13_15_13 [3] */ 5438 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, 5439 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, 5440 /* IP13_12_10 [3] */ 5441 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5, 5442 FN_CAN_DEBUGOUT8, 0, 0, 5443 /* IP13_9_7 [3] */ 5444 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 5445 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, 5446 /* IP13_6_3 [4] */ 5447 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0, 5448 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 5449 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, 5450 /* IP13_2_0 [3] */ 5451 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 5452 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } 5453 }, 5454 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 5455 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { 5456 /* IP14_30 [1] */ 5457 0, 0, 5458 /* IP14_30_28 [3] */ 5459 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 5460 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 5461 FN_HRTS0_N_C, 0, 5462 /* IP14_27_25 [3] */ 5463 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, 5464 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, 5465 /* IP14_24_22 [3] */ 5466 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 5467 FN_LCDOUT9, 0, 0, 0, 5468 /* IP14_21_19 [3] */ 5469 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 5470 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, 5471 /* IP14_18_16 [3] */ 5472 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 5473 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, 5474 /* IP14_15_12 [4] */ 5475 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, 5476 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 5477 0, 0, 0, 0, 0, 0, 0, 5478 /* IP14_11_9 [3] */ 5479 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, 5480 0, 0, 0, 5481 /* IP14_8_6 [3] */ 5482 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, 5483 0, 0, 0, 5484 /* IP14_5_3 [3] */ 5485 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, 5486 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, 5487 /* IP14_2_0 [3] */ 5488 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 5489 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 5490 FN_REMOCON, 0, } 5491 }, 5492 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 5493 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { 5494 /* IP15_31_30 [2] */ 5495 0, 0, 0, 0, 5496 /* IP15_29_28 [2] */ 5497 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, 5498 /* IP15_27_26 [2] */ 5499 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, 5500 /* IP15_25_23 [3] */ 5501 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, 5502 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0, 5503 /* IP15_22_20 [3] */ 5504 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 5505 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, 5506 /* IP15_19_18 [2] */ 5507 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, 5508 /* IP15_17_16 [2] */ 5509 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, 5510 /* IP15_15_14 [2] */ 5511 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, 5512 /* IP15_13_12 [2] */ 5513 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, 5514 /* IP15_11_9 [3] */ 5515 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, 5516 0, 0, 0, 5517 /* IP15_8_6 [3] */ 5518 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 5519 FN_IIC2_SDA, FN_I2C2_SDA, 0, 5520 /* IP15_5_3 [3] */ 5521 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, 5522 FN_IIC2_SCL, FN_I2C2_SCL, 0, 5523 /* IP15_2_0 [3] */ 5524 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 5525 FN_LCDOUT15, FN_SCIF_CLK_B, 0, } 5526 }, 5527 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 5528 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { 5529 /* IP16_31_28 [4] */ 5530 0, 0, 0, 0, 0, 0, 0, 0, 5531 0, 0, 0, 0, 0, 0, 0, 0, 5532 /* IP16_27_24 [4] */ 5533 0, 0, 0, 0, 0, 0, 0, 0, 5534 0, 0, 0, 0, 0, 0, 0, 0, 5535 /* IP16_23_20 [4] */ 5536 0, 0, 0, 0, 0, 0, 0, 0, 5537 0, 0, 0, 0, 0, 0, 0, 0, 5538 /* IP16_19_16 [4] */ 5539 0, 0, 0, 0, 0, 0, 0, 0, 5540 0, 0, 0, 0, 0, 0, 0, 0, 5541 /* IP16_15_12 [4] */ 5542 0, 0, 0, 0, 0, 0, 0, 0, 5543 0, 0, 0, 0, 0, 0, 0, 0, 5544 /* IP16_11_8 [4] */ 5545 0, 0, 0, 0, 0, 0, 0, 0, 5546 0, 0, 0, 0, 0, 0, 0, 0, 5547 /* IP16_7 [1] */ 5548 FN_USB1_OVC, FN_TCLK1_B, 5549 /* IP16_6 [1] */ 5550 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, 5551 /* IP16_5_3 [3] */ 5552 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 5553 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, 5554 /* IP16_2_0 [3] */ 5555 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 5556 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } 5557 }, 5558 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 5559 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 5560 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { 5561 /* SEL_SCIF1 [3] */ 5562 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 5563 FN_SEL_SCIF1_4, 0, 0, 0, 5564 /* SEL_SCIFB [2] */ 5565 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, 5566 /* SEL_SCIFB2 [2] */ 5567 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, 5568 /* SEL_SCIFB1 [3] */ 5569 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, 5570 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, 5571 FN_SEL_SCIFB1_6, 0, 5572 /* SEL_SCIFA1 [2] */ 5573 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 5574 FN_SEL_SCIFA1_3, 5575 /* SEL_SCIF0 [1] */ 5576 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 5577 /* SEL_SCIFA [1] */ 5578 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 5579 /* SEL_SOF1 [1] */ 5580 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 5581 /* SEL_SSI7 [2] */ 5582 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, 5583 /* SEL_SSI6 [1] */ 5584 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 5585 /* SEL_SSI5 [2] */ 5586 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, 5587 /* SEL_VI3 [1] */ 5588 FN_SEL_VI3_0, FN_SEL_VI3_1, 5589 /* SEL_VI2 [1] */ 5590 FN_SEL_VI2_0, FN_SEL_VI2_1, 5591 /* SEL_VI1 [1] */ 5592 FN_SEL_VI1_0, FN_SEL_VI1_1, 5593 /* SEL_VI0 [1] */ 5594 FN_SEL_VI0_0, FN_SEL_VI0_1, 5595 /* SEL_TSIF1 [2] */ 5596 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, 5597 /* RESERVED [1] */ 5598 0, 0, 5599 /* SEL_LBS [1] */ 5600 FN_SEL_LBS_0, FN_SEL_LBS_1, 5601 /* SEL_TSIF0 [2] */ 5602 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 5603 /* SEL_SOF3 [1] */ 5604 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 5605 /* SEL_SOF0 [1] */ 5606 FN_SEL_SOF0_0, FN_SEL_SOF0_1, } 5607 }, 5608 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 5609 3, 1, 1, 1, 2, 1, 2, 1, 2, 5610 1, 1, 1, 3, 3, 2, 3, 2, 2) { 5611 /* RESERVED [3] */ 5612 0, 0, 0, 0, 0, 0, 0, 0, 5613 /* SEL_TMU1 [1] */ 5614 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 5615 /* SEL_HSCIF1 [1] */ 5616 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 5617 /* SEL_SCIFCLK [1] */ 5618 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 5619 /* SEL_CAN0 [2] */ 5620 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 5621 /* SEL_CANCLK [1] */ 5622 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 5623 /* SEL_SCIFA2 [2] */ 5624 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, 5625 /* SEL_CAN1 [1] */ 5626 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 5627 /* RESERVED [2] */ 5628 0, 0, 0, 0, 5629 /* SEL_SCIF2 [1] */ 5630 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 5631 /* SEL_ADI [1] */ 5632 FN_SEL_ADI_0, FN_SEL_ADI_1, 5633 /* SEL_SSP [1] */ 5634 FN_SEL_SSP_0, FN_SEL_SSP_1, 5635 /* SEL_FM [3] */ 5636 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 5637 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, 5638 /* SEL_HSCIF0 [3] */ 5639 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 5640 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, 5641 /* SEL_GPS [2] */ 5642 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, 5643 /* RESERVED [3] */ 5644 0, 0, 0, 0, 0, 0, 0, 0, 5645 /* SEL_SIM [2] */ 5646 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, 5647 /* SEL_SSI8 [2] */ 5648 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } 5649 }, 5650 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5651 1, 1, 2, 4, 4, 2, 2, 5652 4, 2, 3, 2, 3, 2) { 5653 /* SEL_IICDVFS [1] */ 5654 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 5655 /* SEL_IIC0 [1] */ 5656 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 5657 /* RESERVED [2] */ 5658 0, 0, 0, 0, 5659 /* RESERVED [4] */ 5660 0, 0, 0, 0, 0, 0, 0, 0, 5661 0, 0, 0, 0, 0, 0, 0, 0, 5662 /* RESERVED [4] */ 5663 0, 0, 0, 0, 0, 0, 0, 0, 5664 0, 0, 0, 0, 0, 0, 0, 0, 5665 /* RESERVED [2] */ 5666 0, 0, 0, 0, 5667 /* SEL_IEB [2] */ 5668 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 5669 /* RESERVED [4] */ 5670 0, 0, 0, 0, 0, 0, 0, 0, 5671 0, 0, 0, 0, 0, 0, 0, 0, 5672 /* RESERVED [2] */ 5673 0, 0, 0, 0, 5674 /* SEL_IIC2 [3] */ 5675 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 5676 FN_SEL_IIC2_4, 0, 0, 0, 5677 /* SEL_IIC1 [2] */ 5678 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, 5679 /* SEL_I2C2 [3] */ 5680 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 5681 FN_SEL_I2C2_4, 0, 0, 0, 5682 /* SEL_I2C1 [2] */ 5683 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } 5684 }, 5685 { }, 5686 }; 5687 5688 static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5689 { 5690 if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31)) 5691 return -EINVAL; 5692 5693 *pocctrl = 0xe606008c; 5694 5695 return 31 - (pin & 0x1f); 5696 } 5697 5698 static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { 5699 .pin_to_pocctrl = r8a7790_pin_to_pocctrl, 5700 }; 5701 5702 const struct sh_pfc_soc_info r8a7790_pinmux_info = { 5703 .name = "r8a77900_pfc", 5704 .ops = &r8a7790_pinmux_ops, 5705 .unlock_reg = 0xe6060000, /* PMMR */ 5706 5707 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5708 5709 .pins = pinmux_pins, 5710 .nr_pins = ARRAY_SIZE(pinmux_pins), 5711 .groups = pinmux_groups, 5712 .nr_groups = ARRAY_SIZE(pinmux_groups), 5713 .functions = pinmux_functions, 5714 .nr_functions = ARRAY_SIZE(pinmux_functions), 5715 5716 .cfg_regs = pinmux_config_regs, 5717 5718 .pinmux_data = pinmux_data, 5719 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5720 }; 5721