1 #include <common.h>
2 #include <dm.h>
3 #include <dm/pinctrl.h>
4 #include <asm/arch/gpio.h>
5 #include <asm/gpio.h>
6 #include <asm/io.h>
7 
8 DECLARE_GLOBAL_DATA_PTR;
9 
10 #define MAX_PINS_ONE_IP			70
11 #define MODE_BITS_MASK			3
12 #define OSPEED_MASK			3
13 #define PUPD_MASK			3
14 #define OTYPE_MSK			1
15 #define AFR_MASK			0xF
16 
17 #ifndef CONFIG_SPL_BUILD
18 struct stm32_pinctrl_priv {
19 	int pinctrl_ngpios;
20 	struct list_head gpio_dev;
21 };
22 
23 struct stm32_gpio_bank {
24 	struct udevice *gpio_dev;
25 	struct list_head list;
26 };
27 
28 #define MAX_PIN_PER_BANK		16
29 
30 static char pin_name[PINNAME_SIZE];
31 #define PINMUX_MODE_COUNT		5
32 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
33 	"gpio input",
34 	"gpio output",
35 	"analog",
36 	"unknown",
37 	"alt function",
38 };
39 
40 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
41 {
42 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
43 	struct stm32_gpio_regs *regs = priv->regs;
44 	u32 af;
45 	u32 alt_shift = (offset % 8) * 4;
46 	u32 alt_index =  offset / 8;
47 
48 	af = (readl(&regs->afr[alt_index]) &
49 	      GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
50 
51 	return af;
52 }
53 
54 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
55 {
56 	struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
57 	struct gpio_dev_priv *uc_priv;
58 	struct stm32_gpio_bank *gpio_bank;
59 
60 	/*
61 	 * if get_pins_count has already been executed once on this
62 	 * pin-controller, no need to run it again
63 	 */
64 	if (priv->pinctrl_ngpios)
65 		return priv->pinctrl_ngpios;
66 
67 	/*
68 	 * walk through all banks to retrieve the pin-controller
69 	 * pins number
70 	 */
71 	list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
72 		uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
73 
74 		priv->pinctrl_ngpios += uc_priv->gpio_count;
75 	}
76 
77 	return priv->pinctrl_ngpios;
78 }
79 
80 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
81 						  unsigned int selector)
82 {
83 	struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
84 	struct stm32_gpio_bank *gpio_bank;
85 	struct gpio_dev_priv *uc_priv;
86 	int first_pin = 0;
87 
88 	/* look up for the bank which owns the requested pin */
89 	list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
90 		uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
91 
92 		if (selector < (first_pin + uc_priv->gpio_count))
93 			/* we found the bank */
94 			return gpio_bank->gpio_dev;
95 
96 		first_pin += uc_priv->gpio_count;
97 	}
98 
99 	return NULL;
100 }
101 
102 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
103 					      unsigned int selector)
104 {
105 	struct gpio_dev_priv *uc_priv;
106 	struct udevice *gpio_dev;
107 
108 	/* look up for the bank which owns the requested pin */
109 	gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
110 	if (!gpio_dev) {
111 		snprintf(pin_name, PINNAME_SIZE, "Error");
112 	} else {
113 		uc_priv = dev_get_uclass_priv(gpio_dev);
114 
115 		snprintf(pin_name, PINNAME_SIZE, "%s%d",
116 			 uc_priv->bank_name,
117 			 selector % MAX_PIN_PER_BANK);
118 	}
119 
120 	return pin_name;
121 }
122 
123 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
124 					unsigned int selector,
125 					char *buf,
126 					int size)
127 {
128 	struct udevice *gpio_dev;
129 	const char *label;
130 	int gpio_pin;
131 	int mode;
132 	int af_num;
133 
134 	/* look up for the bank which owns the requested pin */
135 	gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
136 
137 	if (!gpio_dev)
138 		return -ENODEV;
139 
140 	/* translate pin-controller pin number to gpio pin number */
141 	gpio_pin = selector % MAX_PIN_PER_BANK;
142 
143 	mode = gpio_get_raw_function(gpio_dev, gpio_pin, &label);
144 
145 	dev_dbg(dev, "selector = %d gpio_pin = %d mode = %d\n",
146 		selector, gpio_pin, mode);
147 
148 	switch (mode) {
149 	case GPIOF_UNKNOWN:
150 		/* should never happen */
151 		return -EINVAL;
152 	case GPIOF_UNUSED:
153 		snprintf(buf, size, "%s", pinmux_mode[mode]);
154 		break;
155 	case GPIOF_FUNC:
156 		af_num = stm32_pinctrl_get_af(gpio_dev, gpio_pin);
157 		snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
158 		break;
159 	case GPIOF_OUTPUT:
160 	case GPIOF_INPUT:
161 		snprintf(buf, size, "%s %s",
162 			 pinmux_mode[mode], label ? label : "");
163 		break;
164 	}
165 
166 	return 0;
167 }
168 
169 int stm32_pinctrl_probe(struct udevice *dev)
170 {
171 	struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
172 	struct udevice *gpio_dev;
173 	struct udevice *child;
174 	struct stm32_gpio_bank *gpio_bank;
175 	int ret;
176 
177 	INIT_LIST_HEAD(&priv->gpio_dev);
178 
179 	/*
180 	 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
181 	 * a list with all gpio device reference which belongs to the
182 	 * current pin-controller. This list is used to find pin_name and
183 	 * pin muxing
184 	 */
185 	list_for_each_entry(child, &dev->child_head, sibling_node) {
186 		ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
187 						&gpio_dev);
188 		if (ret < 0)
189 			continue;
190 
191 		gpio_bank = malloc(sizeof(*gpio_bank));
192 		if (!gpio_bank) {
193 			dev_err(dev, "Not enough memory\n");
194 			return -ENOMEM;
195 		}
196 
197 		gpio_bank->gpio_dev = gpio_dev;
198 		list_add_tail(&gpio_bank->list, &priv->gpio_dev);
199 	}
200 
201 	return 0;
202 }
203 #endif
204 
205 static int stm32_gpio_config(struct gpio_desc *desc,
206 			     const struct stm32_gpio_ctl *ctl)
207 {
208 	struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
209 	struct stm32_gpio_regs *regs = priv->regs;
210 	u32 index;
211 
212 	if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
213 	    ctl->pupd > 2 || ctl->speed > 3)
214 		return -EINVAL;
215 
216 	index = (desc->offset & 0x07) * 4;
217 	clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
218 			ctl->af << index);
219 
220 	index = desc->offset * 2;
221 	clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index,
222 			ctl->mode << index);
223 	clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index,
224 			ctl->speed << index);
225 	clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index);
226 
227 	index = desc->offset;
228 	clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
229 
230 	return 0;
231 }
232 
233 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
234 {
235 	gpio_dsc->port = (port_pin & 0x1F000) >> 12;
236 	gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
237 	debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
238 	      gpio_dsc->pin);
239 
240 	return 0;
241 }
242 
243 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
244 {
245 	gpio_fn &= 0x00FF;
246 	gpio_ctl->af = 0;
247 
248 	switch (gpio_fn) {
249 	case 0:
250 		gpio_ctl->mode = STM32_GPIO_MODE_IN;
251 		break;
252 	case 1 ... 16:
253 		gpio_ctl->mode = STM32_GPIO_MODE_AF;
254 		gpio_ctl->af = gpio_fn - 1;
255 		break;
256 	case 17:
257 		gpio_ctl->mode = STM32_GPIO_MODE_AN;
258 		break;
259 	default:
260 		gpio_ctl->mode = STM32_GPIO_MODE_OUT;
261 		break;
262 	}
263 
264 	gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
265 
266 	if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
267 		gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
268 	else
269 		gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
270 
271 	if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
272 		gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
273 	else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
274 		gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
275 	else
276 		gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
277 
278 	debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
279 	      __func__,  gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
280 	     gpio_ctl->pupd);
281 
282 	return 0;
283 }
284 
285 static int stm32_pinctrl_config(int offset)
286 {
287 	u32 pin_mux[MAX_PINS_ONE_IP];
288 	int rv, len;
289 
290 	/*
291 	 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
292 	 * usart1) of pin controller phandle "pinctrl-0"
293 	 * */
294 	fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
295 		struct stm32_gpio_dsc gpio_dsc;
296 		struct stm32_gpio_ctl gpio_ctl;
297 		int i;
298 
299 		len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
300 						 "pinmux", pin_mux,
301 						 ARRAY_SIZE(pin_mux));
302 		debug("%s: no of pinmux entries= %d\n", __func__, len);
303 		if (len < 0)
304 			return -EINVAL;
305 		for (i = 0; i < len; i++) {
306 			struct gpio_desc desc;
307 
308 			debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
309 			prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
310 			prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
311 			rv = uclass_get_device_by_seq(UCLASS_GPIO,
312 						      gpio_dsc.port,
313 						      &desc.dev);
314 			if (rv)
315 				return rv;
316 			desc.offset = gpio_dsc.pin;
317 			rv = stm32_gpio_config(&desc, &gpio_ctl);
318 			debug("%s: rv = %d\n\n", __func__, rv);
319 			if (rv)
320 				return rv;
321 		}
322 	}
323 
324 	return 0;
325 }
326 
327 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
328 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
329 {
330 	return stm32_pinctrl_config(dev_of_offset(config));
331 }
332 #else /* PINCTRL_FULL */
333 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
334 					  struct udevice *periph)
335 {
336 	const void *fdt = gd->fdt_blob;
337 	const fdt32_t *list;
338 	uint32_t phandle;
339 	int config_node;
340 	int size, i, ret;
341 
342 	list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
343 	if (!list)
344 		return -EINVAL;
345 
346 	debug("%s: periph->name = %s\n", __func__, periph->name);
347 
348 	size /= sizeof(*list);
349 	for (i = 0; i < size; i++) {
350 		phandle = fdt32_to_cpu(*list++);
351 
352 		config_node = fdt_node_offset_by_phandle(fdt, phandle);
353 		if (config_node < 0) {
354 			pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
355 			return -EINVAL;
356 		}
357 
358 		ret = stm32_pinctrl_config(config_node);
359 		if (ret)
360 			return ret;
361 	}
362 
363 	return 0;
364 }
365 #endif /* PINCTRL_FULL */
366 
367 static struct pinctrl_ops stm32_pinctrl_ops = {
368 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
369 	.set_state		= stm32_pinctrl_set_state,
370 #else /* PINCTRL_FULL */
371 	.set_state_simple	= stm32_pinctrl_set_state_simple,
372 #endif /* PINCTRL_FULL */
373 #ifndef CONFIG_SPL_BUILD
374 	.get_pin_name		= stm32_pinctrl_get_pin_name,
375 	.get_pins_count		= stm32_pinctrl_get_pins_count,
376 	.get_pin_muxing		= stm32_pinctrl_get_pin_muxing,
377 #endif
378 };
379 
380 static const struct udevice_id stm32_pinctrl_ids[] = {
381 	{ .compatible = "st,stm32f429-pinctrl" },
382 	{ .compatible = "st,stm32f469-pinctrl" },
383 	{ .compatible = "st,stm32f746-pinctrl" },
384 	{ .compatible = "st,stm32h743-pinctrl" },
385 	{ .compatible = "st,stm32mp157-pinctrl" },
386 	{ .compatible = "st,stm32mp157-z-pinctrl" },
387 	{ }
388 };
389 
390 U_BOOT_DRIVER(pinctrl_stm32) = {
391 	.name			= "pinctrl_stm32",
392 	.id			= UCLASS_PINCTRL,
393 	.of_match		= stm32_pinctrl_ids,
394 	.ops			= &stm32_pinctrl_ops,
395 	.bind			= dm_scan_fdt_dev,
396 #ifndef CONFIG_SPL_BUILD
397 	.probe			= stm32_pinctrl_probe,
398 	.priv_auto_alloc_size	= sizeof(struct stm32_pinctrl_priv),
399 #endif
400 };
401