1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> 4 */ 5 6 #include <common.h> 7 #include <mapmem.h> 8 #include <linux/io.h> 9 #include <linux/err.h> 10 #include <dm.h> 11 #include <dm/pinctrl.h> 12 13 #include "pinctrl-imx.h" 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) 18 { 19 struct imx_pinctrl_priv *priv = dev_get_priv(dev); 20 struct imx_pinctrl_soc_info *info = priv->info; 21 int node = dev_of_offset(config); 22 const struct fdt_property *prop; 23 u32 *pin_data; 24 int npins, size, pin_size; 25 int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val; 26 u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0; 27 int i, j = 0; 28 29 dev_dbg(dev, "%s: %s\n", __func__, config->name); 30 31 if (info->flags & IMX8_USE_SCU) 32 pin_size = SHARE_IMX8_PIN_SIZE; 33 else if (info->flags & SHARE_MUX_CONF_REG) 34 pin_size = SHARE_FSL_PIN_SIZE; 35 else 36 pin_size = FSL_PIN_SIZE; 37 38 prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size); 39 if (!prop) { 40 dev_err(dev, "No fsl,pins property in node %s\n", config->name); 41 return -EINVAL; 42 } 43 44 if (!size || size % pin_size) { 45 dev_err(dev, "Invalid fsl,pins property in node %s\n", 46 config->name); 47 return -EINVAL; 48 } 49 50 pin_data = devm_kzalloc(dev, size, 0); 51 if (!pin_data) 52 return -ENOMEM; 53 54 if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins", 55 pin_data, size >> 2)) { 56 dev_err(dev, "Error reading pin data.\n"); 57 devm_kfree(dev, pin_data); 58 return -EINVAL; 59 } 60 61 npins = size / pin_size; 62 63 if (info->flags & IMX8_USE_SCU) { 64 imx_pinctrl_scu_conf_pins(info, pin_data, npins); 65 } else { 66 /* 67 * Refer to linux documentation for details: 68 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt 69 */ 70 for (i = 0; i < npins; i++) { 71 mux_reg = pin_data[j++]; 72 73 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) 74 mux_reg = -1; 75 76 if (info->flags & SHARE_MUX_CONF_REG) { 77 conf_reg = mux_reg; 78 } else { 79 conf_reg = pin_data[j++]; 80 if (!(info->flags & ZERO_OFFSET_VALID) && 81 !conf_reg) 82 conf_reg = -1; 83 } 84 85 if ((mux_reg == -1) || (conf_reg == -1)) { 86 dev_err(dev, "Error mux_reg or conf_reg\n"); 87 devm_kfree(dev, pin_data); 88 return -EINVAL; 89 } 90 91 input_reg = pin_data[j++]; 92 mux_mode = pin_data[j++]; 93 input_val = pin_data[j++]; 94 config_val = pin_data[j++]; 95 96 dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, " 97 "input_reg 0x%x, mux_mode 0x%x, " 98 "input_val 0x%x, config_val 0x%x\n", 99 mux_reg, conf_reg, input_reg, mux_mode, 100 input_val, config_val); 101 102 if (config_val & IMX_PAD_SION) 103 mux_mode |= IOMUXC_CONFIG_SION; 104 105 config_val &= ~IMX_PAD_SION; 106 107 /* Set Mux */ 108 if (info->flags & SHARE_MUX_CONF_REG) { 109 clrsetbits_le32(info->base + mux_reg, 110 info->mux_mask, 111 mux_mode << mux_shift); 112 } else { 113 writel(mux_mode, info->base + mux_reg); 114 } 115 116 dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", 117 mux_reg, mux_mode); 118 119 /* 120 * Set select input 121 * 122 * If the select input value begins with 0xff, 123 * it's a quirky select input and the value should 124 * be interpreted as below. 125 * 31 23 15 7 0 126 * | 0xff | shift | width | select | 127 * It's used to work around the problem that the 128 * select input for some pin is not implemented in 129 * the select input register but in some general 130 * purpose register. We encode the select input 131 * value, width and shift of the bit field into 132 * input_val cell of pin function ID in device tree, 133 * and then decode them here for setting up the select 134 * input bits in general purpose register. 135 */ 136 137 if (input_val >> 24 == 0xff) { 138 u32 val = input_val; 139 u8 select = val & 0xff; 140 u8 width = (val >> 8) & 0xff; 141 u8 shift = (val >> 16) & 0xff; 142 u32 mask = ((1 << width) - 1) << shift; 143 /* 144 * The input_reg[i] here is actually some 145 * IOMUXC general purpose register, not 146 * regular select input register. 147 */ 148 val = readl(info->base + input_reg); 149 val &= ~mask; 150 val |= select << shift; 151 writel(val, info->base + input_reg); 152 } else if (input_reg) { 153 /* 154 * Regular select input register can never be 155 * at offset 0, and we only print register 156 * value for regular case. 157 */ 158 if (info->input_sel_base) 159 writel(input_val, 160 info->input_sel_base + 161 input_reg); 162 else 163 writel(input_val, 164 info->base + input_reg); 165 166 dev_dbg(dev, "select_input: offset 0x%x val " 167 "0x%x\n", input_reg, input_val); 168 } 169 170 /* Set config */ 171 if (!(config_val & IMX_NO_PAD_CTL)) { 172 if (info->flags & SHARE_MUX_CONF_REG) { 173 clrsetbits_le32(info->base + conf_reg, 174 ~info->mux_mask, 175 config_val); 176 } else { 177 writel(config_val, 178 info->base + conf_reg); 179 } 180 181 dev_dbg(dev, "write config: offset 0x%x val " 182 "0x%x\n", conf_reg, config_val); 183 } 184 } 185 } 186 187 devm_kfree(dev, pin_data); 188 189 return 0; 190 } 191 192 const struct pinctrl_ops imx_pinctrl_ops = { 193 .set_state = imx_pinctrl_set_state, 194 }; 195 196 int imx_pinctrl_probe(struct udevice *dev, 197 struct imx_pinctrl_soc_info *info) 198 { 199 struct imx_pinctrl_priv *priv = dev_get_priv(dev); 200 int node = dev_of_offset(dev), ret; 201 struct fdtdec_phandle_args arg; 202 fdt_addr_t addr; 203 fdt_size_t size; 204 205 if (!info) { 206 dev_err(dev, "wrong pinctrl info\n"); 207 return -EINVAL; 208 } 209 210 priv->dev = dev; 211 priv->info = info; 212 213 if (info->flags & IMX8_USE_SCU) 214 return 0; 215 216 addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg", 217 &size); 218 219 if (addr == FDT_ADDR_T_NONE) 220 return -EINVAL; 221 222 info->base = map_sysmem(addr, size); 223 if (!info->base) 224 return -ENOMEM; 225 priv->info = info; 226 227 info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0); 228 /* 229 * Refer to linux documentation for details: 230 * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt 231 */ 232 if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) { 233 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, 234 node, "fsl,input-sel", 235 NULL, 0, 0, &arg); 236 if (ret) { 237 dev_err(dev, "iomuxc fsl,input-sel property not found\n"); 238 return -EINVAL; 239 } 240 241 addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg", 242 &size); 243 if (addr == FDT_ADDR_T_NONE) 244 return -EINVAL; 245 246 info->input_sel_base = map_sysmem(addr, size); 247 if (!info->input_sel_base) 248 return -ENOMEM; 249 } 250 251 dev_dbg(dev, "initialized IMX pinctrl driver\n"); 252 253 return 0; 254 } 255 256 int imx_pinctrl_remove(struct udevice *dev) 257 { 258 struct imx_pinctrl_priv *priv = dev_get_priv(dev); 259 struct imx_pinctrl_soc_info *info = priv->info; 260 261 if (info->flags & IMX8_USE_SCU) 262 return 0; 263 264 if (info->input_sel_base) 265 unmap_sysmem(info->input_sel_base); 266 if (info->base) 267 unmap_sysmem(info->base); 268 269 return 0; 270 } 271