1 /* 2 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <mapmem.h> 9 #include <linux/io.h> 10 #include <linux/err.h> 11 #include <dm/device.h> 12 #include <dm/pinctrl.h> 13 14 #include "pinctrl-imx.h" 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) 19 { 20 struct imx_pinctrl_priv *priv = dev_get_priv(dev); 21 struct imx_pinctrl_soc_info *info = priv->info; 22 int node = dev_of_offset(config); 23 const struct fdt_property *prop; 24 u32 *pin_data; 25 int npins, size, pin_size; 26 int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val; 27 u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0; 28 int i, j = 0; 29 30 dev_dbg(dev, "%s: %s\n", __func__, config->name); 31 32 if (info->flags & SHARE_MUX_CONF_REG) 33 pin_size = SHARE_FSL_PIN_SIZE; 34 else 35 pin_size = FSL_PIN_SIZE; 36 37 prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size); 38 if (!prop) { 39 dev_err(dev, "No fsl,pins property in node %s\n", config->name); 40 return -EINVAL; 41 } 42 43 if (!size || size % pin_size) { 44 dev_err(dev, "Invalid fsl,pins property in node %s\n", 45 config->name); 46 return -EINVAL; 47 } 48 49 pin_data = devm_kzalloc(dev, size, 0); 50 if (!pin_data) 51 return -ENOMEM; 52 53 if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins", 54 pin_data, size >> 2)) { 55 dev_err(dev, "Error reading pin data.\n"); 56 return -EINVAL; 57 } 58 59 npins = size / pin_size; 60 61 /* 62 * Refer to linux documentation for details: 63 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt 64 */ 65 for (i = 0; i < npins; i++) { 66 mux_reg = pin_data[j++]; 67 68 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) 69 mux_reg = -1; 70 71 if (info->flags & SHARE_MUX_CONF_REG) { 72 conf_reg = mux_reg; 73 } else { 74 conf_reg = pin_data[j++]; 75 if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg) 76 conf_reg = -1; 77 } 78 79 if ((mux_reg == -1) || (conf_reg == -1)) { 80 dev_err(dev, "Error mux_reg or conf_reg\n"); 81 return -EINVAL; 82 } 83 84 input_reg = pin_data[j++]; 85 mux_mode = pin_data[j++]; 86 input_val = pin_data[j++]; 87 config_val = pin_data[j++]; 88 89 dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, " 90 "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n", 91 mux_reg, conf_reg, input_reg, mux_mode, input_val, 92 config_val); 93 94 if (config_val & IMX_PAD_SION) 95 mux_mode |= IOMUXC_CONFIG_SION; 96 97 config_val &= ~IMX_PAD_SION; 98 99 /* Set Mux */ 100 if (info->flags & SHARE_MUX_CONF_REG) { 101 clrsetbits_le32(info->base + mux_reg, info->mux_mask, 102 mux_mode << mux_shift); 103 } else { 104 writel(mux_mode, info->base + mux_reg); 105 } 106 107 dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg, 108 mux_mode); 109 110 /* 111 * Set select input 112 * 113 * If the select input value begins with 0xff, it's a quirky 114 * select input and the value should be interpreted as below. 115 * 31 23 15 7 0 116 * | 0xff | shift | width | select | 117 * It's used to work around the problem that the select 118 * input for some pin is not implemented in the select 119 * input register but in some general purpose register. 120 * We encode the select input value, width and shift of 121 * the bit field into input_val cell of pin function ID 122 * in device tree, and then decode them here for setting 123 * up the select input bits in general purpose register. 124 */ 125 126 if (input_val >> 24 == 0xff) { 127 u32 val = input_val; 128 u8 select = val & 0xff; 129 u8 width = (val >> 8) & 0xff; 130 u8 shift = (val >> 16) & 0xff; 131 u32 mask = ((1 << width) - 1) << shift; 132 /* 133 * The input_reg[i] here is actually some IOMUXC general 134 * purpose register, not regular select input register. 135 */ 136 val = readl(info->base + input_reg); 137 val &= ~mask; 138 val |= select << shift; 139 writel(val, info->base + input_reg); 140 } else if (input_reg) { 141 /* 142 * Regular select input register can never be at offset 143 * 0, and we only print register value for regular case. 144 */ 145 if (info->input_sel_base) 146 writel(input_val, info->input_sel_base + 147 input_reg); 148 else 149 writel(input_val, info->base + input_reg); 150 151 dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n", 152 input_reg, input_val); 153 } 154 155 /* Set config */ 156 if (!(config_val & IMX_NO_PAD_CTL)) { 157 if (info->flags & SHARE_MUX_CONF_REG) { 158 clrsetbits_le32(info->base + conf_reg, 159 info->mux_mask, config_val); 160 } else { 161 writel(config_val, info->base + conf_reg); 162 } 163 164 dev_dbg(dev, "write config: offset 0x%x val 0x%x\n", 165 conf_reg, config_val); 166 } 167 } 168 169 return 0; 170 } 171 172 const struct pinctrl_ops imx_pinctrl_ops = { 173 .set_state = imx_pinctrl_set_state, 174 }; 175 176 int imx_pinctrl_probe(struct udevice *dev, 177 struct imx_pinctrl_soc_info *info) 178 { 179 struct imx_pinctrl_priv *priv = dev_get_priv(dev); 180 int node = dev_of_offset(dev), ret; 181 struct fdtdec_phandle_args arg; 182 fdt_addr_t addr; 183 fdt_size_t size; 184 185 if (!info) { 186 dev_err(dev, "wrong pinctrl info\n"); 187 return -EINVAL; 188 } 189 190 priv->dev = dev; 191 priv->info = info; 192 193 addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg", 194 &size); 195 196 if (addr == FDT_ADDR_T_NONE) 197 return -EINVAL; 198 199 info->base = map_sysmem(addr, size); 200 if (!info->base) 201 return -ENOMEM; 202 priv->info = info; 203 204 info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0); 205 /* 206 * Refer to linux documentation for details: 207 * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt 208 */ 209 if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) { 210 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, 211 node, "fsl,input-sel", 212 NULL, 0, 0, &arg); 213 if (ret) { 214 dev_err(dev, "iomuxc fsl,input-sel property not found\n"); 215 return -EINVAL; 216 } 217 218 addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg", 219 &size); 220 if (addr == FDT_ADDR_T_NONE) 221 return -EINVAL; 222 223 info->input_sel_base = map_sysmem(addr, size); 224 if (!info->input_sel_base) 225 return -ENOMEM; 226 } 227 228 dev_dbg(dev, "initialized IMX pinctrl driver\n"); 229 230 return 0; 231 } 232 233 int imx_pinctrl_remove(struct udevice *dev) 234 { 235 struct imx_pinctrl_priv *priv = dev_get_priv(dev); 236 struct imx_pinctrl_soc_info *info = priv->info; 237 238 if (info->input_sel_base) 239 unmap_sysmem(info->input_sel_base); 240 if (info->base) 241 unmap_sysmem(info->base); 242 243 return 0; 244 } 245