1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016 Marvell International Ltd. 4 * https://spdx.org/licenses 5 */ 6 7 #include <common.h> 8 #include <config.h> 9 #include <fdtdec.h> 10 #include <errno.h> 11 #include <dm.h> 12 #include <dm/pinctrl.h> 13 #include <dm/root.h> 14 #include <asm/system.h> 15 #include <asm/io.h> 16 #include <asm/arch-armada8k/soc-info.h> 17 #include "pinctrl-mvebu.h" 18 19 #define AP_EMMC_PHY_CTRL_REG 0x100 20 #define CP_EMMC_PHY_CTRL_REG 0x424 21 #define EMMC_PHY_CTRL_SDPHY_EN BIT(0) 22 23 #define AP806_EMMC_CLK_PIN_ID 0 24 #define AP806_EMMC_CLK_FUNC 0x1 25 #define CP110_EMMC_CLK_PIN_ID 56 26 #define CP110_EMMC_CLK_FUNC 0xe 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* mvebu_pinctl_emmc_set_mux: configure sd/mmc PHY mux 31 * To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux. 32 * eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC 33 * controller: 34 * - Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer, 35 * - Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller 36 * If pin function is set to eMMC/SD, then configure the eMMC/SD PHY 37 * muxltiplexer register to be on SDIO/eMMC controller 38 */ 39 void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func) 40 { 41 const void *blob = gd->fdt_blob; 42 int node = dev_of_offset(dev); 43 struct mvebu_pinctrl_priv *priv = dev_get_priv(dev); 44 45 if (!fdt_node_check_compatible(blob, node, "marvell,ap806-pinctrl")) { 46 if ((pin == AP806_EMMC_CLK_PIN_ID) && 47 (func == AP806_EMMC_CLK_FUNC)) { 48 clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG, 49 EMMC_PHY_CTRL_SDPHY_EN); 50 } 51 } else if (!fdt_node_check_compatible(blob, node, 52 "marvell,armada-8k-cpm-pinctrl")) { 53 if ((pin == CP110_EMMC_CLK_PIN_ID) && 54 (func == CP110_EMMC_CLK_FUNC)) { 55 clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG, 56 EMMC_PHY_CTRL_SDPHY_EN); 57 } 58 } 59 } 60 61 /* 62 * mvebu_pinctrl_set_state: configure pin functions. 63 * @dev: the pinctrl device to be configured. 64 * @config: the state to be configured. 65 * @return: 0 in success 66 */ 67 int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config) 68 { 69 const void *blob = gd->fdt_blob; 70 int node = dev_of_offset(config); 71 struct mvebu_pinctrl_priv *priv; 72 u32 pin_arr[MVEBU_MAX_PINS_PER_BANK]; 73 u32 function; 74 int i, pin_count; 75 76 priv = dev_get_priv(dev); 77 78 pin_count = fdtdec_get_int_array_count(blob, node, 79 "marvell,pins", 80 pin_arr, 81 MVEBU_MAX_PINS_PER_BANK); 82 if (pin_count <= 0) { 83 debug("Failed reading pins array for pinconfig %s (%d)\n", 84 config->name, pin_count); 85 return -EINVAL; 86 } 87 88 function = fdtdec_get_int(blob, node, "marvell,function", 0xff); 89 90 /* 91 * Check if setup of PHY mux is needed for this pins group. 92 * Only the first pin id in array is tested, all the rest use the same 93 * pin function. 94 */ 95 mvebu_pinctl_emmc_set_mux(dev, pin_arr[0], function); 96 97 for (i = 0; i < pin_count; i++) { 98 int reg_offset; 99 int field_offset; 100 int pin = pin_arr[i]; 101 102 if (function > priv->max_func) { 103 debug("Illegal function %d for pinconfig %s\n", 104 function, config->name); 105 return -EINVAL; 106 } 107 108 /* Calculate register address and bit in register */ 109 reg_offset = priv->reg_direction * 4 * 110 (pin >> (PIN_REG_SHIFT)); 111 field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK); 112 113 clrsetbits_le32(priv->base_reg + reg_offset, 114 PIN_FUNC_MASK << field_offset, 115 (function & PIN_FUNC_MASK) << field_offset); 116 } 117 118 return 0; 119 } 120 121 /* 122 * mvebu_pinctrl_set_state_all: configure the entire bank pin functions. 123 * @dev: the pinctrl device to be configured. 124 * @config: the state to be configured. 125 * @return: 0 in success 126 */ 127 static int mvebu_pinctrl_set_state_all(struct udevice *dev, 128 struct udevice *config) 129 { 130 const void *blob = gd->fdt_blob; 131 int node = dev_of_offset(config); 132 struct mvebu_pinctrl_priv *priv; 133 u32 func_arr[MVEBU_MAX_PINS_PER_BANK]; 134 int pin, err; 135 136 priv = dev_get_priv(dev); 137 138 err = fdtdec_get_int_array(blob, node, "pin-func", 139 func_arr, priv->pin_cnt); 140 if (err) { 141 debug("Failed reading pin functions for bank %s\n", 142 priv->bank_name); 143 return -EINVAL; 144 } 145 146 /* Check if setup of PHY mux is needed for this pins group. */ 147 if (priv->pin_cnt < CP110_EMMC_CLK_PIN_ID) 148 mvebu_pinctl_emmc_set_mux(dev, AP806_EMMC_CLK_PIN_ID, 149 func_arr[AP806_EMMC_CLK_PIN_ID]); 150 else 151 mvebu_pinctl_emmc_set_mux(dev, CP110_EMMC_CLK_PIN_ID, 152 func_arr[CP110_EMMC_CLK_PIN_ID]); 153 154 for (pin = 0; pin < priv->pin_cnt; pin++) { 155 int reg_offset; 156 int field_offset; 157 u32 func = func_arr[pin]; 158 159 /* Bypass pins with function 0xFF */ 160 if (func == 0xff) { 161 debug("Warning: pin %d value is not modified ", pin); 162 debug("(kept as default)\n"); 163 continue; 164 } else if (func > priv->max_func) { 165 debug("Illegal function %d for pin %d\n", func, pin); 166 return -EINVAL; 167 } 168 169 /* Calculate register address and bit in register */ 170 reg_offset = priv->reg_direction * 4 * 171 (pin >> (PIN_REG_SHIFT)); 172 field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK); 173 174 clrsetbits_le32(priv->base_reg + reg_offset, 175 PIN_FUNC_MASK << field_offset, 176 (func & PIN_FUNC_MASK) << field_offset); 177 } 178 179 return 0; 180 } 181 182 int mvebu_pinctl_probe(struct udevice *dev) 183 { 184 const void *blob = gd->fdt_blob; 185 int node = dev_of_offset(dev); 186 struct mvebu_pinctrl_priv *priv; 187 188 priv = dev_get_priv(dev); 189 if (!priv) { 190 debug("%s: Failed to get private\n", __func__); 191 return -EINVAL; 192 } 193 194 priv->base_reg = devfdt_get_addr_ptr(dev); 195 if (priv->base_reg == (void *)FDT_ADDR_T_NONE) { 196 debug("%s: Failed to get base address\n", __func__); 197 return -EINVAL; 198 } 199 200 priv->pin_cnt = fdtdec_get_int(blob, node, "pin-count", 201 MVEBU_MAX_PINS_PER_BANK); 202 priv->max_func = fdtdec_get_int(blob, node, "max-func", 203 MVEBU_MAX_FUNC); 204 priv->bank_name = fdt_getprop(blob, node, "bank-name", NULL); 205 206 priv->reg_direction = 1; 207 if (fdtdec_get_bool(blob, node, "reverse-reg")) 208 priv->reg_direction = -1; 209 210 return mvebu_pinctrl_set_state_all(dev, dev); 211 } 212 213 static struct pinctrl_ops mvebu_pinctrl_ops = { 214 .set_state = mvebu_pinctrl_set_state 215 }; 216 217 static const struct udevice_id mvebu_pinctrl_ids[] = { 218 { .compatible = "marvell,mvebu-pinctrl" }, 219 { .compatible = "marvell,ap806-pinctrl" }, 220 { .compatible = "marvell,armada-7k-pinctrl" }, 221 { .compatible = "marvell,armada-8k-cpm-pinctrl" }, 222 { .compatible = "marvell,armada-8k-cps-pinctrl" }, 223 { } 224 }; 225 226 U_BOOT_DRIVER(pinctrl_mvebu) = { 227 .name = "mvebu_pinctrl", 228 .id = UCLASS_PINCTRL, 229 .of_match = mvebu_pinctrl_ids, 230 .priv_auto_alloc_size = sizeof(struct mvebu_pinctrl_priv), 231 .ops = &mvebu_pinctrl_ops, 232 .probe = mvebu_pinctl_probe 233 }; 234