1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * U-Boot Marvell 37xx SoC pinctrl driver
4  *
5  * Copyright (C) 2017 Stefan Roese <sr@denx.de>
6  *
7  * This driver is based on the Linux driver version, which is:
8  * Copyright (C) 2017 Marvell
9  * Gregory CLEMENT <gregory.clement@free-electrons.com>
10  *
11  * Additionally parts are derived from the Meson U-Boot pinctrl driver,
12  * which is:
13  * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
14  * Based on code from Linux kernel:
15  * Copyright (C) 2016 Endless Mobile, Inc.
16  * https://spdx.org/licenses
17  */
18 
19 #include <common.h>
20 #include <config.h>
21 #include <dm.h>
22 #include <dm/device-internal.h>
23 #include <dm/lists.h>
24 #include <dm/pinctrl.h>
25 #include <dm/root.h>
26 #include <errno.h>
27 #include <fdtdec.h>
28 #include <regmap.h>
29 #include <asm/gpio.h>
30 #include <asm/system.h>
31 #include <asm/io.h>
32 
33 DECLARE_GLOBAL_DATA_PTR;
34 
35 #define OUTPUT_EN	0x0
36 #define INPUT_VAL	0x10
37 #define OUTPUT_VAL	0x18
38 #define OUTPUT_CTL	0x20
39 #define SELECTION	0x30
40 
41 #define IRQ_EN		0x0
42 #define IRQ_POL		0x08
43 #define IRQ_STATUS	0x10
44 #define IRQ_WKUP	0x18
45 
46 #define NB_FUNCS 3
47 #define GPIO_PER_REG	32
48 
49 /**
50  * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
51  * The pins of a pinmux groups are composed of one or two groups of contiguous
52  * pins.
53  * @name:	Name of the pin group, used to lookup the group.
54  * @start_pins:	Index of the first pin of the main range of pins belonging to
55  *		the group
56  * @npins:	Number of pins included in the first range
57  * @reg_mask:	Bit mask matching the group in the selection register
58  * @extra_pins:	Index of the first pin of the optional second range of pins
59  *		belonging to the group
60  * @npins:	Number of pins included in the second optional range
61  * @funcs:	A list of pinmux functions that can be selected for this group.
62  * @pins:	List of the pins included in the group
63  */
64 struct armada_37xx_pin_group {
65 	const char	*name;
66 	unsigned int	start_pin;
67 	unsigned int	npins;
68 	u32		reg_mask;
69 	u32		val[NB_FUNCS];
70 	unsigned int	extra_pin;
71 	unsigned int	extra_npins;
72 	const char	*funcs[NB_FUNCS];
73 	unsigned int	*pins;
74 };
75 
76 struct armada_37xx_pin_data {
77 	u8				nr_pins;
78 	char				*name;
79 	struct armada_37xx_pin_group	*groups;
80 	int				ngroups;
81 };
82 
83 struct armada_37xx_pmx_func {
84 	const char		*name;
85 	const char		**groups;
86 	unsigned int		ngroups;
87 };
88 
89 struct armada_37xx_pinctrl {
90 	void __iomem			*base;
91 	const struct armada_37xx_pin_data	*data;
92 	struct udevice			*dev;
93 	struct pinctrl_dev		*pctl_dev;
94 	struct armada_37xx_pin_group	*groups;
95 	unsigned int			ngroups;
96 	struct armada_37xx_pmx_func	*funcs;
97 	unsigned int			nfuncs;
98 };
99 
100 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2)	\
101 	{					\
102 		.name = _name,			\
103 		.start_pin = _start,		\
104 		.npins = _nr,			\
105 		.reg_mask = _mask,		\
106 		.val = {0, _mask},		\
107 		.funcs = {_func1, _func2}	\
108 	}
109 
110 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1)	\
111 	{					\
112 		.name = _name,			\
113 		.start_pin = _start,		\
114 		.npins = _nr,			\
115 		.reg_mask = _mask,		\
116 		.val = {0, _mask},		\
117 		.funcs = {_func1, "gpio"}	\
118 	}
119 
120 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1)   \
121 	{					\
122 		.name = _name,			\
123 		.start_pin = _start,		\
124 		.npins = _nr,			\
125 		.reg_mask = _mask,		\
126 		.val = {_val1, _val2},		\
127 		.funcs = {_func1, "gpio"}	\
128 	}
129 
130 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
131 	{					\
132 		.name = _name,			\
133 		.start_pin = _start,		\
134 		.npins = _nr,			\
135 		.reg_mask = _mask,		\
136 		.val = {_v1, _v2, _v3},	\
137 		.funcs = {_f1, _f2, "gpio"}	\
138 	}
139 
140 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
141 		      _f1, _f2)				\
142 	{						\
143 		.name = _name,				\
144 		.start_pin = _start,			\
145 		.npins = _nr,				\
146 		.reg_mask = _mask,			\
147 		.val = {_v1, _v2},			\
148 		.extra_pin = _start2,			\
149 		.extra_npins = _nr2,			\
150 		.funcs = {_f1, _f2}			\
151 	}
152 
153 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
154 	PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
155 	PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
156 	PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
157 	PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
158 	PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
159 	PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
160 	PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
161 	PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
162 	PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
163 	PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
164 	PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
165 	PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
166 	PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
167 	PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
168 	PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
169 	PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
170 	PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
171 	PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
172 		      BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
173 		      18, 2, "gpio", "uart"),
174 	PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
175 	PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
176 	PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
177 	PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
178 
179 };
180 
181 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
182 	PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
183 	PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
184 	PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
185 	PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
186 	PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
187 	PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"),
188 	PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
189 	PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
190 	PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
191 	PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
192 		       "mii", "mii_err"),
193 };
194 
195 const struct armada_37xx_pin_data armada_37xx_pin_nb = {
196 	.nr_pins = 36,
197 	.name = "GPIO1",
198 	.groups = armada_37xx_nb_groups,
199 	.ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
200 };
201 
202 const struct armada_37xx_pin_data armada_37xx_pin_sb = {
203 	.nr_pins = 30,
204 	.name = "GPIO2",
205 	.groups = armada_37xx_sb_groups,
206 	.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
207 };
208 
209 static inline void armada_37xx_update_reg(unsigned int *reg,
210 					  unsigned int *offset)
211 {
212 	/* We never have more than 2 registers */
213 	if (*offset >= GPIO_PER_REG) {
214 		*offset -= GPIO_PER_REG;
215 		*reg += sizeof(u32);
216 	}
217 }
218 
219 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
220 				    const char *func)
221 {
222 	int f;
223 
224 	for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
225 		if (!strcmp(grp->funcs[f], func))
226 			return f;
227 
228 	return -ENOTSUPP;
229 }
230 
231 static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
232 {
233 	struct armada_37xx_pinctrl *info = dev_get_priv(dev);
234 
235 	return info->ngroups;
236 }
237 
238 static const char *armada_37xx_pmx_dummy_name = "_dummy";
239 
240 static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
241 						  unsigned selector)
242 {
243 	struct armada_37xx_pinctrl *info = dev_get_priv(dev);
244 
245 	if (!info->groups[selector].name)
246 		return armada_37xx_pmx_dummy_name;
247 
248 	return info->groups[selector].name;
249 }
250 
251 static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
252 {
253 	struct armada_37xx_pinctrl *info = dev_get_priv(dev);
254 
255 	return info->nfuncs;
256 }
257 
258 static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
259 						 unsigned selector)
260 {
261 	struct armada_37xx_pinctrl *info = dev_get_priv(dev);
262 
263 	return info->funcs[selector].name;
264 }
265 
266 static int armada_37xx_pmx_set_by_name(struct udevice *dev,
267 				       const char *name,
268 				       struct armada_37xx_pin_group *grp)
269 {
270 	struct armada_37xx_pinctrl *info = dev_get_priv(dev);
271 	unsigned int reg = SELECTION;
272 	unsigned int mask = grp->reg_mask;
273 	int func, val;
274 
275 	dev_dbg(info->dev, "enable function %s group %s\n",
276 		name, grp->name);
277 
278 	func = armada_37xx_get_func_reg(grp, name);
279 
280 	if (func < 0)
281 		return func;
282 
283 	val = grp->val[func];
284 
285 	clrsetbits_le32(info->base + reg, mask, val);
286 
287 	return 0;
288 }
289 
290 static int armada_37xx_pmx_group_set(struct udevice *dev,
291 				     unsigned group_selector,
292 				     unsigned func_selector)
293 {
294 	struct armada_37xx_pinctrl *info = dev_get_priv(dev);
295 	struct armada_37xx_pin_group *grp = &info->groups[group_selector];
296 	const char *name = info->funcs[func_selector].name;
297 
298 	return armada_37xx_pmx_set_by_name(dev, name, grp);
299 }
300 
301 /**
302  * armada_37xx_add_function() - Add a new function to the list
303  * @funcs: array of function to add the new one
304  * @funcsize: size of the remaining space for the function
305  * @name: name of the function to add
306  *
307  * If it is a new function then create it by adding its name else
308  * increment the number of group associated to this function.
309  */
310 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
311 				    int *funcsize, const char *name)
312 {
313 	int i = 0;
314 
315 	if (*funcsize <= 0)
316 		return -EOVERFLOW;
317 
318 	while (funcs->ngroups) {
319 		/* function already there */
320 		if (strcmp(funcs->name, name) == 0) {
321 			funcs->ngroups++;
322 
323 			return -EEXIST;
324 		}
325 		funcs++;
326 		i++;
327 	}
328 
329 	/* append new unique function */
330 	funcs->name = name;
331 	funcs->ngroups = 1;
332 	(*funcsize)--;
333 
334 	return 0;
335 }
336 
337 /**
338  * armada_37xx_fill_group() - complete the group array
339  * @info: info driver instance
340  *
341  * Based on the data available from the armada_37xx_pin_group array
342  * completes the last member of the struct for each function: the list
343  * of the groups associated to this function.
344  *
345  */
346 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
347 {
348 	int n, num = 0, funcsize = info->data->nr_pins;
349 
350 	for (n = 0; n < info->ngroups; n++) {
351 		struct armada_37xx_pin_group *grp = &info->groups[n];
352 		int i, j, f;
353 
354 		grp->pins = devm_kzalloc(info->dev,
355 					 (grp->npins + grp->extra_npins) *
356 					 sizeof(*grp->pins), GFP_KERNEL);
357 		if (!grp->pins)
358 			return -ENOMEM;
359 
360 		for (i = 0; i < grp->npins; i++)
361 			grp->pins[i] = grp->start_pin + i;
362 
363 		for (j = 0; j < grp->extra_npins; j++)
364 			grp->pins[i+j] = grp->extra_pin + j;
365 
366 		for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
367 			int ret;
368 			/* check for unique functions and count groups */
369 			ret = armada_37xx_add_function(info->funcs, &funcsize,
370 					    grp->funcs[f]);
371 			if (ret == -EOVERFLOW)
372 				dev_err(info->dev,
373 					"More functions than pins(%d)\n",
374 					info->data->nr_pins);
375 			if (ret < 0)
376 				continue;
377 			num++;
378 		}
379 	}
380 
381 	info->nfuncs = num;
382 
383 	return 0;
384 }
385 
386 /**
387  * armada_37xx_fill_funcs() - complete the funcs array
388  * @info: info driver instance
389  *
390  * Based on the data available from the armada_37xx_pin_group array
391  * completes the last two member of the struct for each group:
392  * - the list of the pins included in the group
393  * - the list of pinmux functions that can be selected for this group
394  *
395  */
396 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
397 {
398 	struct armada_37xx_pmx_func *funcs = info->funcs;
399 	int n;
400 
401 	for (n = 0; n < info->nfuncs; n++) {
402 		const char *name = funcs[n].name;
403 		const char **groups;
404 		int g;
405 
406 		funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
407 					       sizeof(*(funcs[n].groups)),
408 					       GFP_KERNEL);
409 		if (!funcs[n].groups)
410 			return -ENOMEM;
411 
412 		groups = funcs[n].groups;
413 
414 		for (g = 0; g < info->ngroups; g++) {
415 			struct armada_37xx_pin_group *gp = &info->groups[g];
416 			int f;
417 
418 			for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
419 				if (strcmp(gp->funcs[f], name) == 0) {
420 					*groups = gp->name;
421 					groups++;
422 				}
423 			}
424 		}
425 	}
426 	return 0;
427 }
428 
429 static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
430 {
431 	struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
432 	unsigned int reg = INPUT_VAL;
433 	unsigned int val, mask;
434 
435 	armada_37xx_update_reg(&reg, &offset);
436 	mask = BIT(offset);
437 
438 	val = readl(info->base + reg);
439 
440 	return (val & mask) != 0;
441 }
442 
443 static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
444 				int value)
445 {
446 	struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
447 	unsigned int reg = OUTPUT_VAL;
448 	unsigned int mask, val;
449 
450 	armada_37xx_update_reg(&reg, &offset);
451 	mask = BIT(offset);
452 	val = value ? mask : 0;
453 
454 	clrsetbits_le32(info->base + reg, mask, val);
455 
456 	return 0;
457 }
458 
459 static int armada_37xx_gpio_get_direction(struct udevice *dev,
460 					  unsigned int offset)
461 {
462 	struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
463 	unsigned int reg = OUTPUT_EN;
464 	unsigned int val, mask;
465 
466 	armada_37xx_update_reg(&reg, &offset);
467 	mask = BIT(offset);
468 	val = readl(info->base + reg);
469 
470 	if (val & mask)
471 		return GPIOF_OUTPUT;
472 	else
473 		return GPIOF_INPUT;
474 }
475 
476 static int armada_37xx_gpio_direction_input(struct udevice *dev,
477 					    unsigned int offset)
478 {
479 	struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
480 	unsigned int reg = OUTPUT_EN;
481 	unsigned int mask;
482 
483 	armada_37xx_update_reg(&reg, &offset);
484 	mask = BIT(offset);
485 
486 	clrbits_le32(info->base + reg, mask);
487 
488 	return 0;
489 }
490 
491 static int armada_37xx_gpio_direction_output(struct udevice *dev,
492 					     unsigned int offset, int value)
493 {
494 	struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
495 	unsigned int reg = OUTPUT_EN;
496 	unsigned int mask;
497 
498 	armada_37xx_update_reg(&reg, &offset);
499 	mask = BIT(offset);
500 
501 	setbits_le32(info->base + reg, mask);
502 
503 	/* And set the requested value */
504 	return armada_37xx_gpio_set(dev, offset, value);
505 }
506 
507 static int armada_37xx_gpio_probe(struct udevice *dev)
508 {
509 	struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
510 	struct gpio_dev_priv *uc_priv;
511 
512 	uc_priv = dev_get_uclass_priv(dev);
513 	uc_priv->bank_name = info->data->name;
514 	uc_priv->gpio_count = info->data->nr_pins;
515 
516 	return 0;
517 }
518 
519 static const struct dm_gpio_ops armada_37xx_gpio_ops = {
520 	.set_value = armada_37xx_gpio_set,
521 	.get_value = armada_37xx_gpio_get,
522 	.get_function = armada_37xx_gpio_get_direction,
523 	.direction_input = armada_37xx_gpio_direction_input,
524 	.direction_output = armada_37xx_gpio_direction_output,
525 };
526 
527 static struct driver armada_37xx_gpio_driver = {
528 	.name	= "armada-37xx-gpio",
529 	.id	= UCLASS_GPIO,
530 	.probe	= armada_37xx_gpio_probe,
531 	.ops	= &armada_37xx_gpio_ops,
532 };
533 
534 static int armada_37xx_gpiochip_register(struct udevice *parent,
535 					 struct armada_37xx_pinctrl *info)
536 {
537 	const void *blob = gd->fdt_blob;
538 	int node = dev_of_offset(parent);
539 	struct uclass_driver *drv;
540 	struct udevice *dev;
541 	int ret = -ENODEV;
542 	int subnode;
543 	char *name;
544 
545 	/* Lookup GPIO driver */
546 	drv = lists_uclass_lookup(UCLASS_GPIO);
547 	if (!drv) {
548 		puts("Cannot find GPIO driver\n");
549 		return -ENOENT;
550 	}
551 
552 	fdt_for_each_subnode(subnode, blob, node) {
553 		if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
554 			ret = 0;
555 			break;
556 		}
557 	};
558 	if (ret)
559 		return ret;
560 
561 	name = calloc(1, 32);
562 	sprintf(name, "armada-37xx-gpio");
563 
564 	/* Create child device UCLASS_GPIO and bind it */
565 	device_bind(parent, &armada_37xx_gpio_driver, name, NULL, subnode,
566 		    &dev);
567 	dev_set_of_offset(dev, subnode);
568 
569 	return 0;
570 }
571 
572 const struct pinctrl_ops armada_37xx_pinctrl_ops  = {
573 	.get_groups_count = armada_37xx_pmx_get_groups_count,
574 	.get_group_name = armada_37xx_pmx_get_group_name,
575 	.get_functions_count = armada_37xx_pmx_get_funcs_count,
576 	.get_function_name = armada_37xx_pmx_get_func_name,
577 	.pinmux_group_set = armada_37xx_pmx_group_set,
578 	.set_state = pinctrl_generic_set_state,
579 };
580 
581 int armada_37xx_pinctrl_probe(struct udevice *dev)
582 {
583 	struct armada_37xx_pinctrl *info = dev_get_priv(dev);
584 	const struct armada_37xx_pin_data *pin_data;
585 	int ret;
586 
587 	info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
588 	pin_data = info->data;
589 
590 	info->base = (void __iomem *)devfdt_get_addr(dev);
591 	if (!info->base) {
592 		pr_err("unable to find regmap\n");
593 		return -ENODEV;
594 	}
595 
596 	info->groups = pin_data->groups;
597 	info->ngroups = pin_data->ngroups;
598 
599 	/*
600 	 * we allocate functions for number of pins and hope there are
601 	 * fewer unique functions than pins available
602 	 */
603 	info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
604 			   sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
605 	if (!info->funcs)
606 		return -ENOMEM;
607 
608 
609 	ret = armada_37xx_fill_group(info);
610 	if (ret)
611 		return ret;
612 
613 	ret = armada_37xx_fill_func(info);
614 	if (ret)
615 		return ret;
616 
617 	ret = armada_37xx_gpiochip_register(dev, info);
618 	if (ret)
619 		return ret;
620 
621 	return 0;
622 }
623 
624 static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
625 	{
626 		.compatible = "marvell,armada3710-sb-pinctrl",
627 		.data = (ulong)&armada_37xx_pin_sb,
628 	},
629 	{
630 		.compatible = "marvell,armada3710-nb-pinctrl",
631 		.data = (ulong)&armada_37xx_pin_nb,
632 	},
633 	{ /* sentinel */ }
634 };
635 
636 U_BOOT_DRIVER(armada_37xx_pinctrl) = {
637 	.name = "armada-37xx-pinctrl",
638 	.id = UCLASS_PINCTRL,
639 	.of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
640 	.probe = armada_37xx_pinctrl_probe,
641 	.priv_auto_alloc_size = sizeof(struct armada_37xx_pinctrl),
642 	.ops = &armada_37xx_pinctrl_ops,
643 };
644