1 /* 2 * U-Boot Marvell 37xx SoC pinctrl driver 3 * 4 * Copyright (C) 2017 Stefan Roese <sr@denx.de> 5 * 6 * This driver is based on the Linux driver version, which is: 7 * Copyright (C) 2017 Marvell 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * 10 * Additionally parts are derived from the Meson U-Boot pinctrl driver, 11 * which is: 12 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> 13 * Based on code from Linux kernel: 14 * Copyright (C) 2016 Endless Mobile, Inc. 15 * 16 * SPDX-License-Identifier: GPL-2.0+ 17 * https://spdx.org/licenses 18 */ 19 20 #include <common.h> 21 #include <config.h> 22 #include <dm.h> 23 #include <dm/device-internal.h> 24 #include <dm/lists.h> 25 #include <dm/pinctrl.h> 26 #include <dm/root.h> 27 #include <errno.h> 28 #include <fdtdec.h> 29 #include <regmap.h> 30 #include <asm/gpio.h> 31 #include <asm/system.h> 32 #include <asm/io.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define OUTPUT_EN 0x0 37 #define INPUT_VAL 0x10 38 #define OUTPUT_VAL 0x18 39 #define OUTPUT_CTL 0x20 40 #define SELECTION 0x30 41 42 #define IRQ_EN 0x0 43 #define IRQ_POL 0x08 44 #define IRQ_STATUS 0x10 45 #define IRQ_WKUP 0x18 46 47 #define NB_FUNCS 3 48 #define GPIO_PER_REG 32 49 50 /** 51 * struct armada_37xx_pin_group: represents group of pins of a pinmux function. 52 * The pins of a pinmux groups are composed of one or two groups of contiguous 53 * pins. 54 * @name: Name of the pin group, used to lookup the group. 55 * @start_pins: Index of the first pin of the main range of pins belonging to 56 * the group 57 * @npins: Number of pins included in the first range 58 * @reg_mask: Bit mask matching the group in the selection register 59 * @extra_pins: Index of the first pin of the optional second range of pins 60 * belonging to the group 61 * @npins: Number of pins included in the second optional range 62 * @funcs: A list of pinmux functions that can be selected for this group. 63 * @pins: List of the pins included in the group 64 */ 65 struct armada_37xx_pin_group { 66 const char *name; 67 unsigned int start_pin; 68 unsigned int npins; 69 u32 reg_mask; 70 u32 val[NB_FUNCS]; 71 unsigned int extra_pin; 72 unsigned int extra_npins; 73 const char *funcs[NB_FUNCS]; 74 unsigned int *pins; 75 }; 76 77 struct armada_37xx_pin_data { 78 u8 nr_pins; 79 char *name; 80 struct armada_37xx_pin_group *groups; 81 int ngroups; 82 }; 83 84 struct armada_37xx_pmx_func { 85 const char *name; 86 const char **groups; 87 unsigned int ngroups; 88 }; 89 90 struct armada_37xx_pinctrl { 91 void __iomem *base; 92 const struct armada_37xx_pin_data *data; 93 struct udevice *dev; 94 struct pinctrl_dev *pctl_dev; 95 struct armada_37xx_pin_group *groups; 96 unsigned int ngroups; 97 struct armada_37xx_pmx_func *funcs; 98 unsigned int nfuncs; 99 }; 100 101 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \ 102 { \ 103 .name = _name, \ 104 .start_pin = _start, \ 105 .npins = _nr, \ 106 .reg_mask = _mask, \ 107 .val = {0, _mask}, \ 108 .funcs = {_func1, _func2} \ 109 } 110 111 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ 112 { \ 113 .name = _name, \ 114 .start_pin = _start, \ 115 .npins = _nr, \ 116 .reg_mask = _mask, \ 117 .val = {0, _mask}, \ 118 .funcs = {_func1, "gpio"} \ 119 } 120 121 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ 122 { \ 123 .name = _name, \ 124 .start_pin = _start, \ 125 .npins = _nr, \ 126 .reg_mask = _mask, \ 127 .val = {_val1, _val2}, \ 128 .funcs = {_func1, "gpio"} \ 129 } 130 131 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \ 132 { \ 133 .name = _name, \ 134 .start_pin = _start, \ 135 .npins = _nr, \ 136 .reg_mask = _mask, \ 137 .val = {_v1, _v2, _v3}, \ 138 .funcs = {_f1, _f2, "gpio"} \ 139 } 140 141 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ 142 _f1, _f2) \ 143 { \ 144 .name = _name, \ 145 .start_pin = _start, \ 146 .npins = _nr, \ 147 .reg_mask = _mask, \ 148 .val = {_v1, _v2}, \ 149 .extra_pin = _start2, \ 150 .extra_npins = _nr2, \ 151 .funcs = {_f1, _f2} \ 152 } 153 154 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { 155 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), 156 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), 157 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), 158 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"), 159 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"), 160 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"), 161 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"), 162 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), 163 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), 164 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), 165 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), 166 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), 167 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"), 168 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"), 169 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), 170 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), 171 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), 172 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), 173 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), 174 18, 2, "gpio", "uart"), 175 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"), 176 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"), 177 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"), 178 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"), 179 180 }; 181 182 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { 183 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), 184 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), 185 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), 186 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), 187 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), 188 PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"), 189 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), 190 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), 191 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), 192 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), 193 "mii", "mii_err"), 194 }; 195 196 const struct armada_37xx_pin_data armada_37xx_pin_nb = { 197 .nr_pins = 36, 198 .name = "GPIO1", 199 .groups = armada_37xx_nb_groups, 200 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups), 201 }; 202 203 const struct armada_37xx_pin_data armada_37xx_pin_sb = { 204 .nr_pins = 30, 205 .name = "GPIO2", 206 .groups = armada_37xx_sb_groups, 207 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups), 208 }; 209 210 static inline void armada_37xx_update_reg(unsigned int *reg, 211 unsigned int *offset) 212 { 213 /* We never have more than 2 registers */ 214 if (*offset >= GPIO_PER_REG) { 215 *offset -= GPIO_PER_REG; 216 *reg += sizeof(u32); 217 } 218 } 219 220 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp, 221 const char *func) 222 { 223 int f; 224 225 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) 226 if (!strcmp(grp->funcs[f], func)) 227 return f; 228 229 return -ENOTSUPP; 230 } 231 232 static int armada_37xx_pmx_get_groups_count(struct udevice *dev) 233 { 234 struct armada_37xx_pinctrl *info = dev_get_priv(dev); 235 236 return info->ngroups; 237 } 238 239 static const char *armada_37xx_pmx_dummy_name = "_dummy"; 240 241 static const char *armada_37xx_pmx_get_group_name(struct udevice *dev, 242 unsigned selector) 243 { 244 struct armada_37xx_pinctrl *info = dev_get_priv(dev); 245 246 if (!info->groups[selector].name) 247 return armada_37xx_pmx_dummy_name; 248 249 return info->groups[selector].name; 250 } 251 252 static int armada_37xx_pmx_get_funcs_count(struct udevice *dev) 253 { 254 struct armada_37xx_pinctrl *info = dev_get_priv(dev); 255 256 return info->nfuncs; 257 } 258 259 static const char *armada_37xx_pmx_get_func_name(struct udevice *dev, 260 unsigned selector) 261 { 262 struct armada_37xx_pinctrl *info = dev_get_priv(dev); 263 264 return info->funcs[selector].name; 265 } 266 267 static int armada_37xx_pmx_set_by_name(struct udevice *dev, 268 const char *name, 269 struct armada_37xx_pin_group *grp) 270 { 271 struct armada_37xx_pinctrl *info = dev_get_priv(dev); 272 unsigned int reg = SELECTION; 273 unsigned int mask = grp->reg_mask; 274 int func, val; 275 276 dev_dbg(info->dev, "enable function %s group %s\n", 277 name, grp->name); 278 279 func = armada_37xx_get_func_reg(grp, name); 280 281 if (func < 0) 282 return func; 283 284 val = grp->val[func]; 285 286 clrsetbits_le32(info->base + reg, mask, val); 287 288 return 0; 289 } 290 291 static int armada_37xx_pmx_group_set(struct udevice *dev, 292 unsigned group_selector, 293 unsigned func_selector) 294 { 295 struct armada_37xx_pinctrl *info = dev_get_priv(dev); 296 struct armada_37xx_pin_group *grp = &info->groups[group_selector]; 297 const char *name = info->funcs[func_selector].name; 298 299 return armada_37xx_pmx_set_by_name(dev, name, grp); 300 } 301 302 /** 303 * armada_37xx_add_function() - Add a new function to the list 304 * @funcs: array of function to add the new one 305 * @funcsize: size of the remaining space for the function 306 * @name: name of the function to add 307 * 308 * If it is a new function then create it by adding its name else 309 * increment the number of group associated to this function. 310 */ 311 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, 312 int *funcsize, const char *name) 313 { 314 int i = 0; 315 316 if (*funcsize <= 0) 317 return -EOVERFLOW; 318 319 while (funcs->ngroups) { 320 /* function already there */ 321 if (strcmp(funcs->name, name) == 0) { 322 funcs->ngroups++; 323 324 return -EEXIST; 325 } 326 funcs++; 327 i++; 328 } 329 330 /* append new unique function */ 331 funcs->name = name; 332 funcs->ngroups = 1; 333 (*funcsize)--; 334 335 return 0; 336 } 337 338 /** 339 * armada_37xx_fill_group() - complete the group array 340 * @info: info driver instance 341 * 342 * Based on the data available from the armada_37xx_pin_group array 343 * completes the last member of the struct for each function: the list 344 * of the groups associated to this function. 345 * 346 */ 347 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) 348 { 349 int n, num = 0, funcsize = info->data->nr_pins; 350 351 for (n = 0; n < info->ngroups; n++) { 352 struct armada_37xx_pin_group *grp = &info->groups[n]; 353 int i, j, f; 354 355 grp->pins = devm_kzalloc(info->dev, 356 (grp->npins + grp->extra_npins) * 357 sizeof(*grp->pins), GFP_KERNEL); 358 if (!grp->pins) 359 return -ENOMEM; 360 361 for (i = 0; i < grp->npins; i++) 362 grp->pins[i] = grp->start_pin + i; 363 364 for (j = 0; j < grp->extra_npins; j++) 365 grp->pins[i+j] = grp->extra_pin + j; 366 367 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) { 368 int ret; 369 /* check for unique functions and count groups */ 370 ret = armada_37xx_add_function(info->funcs, &funcsize, 371 grp->funcs[f]); 372 if (ret == -EOVERFLOW) 373 dev_err(info->dev, 374 "More functions than pins(%d)\n", 375 info->data->nr_pins); 376 if (ret < 0) 377 continue; 378 num++; 379 } 380 } 381 382 info->nfuncs = num; 383 384 return 0; 385 } 386 387 /** 388 * armada_37xx_fill_funcs() - complete the funcs array 389 * @info: info driver instance 390 * 391 * Based on the data available from the armada_37xx_pin_group array 392 * completes the last two member of the struct for each group: 393 * - the list of the pins included in the group 394 * - the list of pinmux functions that can be selected for this group 395 * 396 */ 397 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) 398 { 399 struct armada_37xx_pmx_func *funcs = info->funcs; 400 int n; 401 402 for (n = 0; n < info->nfuncs; n++) { 403 const char *name = funcs[n].name; 404 const char **groups; 405 int g; 406 407 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups * 408 sizeof(*(funcs[n].groups)), 409 GFP_KERNEL); 410 if (!funcs[n].groups) 411 return -ENOMEM; 412 413 groups = funcs[n].groups; 414 415 for (g = 0; g < info->ngroups; g++) { 416 struct armada_37xx_pin_group *gp = &info->groups[g]; 417 int f; 418 419 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) { 420 if (strcmp(gp->funcs[f], name) == 0) { 421 *groups = gp->name; 422 groups++; 423 } 424 } 425 } 426 } 427 return 0; 428 } 429 430 static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset) 431 { 432 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent); 433 unsigned int reg = INPUT_VAL; 434 unsigned int val, mask; 435 436 armada_37xx_update_reg(®, &offset); 437 mask = BIT(offset); 438 439 val = readl(info->base + reg); 440 441 return (val & mask) != 0; 442 } 443 444 static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset, 445 int value) 446 { 447 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent); 448 unsigned int reg = OUTPUT_VAL; 449 unsigned int mask, val; 450 451 armada_37xx_update_reg(®, &offset); 452 mask = BIT(offset); 453 val = value ? mask : 0; 454 455 clrsetbits_le32(info->base + reg, mask, val); 456 457 return 0; 458 } 459 460 static int armada_37xx_gpio_get_direction(struct udevice *dev, 461 unsigned int offset) 462 { 463 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent); 464 unsigned int reg = OUTPUT_EN; 465 unsigned int val, mask; 466 467 armada_37xx_update_reg(®, &offset); 468 mask = BIT(offset); 469 val = readl(info->base + reg); 470 471 if (val & mask) 472 return GPIOF_OUTPUT; 473 else 474 return GPIOF_INPUT; 475 } 476 477 static int armada_37xx_gpio_direction_input(struct udevice *dev, 478 unsigned int offset) 479 { 480 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent); 481 unsigned int reg = OUTPUT_EN; 482 unsigned int mask; 483 484 armada_37xx_update_reg(®, &offset); 485 mask = BIT(offset); 486 487 clrbits_le32(info->base + reg, mask); 488 489 return 0; 490 } 491 492 static int armada_37xx_gpio_direction_output(struct udevice *dev, 493 unsigned int offset, int value) 494 { 495 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent); 496 unsigned int reg = OUTPUT_EN; 497 unsigned int mask; 498 499 armada_37xx_update_reg(®, &offset); 500 mask = BIT(offset); 501 502 setbits_le32(info->base + reg, mask); 503 504 /* And set the requested value */ 505 return armada_37xx_gpio_set(dev, offset, value); 506 } 507 508 static int armada_37xx_gpio_probe(struct udevice *dev) 509 { 510 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent); 511 struct gpio_dev_priv *uc_priv; 512 513 uc_priv = dev_get_uclass_priv(dev); 514 uc_priv->bank_name = info->data->name; 515 uc_priv->gpio_count = info->data->nr_pins; 516 517 return 0; 518 } 519 520 static const struct dm_gpio_ops armada_37xx_gpio_ops = { 521 .set_value = armada_37xx_gpio_set, 522 .get_value = armada_37xx_gpio_get, 523 .get_function = armada_37xx_gpio_get_direction, 524 .direction_input = armada_37xx_gpio_direction_input, 525 .direction_output = armada_37xx_gpio_direction_output, 526 }; 527 528 static struct driver armada_37xx_gpio_driver = { 529 .name = "armada-37xx-gpio", 530 .id = UCLASS_GPIO, 531 .probe = armada_37xx_gpio_probe, 532 .ops = &armada_37xx_gpio_ops, 533 }; 534 535 static int armada_37xx_gpiochip_register(struct udevice *parent, 536 struct armada_37xx_pinctrl *info) 537 { 538 const void *blob = gd->fdt_blob; 539 int node = dev_of_offset(parent); 540 struct uclass_driver *drv; 541 struct udevice *dev; 542 int ret = -ENODEV; 543 int subnode; 544 char *name; 545 546 /* Lookup GPIO driver */ 547 drv = lists_uclass_lookup(UCLASS_GPIO); 548 if (!drv) { 549 puts("Cannot find GPIO driver\n"); 550 return -ENOENT; 551 } 552 553 fdt_for_each_subnode(subnode, blob, node) { 554 if (fdtdec_get_bool(blob, subnode, "gpio-controller")) { 555 ret = 0; 556 break; 557 } 558 }; 559 if (ret) 560 return ret; 561 562 name = calloc(1, 32); 563 sprintf(name, "armada-37xx-gpio"); 564 565 /* Create child device UCLASS_GPIO and bind it */ 566 device_bind(parent, &armada_37xx_gpio_driver, name, NULL, subnode, 567 &dev); 568 dev_set_of_offset(dev, subnode); 569 570 return 0; 571 } 572 573 const struct pinctrl_ops armada_37xx_pinctrl_ops = { 574 .get_groups_count = armada_37xx_pmx_get_groups_count, 575 .get_group_name = armada_37xx_pmx_get_group_name, 576 .get_functions_count = armada_37xx_pmx_get_funcs_count, 577 .get_function_name = armada_37xx_pmx_get_func_name, 578 .pinmux_group_set = armada_37xx_pmx_group_set, 579 .set_state = pinctrl_generic_set_state, 580 }; 581 582 int armada_37xx_pinctrl_probe(struct udevice *dev) 583 { 584 struct armada_37xx_pinctrl *info = dev_get_priv(dev); 585 const struct armada_37xx_pin_data *pin_data; 586 int ret; 587 588 info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev); 589 pin_data = info->data; 590 591 info->base = (void __iomem *)devfdt_get_addr(dev); 592 if (!info->base) { 593 pr_err("unable to find regmap\n"); 594 return -ENODEV; 595 } 596 597 info->groups = pin_data->groups; 598 info->ngroups = pin_data->ngroups; 599 600 /* 601 * we allocate functions for number of pins and hope there are 602 * fewer unique functions than pins available 603 */ 604 info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins * 605 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL); 606 if (!info->funcs) 607 return -ENOMEM; 608 609 610 ret = armada_37xx_fill_group(info); 611 if (ret) 612 return ret; 613 614 ret = armada_37xx_fill_func(info); 615 if (ret) 616 return ret; 617 618 ret = armada_37xx_gpiochip_register(dev, info); 619 if (ret) 620 return ret; 621 622 return 0; 623 } 624 625 static const struct udevice_id armada_37xx_pinctrl_of_match[] = { 626 { 627 .compatible = "marvell,armada3710-sb-pinctrl", 628 .data = (ulong)&armada_37xx_pin_sb, 629 }, 630 { 631 .compatible = "marvell,armada3710-nb-pinctrl", 632 .data = (ulong)&armada_37xx_pin_nb, 633 }, 634 { /* sentinel */ } 635 }; 636 637 U_BOOT_DRIVER(armada_37xx_pinctrl) = { 638 .name = "armada-37xx-pinctrl", 639 .id = UCLASS_PINCTRL, 640 .of_match = of_match_ptr(armada_37xx_pinctrl_of_match), 641 .probe = armada_37xx_pinctrl_probe, 642 .priv_auto_alloc_size = sizeof(struct armada_37xx_pinctrl), 643 .ops = &armada_37xx_pinctrl_ops, 644 }; 645