1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
4  */
5 
6 #include <common.h>
7 #include <dm.h>
8 #include <dm/device-internal.h>
9 #include <dm/lists.h>
10 #include <dm/pinctrl.h>
11 #include <fdt_support.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/sizes.h>
15 #include <asm/gpio.h>
16 
17 #include "pinctrl-meson.h"
18 
19 DECLARE_GLOBAL_DATA_PTR;
20 
21 static const char *meson_pinctrl_dummy_name = "_dummy";
22 
23 static int meson_pinctrl_get_groups_count(struct udevice *dev)
24 {
25 	struct meson_pinctrl *priv = dev_get_priv(dev);
26 
27 	return priv->data->num_groups;
28 }
29 
30 static const char *meson_pinctrl_get_group_name(struct udevice *dev,
31 						unsigned selector)
32 {
33 	struct meson_pinctrl *priv = dev_get_priv(dev);
34 
35 	if (!priv->data->groups[selector].name)
36 		return meson_pinctrl_dummy_name;
37 
38 	return priv->data->groups[selector].name;
39 }
40 
41 static int meson_pinmux_get_functions_count(struct udevice *dev)
42 {
43 	struct meson_pinctrl *priv = dev_get_priv(dev);
44 
45 	return priv->data->num_funcs;
46 }
47 
48 static const char *meson_pinmux_get_function_name(struct udevice *dev,
49 						  unsigned selector)
50 {
51 	struct meson_pinctrl *priv = dev_get_priv(dev);
52 
53 	return priv->data->funcs[selector].name;
54 }
55 
56 static void meson_pinmux_disable_other_groups(struct meson_pinctrl *priv,
57 					      unsigned int pin, int sel_group)
58 {
59 	struct meson_pmx_group *group;
60 	void __iomem *addr;
61 	int i, j;
62 
63 	for (i = 0; i < priv->data->num_groups; i++) {
64 		group = &priv->data->groups[i];
65 		if (group->is_gpio || i == sel_group)
66 			continue;
67 
68 		for (j = 0; j < group->num_pins; j++) {
69 			if (group->pins[j] == pin) {
70 				/* We have found a group using the pin */
71 				debug("pinmux: disabling %s\n", group->name);
72 				addr = priv->reg_mux + group->reg * 4;
73 				writel(readl(addr) & ~BIT(group->bit), addr);
74 			}
75 		}
76 	}
77 }
78 
79 static int meson_pinmux_group_set(struct udevice *dev,
80 				  unsigned group_selector,
81 				  unsigned func_selector)
82 {
83 	struct meson_pinctrl *priv = dev_get_priv(dev);
84 	const struct meson_pmx_group *group;
85 	const struct meson_pmx_func *func;
86 	void __iomem *addr;
87 	int i;
88 
89 	group = &priv->data->groups[group_selector];
90 	func = &priv->data->funcs[func_selector];
91 
92 	debug("pinmux: set group %s func %s\n", group->name, func->name);
93 
94 	/*
95 	 * Disable groups using the same pins.
96 	 * The selected group is not disabled to avoid glitches.
97 	 */
98 	for (i = 0; i < group->num_pins; i++) {
99 		meson_pinmux_disable_other_groups(priv,
100 						  group->pins[i],
101 						  group_selector);
102 	}
103 
104 	/* Function 0 (GPIO) doesn't need any additional setting */
105 	if (func_selector) {
106 		addr = priv->reg_mux + group->reg * 4;
107 		writel(readl(addr) | BIT(group->bit), addr);
108 	}
109 
110 	return 0;
111 }
112 
113 const struct pinctrl_ops meson_pinctrl_ops = {
114 	.get_groups_count = meson_pinctrl_get_groups_count,
115 	.get_group_name = meson_pinctrl_get_group_name,
116 	.get_functions_count = meson_pinmux_get_functions_count,
117 	.get_function_name = meson_pinmux_get_function_name,
118 	.pinmux_group_set = meson_pinmux_group_set,
119 	.set_state = pinctrl_generic_set_state,
120 };
121 
122 static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
123 				       enum meson_reg_type reg_type,
124 				       unsigned int *reg, unsigned int *bit)
125 {
126 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
127 	struct meson_bank *bank = NULL;
128 	struct meson_reg_desc *desc;
129 	unsigned int pin;
130 	int i;
131 
132 	pin = priv->data->pin_base + offset;
133 
134 	for (i = 0; i < priv->data->num_banks; i++) {
135 		if (pin >= priv->data->banks[i].first &&
136 		    pin <= priv->data->banks[i].last) {
137 			bank = &priv->data->banks[i];
138 			break;
139 		}
140 	}
141 
142 	if (!bank)
143 		return -EINVAL;
144 
145 	desc = &bank->regs[reg_type];
146 	*reg = desc->reg * 4;
147 	*bit = desc->bit + pin - bank->first;
148 
149 	return 0;
150 }
151 
152 static int meson_gpio_get(struct udevice *dev, unsigned int offset)
153 {
154 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
155 	unsigned int reg, bit;
156 	int ret;
157 
158 	ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_IN, &reg, &bit);
159 	if (ret)
160 		return ret;
161 
162 	return !!(readl(priv->reg_gpio + reg) & BIT(bit));
163 }
164 
165 static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
166 {
167 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
168 	unsigned int reg, bit;
169 	int ret;
170 
171 	ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, &reg, &bit);
172 	if (ret)
173 		return ret;
174 
175 	clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
176 
177 	return 0;
178 }
179 
180 static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
181 {
182 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
183 	unsigned int reg, bit, val;
184 	int ret;
185 
186 	ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, &reg, &bit);
187 	if (ret)
188 		return ret;
189 
190 	val = readl(priv->reg_gpio + reg);
191 
192 	return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
193 }
194 
195 static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
196 {
197 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
198 	unsigned int reg, bit;
199 	int ret;
200 
201 	ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, &reg, &bit);
202 	if (ret)
203 		return ret;
204 
205 	clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 1);
206 
207 	return 0;
208 }
209 
210 static int meson_gpio_direction_output(struct udevice *dev,
211 				       unsigned int offset, int value)
212 {
213 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
214 	unsigned int reg, bit;
215 	int ret;
216 
217 	ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, &reg, &bit);
218 	if (ret)
219 		return ret;
220 
221 	clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 0);
222 
223 	ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, &reg, &bit);
224 	if (ret)
225 		return ret;
226 
227 	clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
228 
229 	return 0;
230 }
231 
232 static int meson_gpio_probe(struct udevice *dev)
233 {
234 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
235 	struct gpio_dev_priv *uc_priv;
236 
237 	uc_priv = dev_get_uclass_priv(dev);
238 	uc_priv->bank_name = priv->data->name;
239 	uc_priv->gpio_count = priv->data->num_pins;
240 
241 	return 0;
242 }
243 
244 static const struct dm_gpio_ops meson_gpio_ops = {
245 	.set_value = meson_gpio_set,
246 	.get_value = meson_gpio_get,
247 	.get_function = meson_gpio_get_direction,
248 	.direction_input = meson_gpio_direction_input,
249 	.direction_output = meson_gpio_direction_output,
250 };
251 
252 static struct driver meson_gpio_driver = {
253 	.name	= "meson-gpio",
254 	.id	= UCLASS_GPIO,
255 	.probe	= meson_gpio_probe,
256 	.ops	= &meson_gpio_ops,
257 };
258 
259 static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
260 {
261 	int index, len = 0;
262 	const fdt32_t *reg;
263 
264 	index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", name);
265 	if (index < 0)
266 		return FDT_ADDR_T_NONE;
267 
268 	reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
269 	if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns))))
270 		return FDT_ADDR_T_NONE;
271 
272 	reg += index * (na + ns);
273 
274 	return fdt_translate_address((void *)gd->fdt_blob, offset, reg);
275 }
276 
277 int meson_pinctrl_probe(struct udevice *dev)
278 {
279 	struct meson_pinctrl *priv = dev_get_priv(dev);
280 	struct uclass_driver *drv;
281 	struct udevice *gpio_dev;
282 	fdt_addr_t addr;
283 	int node, gpio = -1, len;
284 	int na, ns;
285 	char *name;
286 
287 	na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
288 	if (na < 1) {
289 		debug("bad #address-cells\n");
290 		return -EINVAL;
291 	}
292 
293 	ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
294 	if (ns < 1) {
295 		debug("bad #size-cells\n");
296 		return -EINVAL;
297 	}
298 
299 	fdt_for_each_subnode(node, gd->fdt_blob, dev_of_offset(dev)) {
300 		if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
301 			gpio = node;
302 			break;
303 		}
304 	}
305 
306 	if (!gpio) {
307 		debug("gpio node not found\n");
308 		return -EINVAL;
309 	}
310 
311 	addr = parse_address(gpio, "mux", na, ns);
312 	if (addr == FDT_ADDR_T_NONE) {
313 		debug("mux address not found\n");
314 		return -EINVAL;
315 	}
316 	priv->reg_mux = (void __iomem *)addr;
317 
318 	addr = parse_address(gpio, "gpio", na, ns);
319 	if (addr == FDT_ADDR_T_NONE) {
320 		debug("gpio address not found\n");
321 		return -EINVAL;
322 	}
323 	priv->reg_gpio = (void __iomem *)addr;
324 	priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
325 
326 	/* Lookup GPIO driver */
327 	drv = lists_uclass_lookup(UCLASS_GPIO);
328 	if (!drv) {
329 		puts("Cannot find GPIO driver\n");
330 		return -ENOENT;
331 	}
332 
333 	name = calloc(1, 32);
334 	sprintf(name, "meson-gpio");
335 
336 	/* Create child device UCLASS_GPIO and bind it */
337 	device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev);
338 	dev_set_of_offset(gpio_dev, gpio);
339 
340 	return 0;
341 }
342