1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 MediaTek Inc.
4  * Author: Ryder Lee <ryder.lee@mediatek.com>
5  */
6 
7 #include <common.h>
8 #include <dm.h>
9 #include <dm/device-internal.h>
10 #include <dm/lists.h>
11 #include <dm/pinctrl.h>
12 #include <asm/io.h>
13 #include <asm-generic/gpio.h>
14 
15 #include "pinctrl-mtk-common.h"
16 
17 /**
18  * struct mtk_drive_desc - the structure that holds the information
19  *			    of the driving current
20  * @min:	the minimum current of this group
21  * @max:	the maximum current of this group
22  * @step:	the step current of this group
23  * @scal:	the weight factor
24  *
25  * formula: output = ((input) / step - 1) * scal
26  */
27 struct mtk_drive_desc {
28 	u8 min;
29 	u8 max;
30 	u8 step;
31 	u8 scal;
32 };
33 
34 /* The groups of drive strength */
35 static const struct mtk_drive_desc mtk_drive[] = {
36 	[DRV_GRP0] = { 4, 16, 4, 1 },
37 	[DRV_GRP1] = { 4, 16, 4, 2 },
38 	[DRV_GRP2] = { 2, 8, 2, 1 },
39 	[DRV_GRP3] = { 2, 8, 2, 2 },
40 	[DRV_GRP4] = { 2, 16, 2, 1 },
41 };
42 
43 static const char *mtk_pinctrl_dummy_name = "_dummy";
44 
45 static void mtk_w32(struct udevice *dev, u32 reg, u32 val)
46 {
47 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
48 
49 	__raw_writel(val, priv->base + reg);
50 }
51 
52 static u32 mtk_r32(struct udevice *dev, u32 reg)
53 {
54 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
55 
56 	return __raw_readl(priv->base + reg);
57 }
58 
59 static inline int get_count_order(unsigned int count)
60 {
61 	int order;
62 
63 	order = fls(count) - 1;
64 	if (count & (count - 1))
65 		order++;
66 	return order;
67 }
68 
69 void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set)
70 {
71 	u32 val;
72 
73 	val = mtk_r32(dev, reg);
74 	val &= ~mask;
75 	val |= set;
76 	mtk_w32(dev, reg, val);
77 }
78 
79 static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin,
80 				   const struct mtk_pin_reg_calc *rc,
81 				   struct mtk_pin_field *pfd)
82 {
83 	const struct mtk_pin_field_calc *c, *e;
84 	u32 bits;
85 
86 	c = rc->range;
87 	e = c + rc->nranges;
88 
89 	while (c < e) {
90 		if (pin >= c->s_pin && pin <= c->e_pin)
91 			break;
92 		c++;
93 	}
94 
95 	if (c >= e)
96 		return -EINVAL;
97 
98 	/* Calculated bits as the overall offset the pin is located at,
99 	 * if c->fixed is held, that determines the all the pins in the
100 	 * range use the same field with the s_pin.
101 	 */
102 	bits = c->fixed ? c->s_bit : c->s_bit + (pin - c->s_pin) * (c->x_bits);
103 
104 	/* Fill pfd from bits. For example 32-bit register applied is assumed
105 	 * when c->sz_reg is equal to 32.
106 	 */
107 	pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
108 	pfd->bitpos = bits % c->sz_reg;
109 	pfd->mask = (1 << c->x_bits) - 1;
110 
111 	/* pfd->next is used for indicating that bit wrapping-around happens
112 	 * which requires the manipulation for bit 0 starting in the next
113 	 * register to form the complete field read/write.
114 	 */
115 	pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
116 
117 	return 0;
118 }
119 
120 static int mtk_hw_pin_field_get(struct udevice *dev, int pin,
121 				int field, struct mtk_pin_field *pfd)
122 {
123 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
124 	const struct mtk_pin_reg_calc *rc;
125 
126 	if (field < 0 || field >= PINCTRL_PIN_REG_MAX)
127 		return -EINVAL;
128 
129 	if (priv->soc->reg_cal && priv->soc->reg_cal[field].range)
130 		rc = &priv->soc->reg_cal[field];
131 	else
132 		return -EINVAL;
133 
134 	return mtk_hw_pin_field_lookup(dev, pin, rc, pfd);
135 }
136 
137 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
138 {
139 	*l = 32 - pf->bitpos;
140 	*h = get_count_order(pf->mask) - *l;
141 }
142 
143 static void mtk_hw_write_cross_field(struct udevice *dev,
144 				     struct mtk_pin_field *pf, int value)
145 {
146 	int nbits_l, nbits_h;
147 
148 	mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
149 
150 	mtk_rmw(dev, pf->offset, pf->mask << pf->bitpos,
151 		(value & pf->mask) << pf->bitpos);
152 
153 	mtk_rmw(dev, pf->offset + pf->next, BIT(nbits_h) - 1,
154 		(value & pf->mask) >> nbits_l);
155 }
156 
157 static void mtk_hw_read_cross_field(struct udevice *dev,
158 				    struct mtk_pin_field *pf, int *value)
159 {
160 	int nbits_l, nbits_h, h, l;
161 
162 	mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
163 
164 	l  = (mtk_r32(dev, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
165 	h  = (mtk_r32(dev, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
166 
167 	*value = (h << nbits_l) | l;
168 }
169 
170 static int mtk_hw_set_value(struct udevice *dev, int pin, int field,
171 			    int value)
172 {
173 	struct mtk_pin_field pf;
174 	int err;
175 
176 	err = mtk_hw_pin_field_get(dev, pin, field, &pf);
177 	if (err)
178 		return err;
179 
180 	if (!pf.next)
181 		mtk_rmw(dev, pf.offset, pf.mask << pf.bitpos,
182 			(value & pf.mask) << pf.bitpos);
183 	else
184 		mtk_hw_write_cross_field(dev, &pf, value);
185 
186 	return 0;
187 }
188 
189 static int mtk_hw_get_value(struct udevice *dev, int pin, int field,
190 			    int *value)
191 {
192 	struct mtk_pin_field pf;
193 	int err;
194 
195 	err = mtk_hw_pin_field_get(dev, pin, field, &pf);
196 	if (err)
197 		return err;
198 
199 	if (!pf.next)
200 		*value = (mtk_r32(dev, pf.offset) >> pf.bitpos) & pf.mask;
201 	else
202 		mtk_hw_read_cross_field(dev, &pf, value);
203 
204 	return 0;
205 }
206 
207 static int mtk_get_groups_count(struct udevice *dev)
208 {
209 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
210 
211 	return priv->soc->ngrps;
212 }
213 
214 static const char *mtk_get_pin_name(struct udevice *dev,
215 				    unsigned int selector)
216 {
217 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
218 
219 	if (!priv->soc->grps[selector].name)
220 		return mtk_pinctrl_dummy_name;
221 
222 	return priv->soc->pins[selector].name;
223 }
224 
225 static int mtk_get_pins_count(struct udevice *dev)
226 {
227 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
228 
229 	return priv->soc->npins;
230 }
231 
232 static const char *mtk_get_group_name(struct udevice *dev,
233 				      unsigned int selector)
234 {
235 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
236 
237 	if (!priv->soc->grps[selector].name)
238 		return mtk_pinctrl_dummy_name;
239 
240 	return priv->soc->grps[selector].name;
241 }
242 
243 static int mtk_get_functions_count(struct udevice *dev)
244 {
245 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
246 
247 	return priv->soc->nfuncs;
248 }
249 
250 static const char *mtk_get_function_name(struct udevice *dev,
251 					 unsigned int selector)
252 {
253 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
254 
255 	if (!priv->soc->funcs[selector].name)
256 		return mtk_pinctrl_dummy_name;
257 
258 	return priv->soc->funcs[selector].name;
259 }
260 
261 static int mtk_pinmux_group_set(struct udevice *dev,
262 				unsigned int group_selector,
263 				unsigned int func_selector)
264 {
265 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
266 	const struct mtk_group_desc *grp =
267 			&priv->soc->grps[group_selector];
268 	int i;
269 
270 	for (i = 0; i < grp->num_pins; i++) {
271 		int *pin_modes = grp->data;
272 
273 		mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
274 				 pin_modes[i]);
275 	}
276 
277 	return 0;
278 }
279 
280 #if CONFIG_IS_ENABLED(PINCONF)
281 static const struct pinconf_param mtk_conf_params[] = {
282 	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
283 	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
284 	{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
285 	{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
286 	{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
287 	{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
288 	{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
289 	{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
290 	{ "output-high", PIN_CONFIG_OUTPUT, 1, },
291 	{ "output-low", PIN_CONFIG_OUTPUT, 0, },
292 	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
293 };
294 
295 int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
296 {
297 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
298 	const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
299 	const struct mtk_drive_desc *tb;
300 	int err = -ENOTSUPP;
301 
302 	tb = &mtk_drive[desc->drv_n];
303 	/* 4mA when (e8, e4) = (0, 0)
304 	 * 8mA when (e8, e4) = (0, 1)
305 	 * 12mA when (e8, e4) = (1, 0)
306 	 * 16mA when (e8, e4) = (1, 1)
307 	 */
308 	if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
309 		arg = (arg / tb->step - 1) * tb->scal;
310 
311 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg);
312 		if (err)
313 			return err;
314 	}
315 
316 	return 0;
317 }
318 
319 static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
320 			   unsigned int param, unsigned int arg)
321 {
322 	int err = 0;
323 
324 	switch (param) {
325 	case PIN_CONFIG_BIAS_DISABLE:
326 	case PIN_CONFIG_BIAS_PULL_UP:
327 	case PIN_CONFIG_BIAS_PULL_DOWN:
328 		arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
329 			(param == PIN_CONFIG_BIAS_PULL_UP) ? 3 : 2;
330 
331 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
332 				       arg & 1);
333 		if (err)
334 			goto err;
335 
336 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN,
337 				       !!(arg & 2));
338 		if (err)
339 			goto err;
340 		break;
341 	case PIN_CONFIG_OUTPUT_ENABLE:
342 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, 0);
343 		if (err)
344 			goto err;
345 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
346 		if (err)
347 			goto err;
348 		break;
349 	case PIN_CONFIG_INPUT_ENABLE:
350 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
351 		if (err)
352 			goto err;
353 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
354 		if (err)
355 			goto err;
356 		break;
357 	case PIN_CONFIG_OUTPUT:
358 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
359 		if (err)
360 			goto err;
361 
362 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DO, arg);
363 		if (err)
364 			goto err;
365 		break;
366 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
367 		/* arg = 1: Input mode & SMT enable ;
368 		 * arg = 0: Output mode & SMT disable
369 		 */
370 		arg = arg ? 2 : 1;
371 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR,
372 				       arg & 1);
373 		if (err)
374 			goto err;
375 
376 		err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT,
377 				       !!(arg & 2));
378 		if (err)
379 			goto err;
380 		break;
381 	case PIN_CONFIG_DRIVE_STRENGTH:
382 		err = mtk_pinconf_drive_set(dev, pin, arg);
383 		if (err)
384 			goto err;
385 		break;
386 
387 	default:
388 		err = -ENOTSUPP;
389 	}
390 
391 err:
392 
393 	return err;
394 }
395 
396 static int mtk_pinconf_group_set(struct udevice *dev,
397 				 unsigned int group_selector,
398 				 unsigned int param, unsigned int arg)
399 {
400 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
401 	const struct mtk_group_desc *grp =
402 			&priv->soc->grps[group_selector];
403 	int i, ret;
404 
405 	for (i = 0; i < grp->num_pins; i++) {
406 		ret = mtk_pinconf_set(dev, grp->pins[i], param, arg);
407 		if (ret)
408 			return ret;
409 	}
410 
411 	return 0;
412 }
413 #endif
414 
415 const struct pinctrl_ops mtk_pinctrl_ops = {
416 	.get_pins_count = mtk_get_pins_count,
417 	.get_pin_name = mtk_get_pin_name,
418 	.get_groups_count = mtk_get_groups_count,
419 	.get_group_name = mtk_get_group_name,
420 	.get_functions_count = mtk_get_functions_count,
421 	.get_function_name = mtk_get_function_name,
422 	.pinmux_group_set = mtk_pinmux_group_set,
423 #if CONFIG_IS_ENABLED(PINCONF)
424 	.pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
425 	.pinconf_params = mtk_conf_params,
426 	.pinconf_set = mtk_pinconf_set,
427 	.pinconf_group_set = mtk_pinconf_group_set,
428 #endif
429 	.set_state = pinctrl_generic_set_state,
430 };
431 
432 static int mtk_gpio_get(struct udevice *dev, unsigned int off)
433 {
434 	int val, err;
435 
436 	err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DI, &val);
437 	if (err)
438 		return err;
439 
440 	return !!val;
441 }
442 
443 static int mtk_gpio_set(struct udevice *dev, unsigned int off, int val)
444 {
445 	return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DO, !!val);
446 }
447 
448 static int mtk_gpio_get_direction(struct udevice *dev, unsigned int off)
449 {
450 	int val, err;
451 
452 	err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DIR, &val);
453 	if (err)
454 		return err;
455 
456 	return val ? GPIOF_OUTPUT : GPIOF_INPUT;
457 }
458 
459 static int mtk_gpio_direction_input(struct udevice *dev, unsigned int off)
460 {
461 	return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 0);
462 }
463 
464 static int mtk_gpio_direction_output(struct udevice *dev,
465 				     unsigned int off, int val)
466 {
467 	mtk_gpio_set(dev, off, val);
468 
469 	/* And set the requested value */
470 	return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 1);
471 }
472 
473 static int mtk_gpio_request(struct udevice *dev, unsigned int off,
474 			    const char *label)
475 {
476 	return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, 0);
477 }
478 
479 static int mtk_gpio_probe(struct udevice *dev)
480 {
481 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
482 	struct gpio_dev_priv *uc_priv;
483 
484 	uc_priv = dev_get_uclass_priv(dev);
485 	uc_priv->bank_name = priv->soc->name;
486 	uc_priv->gpio_count = priv->soc->npins;
487 
488 	return 0;
489 }
490 
491 static const struct dm_gpio_ops mtk_gpio_ops = {
492 	.request = mtk_gpio_request,
493 	.set_value = mtk_gpio_set,
494 	.get_value = mtk_gpio_get,
495 	.get_function = mtk_gpio_get_direction,
496 	.direction_input = mtk_gpio_direction_input,
497 	.direction_output = mtk_gpio_direction_output,
498 };
499 
500 static struct driver mtk_gpio_driver = {
501 	.name = "mediatek_gpio",
502 	.id	= UCLASS_GPIO,
503 	.probe = mtk_gpio_probe,
504 	.ops = &mtk_gpio_ops,
505 };
506 
507 static int mtk_gpiochip_register(struct udevice *parent)
508 {
509 	struct uclass_driver *drv;
510 	struct udevice *dev;
511 	int ret;
512 	ofnode node;
513 
514 	drv = lists_uclass_lookup(UCLASS_GPIO);
515 	if (!drv)
516 		return -ENOENT;
517 
518 	dev_for_each_subnode(node, parent)
519 		if (ofnode_read_bool(node, "gpio-controller")) {
520 			ret = 0;
521 			break;
522 		}
523 
524 	if (ret)
525 		return ret;
526 
527 	ret = device_bind_with_driver_data(parent, &mtk_gpio_driver,
528 					   "mediatek_gpio", 0, node,
529 					   &dev);
530 	if (ret)
531 		return ret;
532 
533 	return 0;
534 }
535 
536 int mtk_pinctrl_common_probe(struct udevice *dev,
537 			     struct mtk_pinctrl_soc *soc)
538 {
539 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
540 	int ret;
541 
542 	priv->base = dev_read_addr_ptr(dev);
543 	if (priv->base == (void *)FDT_ADDR_T_NONE)
544 		return -EINVAL;
545 
546 	priv->soc = soc;
547 
548 	ret = mtk_gpiochip_register(dev);
549 	if (ret)
550 		return ret;
551 
552 	return 0;
553 }
554