1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  */
5 
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <linux/bitops.h>
11 #include <asm/arch/pinctrl.h>
12 #include <asm/arch/scu_ast2600.h>
13 #include <dm/pinctrl.h>
14 #include "pinctrl-aspeed.h"
15 /*
16  * This driver works with very simple configuration that has the same name
17  * for group and function. This way it is compatible with the Linux Kernel
18  * driver.
19  */
20 
21 struct ast2600_pinctrl_priv {
22 	struct ast2600_scu *scu;
23 };
24 
25 static int ast2600_pinctrl_probe(struct udevice *dev)
26 {
27 	struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
28 	struct udevice *clk_dev;
29 	int ret = 0;
30 
31 	/* find SCU base address from clock device */
32 	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
33                                           &clk_dev);
34     if (ret) {
35             debug("clock device not found\n");
36             return ret;
37     }
38 
39 	priv->scu = devfdt_get_addr_ptr(clk_dev);
40 	if (IS_ERR(priv->scu)) {
41 	        debug("%s(): can't get SCU\n", __func__);
42 	        return PTR_ERR(priv->scu);
43 	}
44 
45 	return 0;
46 }
47 
48 static struct aspeed_sig_desc i2c1_link[] = {
49 	{ 0x418, GENMASK(9, 8), 1 },
50 	{ 0x4B8, GENMASK(9, 8), 0 },
51 };
52 
53 static struct aspeed_sig_desc i2c2_link[] = {
54 	{ 0x418, GENMASK(11, 10), 1 },
55 	{ 0x4B8, GENMASK(11, 10), 0 },
56 };
57 
58 static struct aspeed_sig_desc i2c3_link[] = {
59 	{ 0x418, GENMASK(13, 12), 1 },
60 	{ 0x4B8, GENMASK(13, 12), 0 },
61 };
62 
63 static struct aspeed_sig_desc i2c4_link[] = {
64 	{ 0x418, GENMASK(15, 14), 1 },
65 	{ 0x4B8, GENMASK(15, 14), 0 },
66 };
67 
68 static struct aspeed_sig_desc i2c5_link[] = {
69 	{ 0x418, GENMASK(17, 16), 0 },
70 };
71 
72 static struct aspeed_sig_desc i2c6_link[] = {
73 	{ 0x418, GENMASK(19, 18), 0 },
74 };
75 
76 static struct aspeed_sig_desc i2c7_link[] = {
77 	{ 0x418, GENMASK(21, 20), 0 },
78 };
79 
80 static struct aspeed_sig_desc i2c8_link[] = {
81 	{ 0x418, GENMASK(23, 22), 0 },
82 };
83 
84 static struct aspeed_sig_desc i2c9_link[] = {
85 	{ 0x418, GENMASK(25, 24), 0 },
86 };
87 
88 static struct aspeed_sig_desc i2c10_link[] = {
89 	{ 0x418, GENMASK(27, 26), 0 },
90 };
91 
92 static struct aspeed_sig_desc i2c11_link[] = {
93 	{ 0x410, GENMASK(1, 0), 1 },
94 	{ 0x4B0, GENMASK(1, 0), 0 },
95 };
96 
97 static struct aspeed_sig_desc i2c12_link[] = {
98 	{ 0x410, GENMASK(3, 2), 1 },
99 	{ 0x4B0, GENMASK(3, 2), 0 },
100 };
101 
102 static struct aspeed_sig_desc i2c13_link[] = {
103 	{ 0x410, GENMASK(5, 4), 1 },
104 	{ 0x4B0, GENMASK(5, 4), 0 },
105 };
106 
107 static struct aspeed_sig_desc i2c14_link[] = {
108 	{ 0x410, GENMASK(7, 6), 1 },
109 	{ 0x4B0, GENMASK(7, 6), 0 },
110 };
111 
112 static struct aspeed_sig_desc i2c15_link[] = {
113 	{ 0x414, GENMASK(29, 28), 1 },
114 	{ 0x4B4, GENMASK(29, 28), 1 },
115 };
116 
117 static struct aspeed_sig_desc i2c16_link[] = {
118 	{ 0x414, GENMASK(31, 30), 1 },
119 	{ 0x4B4, GENMASK(31, 30), 1 },
120 };
121 
122 
123 static struct aspeed_sig_desc mac1_link[] = {
124 	{ 0x410, BIT(4), 0 },
125 #ifndef CONFIG_FPGA_ASPEED
126 	{ 0x470, BIT(4), 1 },
127 #endif
128 };
129 
130 static struct aspeed_sig_desc mac2_link[] = {
131 	{ 0x410, BIT(5), 0	},
132 	{ 0x470, BIT(5), 1 },
133 };
134 
135 static struct aspeed_sig_desc mac3_link[] = {
136 	{ 0x410, BIT(6), 0		},
137 	{ 0x470, BIT(6), 1      	},
138 };
139 
140 static struct aspeed_sig_desc mac4_link[] = {
141 	{ 0x410, BIT(7), 0		},
142 	{ 0x470, BIT(7), 1		},
143 };
144 
145 
146 static struct aspeed_sig_desc rgmii1[] = {
147 #ifndef CONFIG_FPGA_ASPEED
148 	{ 0x400, GENMASK(11, 0), 0 },
149 #endif
150 };
151 
152 static struct aspeed_sig_desc rgmii2[] = {
153 	{ 0x400, GENMASK(23, 12), 0 },
154 };
155 
156 static struct aspeed_sig_desc rgmii3[] = {
157 	{ 0x410, GENMASK(27, 16), 0	},
158 };
159 
160 static struct aspeed_sig_desc rgmii4[] = {
161 	{ 0x410, GENMASK(31, 28), 1	},
162 	{ 0x4b0, GENMASK(31, 28), 0	},
163 	{ 0x474, GENMASK(7, 0), 1	},
164 	{ 0x414, GENMASK(7, 0), 1	},
165 	{ 0x4b4, GENMASK(7, 0), 0	},
166 };
167 
168 static struct aspeed_sig_desc rmii1[] = {
169 	{ 0x400, GENMASK(3, 0), 0	},
170 	{ 0x400, GENMASK(11, 6), 0	},
171 };
172 
173 static struct aspeed_sig_desc rmii2[] = {
174 	{ 0x400, GENMASK(15, 12), 0	},
175 	{ 0x400, GENMASK(23, 18), 0	},
176 };
177 
178 static struct aspeed_sig_desc rmii3[] = {
179 	{ 0x410, GENMASK(27, 22), 0	},
180 	{ 0x410, GENMASK(19, 16), 0	},
181 };
182 
183 static struct aspeed_sig_desc rmii4[] = {
184 	{ 0x410, GENMASK(7, 2), 1	},
185 	{ 0x410, GENMASK(31, 28), 1	},
186 	{ 0x414, GENMASK(7, 2), 1	},
187 	{ 0x4B0, GENMASK(31, 28), 0	},
188 	{ 0x4B4, GENMASK(7, 2), 0	},
189 };
190 
191 static struct aspeed_sig_desc mdio1_link[] = {
192 	{ 0x430, BIT(17) | BIT(16), 0	},
193 };
194 
195 static struct aspeed_sig_desc mdio2_link[] = {
196 	{ 0x470, BIT(13) | BIT(12), 1	},
197 	{ 0x410, BIT(13) | BIT(12), 0	},
198 };
199 
200 static struct aspeed_sig_desc mdio3_link[] = {
201 	{ 0x470, BIT(1) | BIT(0), 1	},
202 	{ 0x410, BIT(1) | BIT(0), 0	},
203 };
204 
205 static struct aspeed_sig_desc mdio4_link[] = {
206 	{ 0x470, BIT(3) | BIT(2), 1	},
207 	{ 0x410, BIT(3) | BIT(2), 0	},
208 };
209 
210 static struct aspeed_sig_desc sdio2_link[] = {
211 	{ 0x414, GENMASK(23, 16), 1	},
212 	{ 0x4B4, GENMASK(23, 16), 0	},
213 	{ 0x450, BIT(1), 0		},
214 };
215 
216 static struct aspeed_sig_desc sdio1_link[] = {
217 	{ 0x414, GENMASK(15, 8), 0	},
218 };
219 
220 //when sdio1 8bits, sdio2 can't use
221 static struct aspeed_sig_desc sdio1_8bit_link[] = {
222 	{ 0x414, GENMASK(15, 8), 0	},
223 	{ 0x4b4, GENMASK(21, 18), 0	},
224 	{ 0x450, BIT(3), 0	},
225 	{ 0x450, BIT(1), 1	},
226 };
227 
228 static struct aspeed_sig_desc emmc_link[] = {
229 	{ 0x400, GENMASK(31, 24), 0 },
230 #if 0	//8bit emmc
231 	{ 0x404, GENMASK(3, 0), 0 },
232 	{ 0x500, BIT(3), 1 },
233 	{ 0x500, BIT(5), 1 },
234 #endif
235 };
236 
237 static struct aspeed_sig_desc fmcquad_link[] = {
238 	{ 0x438, GENMASK(5, 4), 0 },
239 };
240 
241 static struct aspeed_sig_desc spi1_link[] = {
242 	{ 0x438, GENMASK(13, 11), 0 },
243 };
244 
245 static struct aspeed_sig_desc spi1abr_link[] = {
246 	{ 0x438, BIT(9), 0 },
247 };
248 
249 static struct aspeed_sig_desc spi1cs1_link[] = {
250 	{ 0x438, BIT(8), 0 },
251 };
252 
253 static struct aspeed_sig_desc spi1wp_link[] = {
254 	{ 0x438, BIT(10), 0 },
255 };
256 
257 static struct aspeed_sig_desc spi1quad_link[] = {
258 	{ 0x438, GENMASK(15, 14), 0 },
259 };
260 
261 static struct aspeed_sig_desc spi2_link[] = {
262 	{ 0x434, GENMASK(29, 27) | BIT(24), 0 },
263 };
264 
265 static struct aspeed_sig_desc spi2cs1_link[] = {
266 	{ 0x434, BIT(25), 0 },
267 };
268 
269 static struct aspeed_sig_desc spi2cs2_link[] = {
270 	{ 0x434, BIT(26), 0 },
271 };
272 
273 static struct aspeed_sig_desc spi2quad_link[] = {
274 	{ 0x434, GENMASK(31, 30), 0 },
275 };
276 
277 static struct aspeed_sig_desc pcie_rc_reset_link[] = {
278 	{ 0x500, BIT(24), 0 },
279 };
280 
281 static struct aspeed_sig_desc fsi1[] = {
282 	{ 0xd48, GENMASK(21, 20), 0 },
283 };
284 
285 static struct aspeed_sig_desc fsi2[] = {
286 	{ 0xd48, GENMASK(23, 22), 0 },
287 };
288 
289 static const struct aspeed_group_config ast2600_groups[] = {
290 	{ "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
291 	{ "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
292 	{ "MAC3LINK", ARRAY_SIZE(mac3_link), mac3_link },
293 	{ "MAC4LINK", ARRAY_SIZE(mac4_link), mac4_link },
294 	{ "RGMII1", ARRAY_SIZE(rgmii1), rgmii1 },
295 	{ "RGMII2", ARRAY_SIZE(rgmii2), rgmii2 },
296 	{ "RGMII3", ARRAY_SIZE(rgmii3), rgmii3 },
297 	{ "RGMII4", ARRAY_SIZE(rgmii4), rgmii4 },
298 	{ "RMII1", ARRAY_SIZE(rmii1), rmii1 },
299 	{ "RMII2", ARRAY_SIZE(rmii2), rmii2 },
300 	{ "RMII3", ARRAY_SIZE(rmii3), rmii3 },
301 	{ "RMII4", ARRAY_SIZE(rmii4), rmii4 },
302 	{ "MDIO1", ARRAY_SIZE(mdio1_link), mdio1_link },
303 	{ "MDIO2", ARRAY_SIZE(mdio2_link), mdio2_link },
304 	{ "MDIO3", ARRAY_SIZE(mdio3_link), mdio3_link },
305 	{ "MDIO4", ARRAY_SIZE(mdio4_link), mdio4_link },
306 	{ "SD1", ARRAY_SIZE(sdio1_link), sdio1_link },
307 	{ "SD1_8bits", ARRAY_SIZE(sdio1_8bit_link), sdio1_8bit_link },
308 	{ "SD2", ARRAY_SIZE(sdio2_link), sdio2_link },
309 	{ "EMMC", ARRAY_SIZE(emmc_link), emmc_link },
310 	{ "FMCQUAD", ARRAY_SIZE(fmcquad_link), fmcquad_link },
311 	{ "SPI1", ARRAY_SIZE(spi1_link), spi1_link },
312 	{ "SPI1ABR", ARRAY_SIZE(spi1abr_link), spi1abr_link },
313 	{ "SPI1CS1", ARRAY_SIZE(spi1cs1_link), spi1cs1_link },
314 	{ "SPI1WP", ARRAY_SIZE(spi1wp_link), spi1wp_link },
315 	{ "SPI1QUAD", ARRAY_SIZE(spi1quad_link), spi1quad_link },
316 	{ "SPI2", ARRAY_SIZE(spi2_link), spi2_link },
317 	{ "SPI2CS1", ARRAY_SIZE(spi2cs1_link), spi2cs1_link },
318 	{ "SPI2CS2", ARRAY_SIZE(spi2cs2_link), spi2cs2_link },
319 	{ "SPI2QUAD", ARRAY_SIZE(spi2quad_link), spi2quad_link },
320 	{ "I2C1", ARRAY_SIZE(i2c1_link), i2c1_link },
321 	{ "I2C2", ARRAY_SIZE(i2c2_link), i2c2_link },
322 	{ "I2C3", ARRAY_SIZE(i2c3_link), i2c3_link },
323 	{ "I2C4", ARRAY_SIZE(i2c4_link), i2c4_link },
324 	{ "I2C5", ARRAY_SIZE(i2c5_link), i2c5_link },
325 	{ "I2C6", ARRAY_SIZE(i2c6_link), i2c6_link },
326 	{ "I2C7", ARRAY_SIZE(i2c7_link), i2c7_link },
327 	{ "I2C8", ARRAY_SIZE(i2c8_link), i2c8_link },
328 	{ "I2C9", ARRAY_SIZE(i2c9_link), i2c9_link },
329 	{ "I2C10", ARRAY_SIZE(i2c10_link), i2c10_link },
330 	{ "I2C11", ARRAY_SIZE(i2c11_link), i2c11_link },
331 	{ "I2C12", ARRAY_SIZE(i2c12_link), i2c12_link },
332 	{ "I2C13", ARRAY_SIZE(i2c13_link), i2c13_link },
333 	{ "I2C14", ARRAY_SIZE(i2c14_link), i2c14_link },
334 	{ "I2C15", ARRAY_SIZE(i2c15_link), i2c15_link },
335 	{ "I2C16", ARRAY_SIZE(i2c16_link), i2c16_link },
336 	{ "PCIERC", ARRAY_SIZE(pcie_rc_reset_link), pcie_rc_reset_link },
337 	{ "FSI1", ARRAY_SIZE(fsi1), fsi1 },
338 	{ "FSI2", ARRAY_SIZE(fsi2), fsi2 },
339 };
340 
341 static int ast2600_pinctrl_get_groups_count(struct udevice *dev)
342 {
343 	debug("PINCTRL: get_(functions/groups)_count\n");
344 
345 	return ARRAY_SIZE(ast2600_groups);
346 }
347 
348 static const char *ast2600_pinctrl_get_group_name(struct udevice *dev,
349 						  unsigned selector)
350 {
351 	debug("PINCTRL: get_(function/group)_name %u\n", selector);
352 
353 	return ast2600_groups[selector].group_name;
354 }
355 
356 static int ast2600_pinctrl_group_set(struct udevice *dev, unsigned selector,
357 				     unsigned func_selector)
358 {
359 	struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
360 	const struct aspeed_group_config *config;
361 	const struct aspeed_sig_desc *descs;
362 	u32 ctrl_reg = (u32)priv->scu;
363 	u32 i;
364 
365 	debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector);
366 	if (selector >= ARRAY_SIZE(ast2600_groups))
367 		return -EINVAL;
368 
369 	config = &ast2600_groups[selector];
370 	for (i = 0; i < config->ndescs; i++) {
371 		descs = &config->descs[i];
372 		if (descs->clr) {
373 			clrbits_le32((u32)ctrl_reg + descs->offset,
374 				     descs->reg_set);
375 		} else {
376 			setbits_le32((u32)ctrl_reg + descs->offset,
377 				     descs->reg_set);
378 		}
379 	}
380 
381 	return 0;
382 }
383 
384 static struct pinctrl_ops ast2600_pinctrl_ops = {
385 	.set_state = pinctrl_generic_set_state,
386 	.get_groups_count = ast2600_pinctrl_get_groups_count,
387 	.get_group_name = ast2600_pinctrl_get_group_name,
388 	.get_functions_count = ast2600_pinctrl_get_groups_count,
389 	.get_function_name = ast2600_pinctrl_get_group_name,
390 	.pinmux_group_set = ast2600_pinctrl_group_set,
391 };
392 
393 static const struct udevice_id ast2600_pinctrl_ids[] = {
394 	{ .compatible = "aspeed,g6-pinctrl" },
395 	{ }
396 };
397 
398 U_BOOT_DRIVER(pinctrl_aspeed) = {
399 	.name = "aspeed_ast2600_pinctrl",
400 	.id = UCLASS_PINCTRL,
401 	.of_match = ast2600_pinctrl_ids,
402 	.priv_auto_alloc_size = sizeof(struct ast2600_pinctrl_priv),
403 	.ops = &ast2600_pinctrl_ops,
404 	.probe = ast2600_pinctrl_probe,
405 };
406