1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  */
5 
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <linux/bitops.h>
11 #include <asm/arch/pinctrl.h>
12 #include <asm/arch/scu_ast2600.h>
13 #include <dm/pinctrl.h>
14 #include "pinctrl-aspeed.h"
15 /*
16  * This driver works with very simple configuration that has the same name
17  * for group and function. This way it is compatible with the Linux Kernel
18  * driver.
19  */
20 
21 struct ast2600_pinctrl_priv {
22 	struct ast2600_scu *scu;
23 };
24 
25 static int ast2600_pinctrl_probe(struct udevice *dev)
26 {
27 	struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
28 	struct udevice *clk_dev;
29 	int ret = 0;
30 
31 	/* find SCU base address from clock device */
32 	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
33                                           &clk_dev);
34     if (ret) {
35             debug("clock device not found\n");
36             return ret;
37     }
38 
39 	priv->scu = devfdt_get_addr_ptr(clk_dev);
40 	if (IS_ERR(priv->scu)) {
41 	        debug("%s(): can't get SCU\n", __func__);
42 	        return PTR_ERR(priv->scu);
43 	}
44 
45 	return 0;
46 }
47 
48 static struct aspeed_sig_desc i2c1_link[] = {
49 	{ 0x418, GENMASK(9, 8), 1 },
50 	{ 0x4B8, GENMASK(9, 8), 0 },
51 };
52 
53 static struct aspeed_sig_desc i2c2_link[] = {
54 	{ 0x418, GENMASK(11, 10), 1 },
55 	{ 0x4B8, GENMASK(11, 10), 0 },
56 };
57 
58 static struct aspeed_sig_desc i2c3_link[] = {
59 	{ 0x418, GENMASK(13, 12), 1 },
60 	{ 0x4B8, GENMASK(13, 12), 0 },
61 };
62 
63 static struct aspeed_sig_desc i2c4_link[] = {
64 	{ 0x418, GENMASK(15, 14), 1 },
65 	{ 0x4B8, GENMASK(15, 14), 0 },
66 };
67 
68 static struct aspeed_sig_desc i2c5_link[] = {
69 	{ 0x418, GENMASK(17, 16), 0 },
70 };
71 
72 static struct aspeed_sig_desc i2c6_link[] = {
73 	{ 0x418, GENMASK(19, 18), 0 },
74 };
75 
76 static struct aspeed_sig_desc i2c7_link[] = {
77 	{ 0x418, GENMASK(21, 20), 0 },
78 };
79 
80 static struct aspeed_sig_desc i2c8_link[] = {
81 	{ 0x418, GENMASK(23, 22), 0 },
82 };
83 
84 static struct aspeed_sig_desc i2c9_link[] = {
85 	{ 0x418, GENMASK(25, 24), 0 },
86 };
87 
88 static struct aspeed_sig_desc i2c10_link[] = {
89 	{ 0x418, GENMASK(27, 26), 0 },
90 };
91 
92 static struct aspeed_sig_desc i2c11_link[] = {
93 	{ 0x410, GENMASK(1, 0), 1 },
94 	{ 0x4B0, GENMASK(1, 0), 0 },
95 };
96 
97 static struct aspeed_sig_desc i2c12_link[] = {
98 	{ 0x410, GENMASK(3, 2), 1 },
99 	{ 0x4B0, GENMASK(3, 2), 0 },
100 };
101 
102 static struct aspeed_sig_desc i2c13_link[] = {
103 	{ 0x410, GENMASK(5, 4), 1 },
104 	{ 0x4B0, GENMASK(5, 4), 0 },
105 };
106 
107 static struct aspeed_sig_desc i2c14_link[] = {
108 	{ 0x410, GENMASK(7, 6), 1 },
109 	{ 0x4B0, GENMASK(7, 6), 0 },
110 };
111 
112 static struct aspeed_sig_desc i2c15_link[] = {
113 	{ 0x414, GENMASK(29, 28), 1 },
114 	{ 0x4B4, GENMASK(29, 28), 1 },
115 };
116 
117 static struct aspeed_sig_desc i2c16_link[] = {
118 	{ 0x414, GENMASK(31, 30), 1 },
119 	{ 0x4B4, GENMASK(31, 30), 1 },
120 };
121 
122 
123 static struct aspeed_sig_desc mac1_link[] = {
124 	{ 0x410, BIT(4), 0 },
125 #ifndef CONFIG_FPGA_ASPEED
126 	{ 0x470, BIT(4), 1 },
127 #endif
128 };
129 
130 static struct aspeed_sig_desc mac2_link[] = {
131 	{ 0x410, BIT(5), 0	},
132 	{ 0x470, BIT(5), 1 },
133 };
134 
135 static struct aspeed_sig_desc mac3_link[] = {
136 	{ 0x410, BIT(6), 0		},
137 	{ 0x470, BIT(6), 1      	},
138 };
139 
140 static struct aspeed_sig_desc mac4_link[] = {
141 	{ 0x410, BIT(7), 0		},
142 	{ 0x470, BIT(7), 1		},
143 };
144 
145 
146 static struct aspeed_sig_desc rgmii1[] = {
147 #ifndef CONFIG_FPGA_ASPEED
148 	{ 0x500, BIT(6), 0         	},
149 	{ 0x400, GENMASK(11, 0), 0 	},
150 #endif
151 };
152 
153 static struct aspeed_sig_desc rgmii2[] = {
154 	{ 0x500, BIT(7), 0		},
155 	{ 0x400, GENMASK(23, 12), 0 	},
156 };
157 
158 static struct aspeed_sig_desc rgmii3[] = {
159 	{ 0x510, BIT(0), 0         },
160 	{ 0x410, GENMASK(27, 16), 0	},
161 };
162 
163 static struct aspeed_sig_desc rgmii4[] = {
164 	{ 0x510, BIT(1), 0         },
165 	{ 0x410, GENMASK(31, 28), 1	},
166 	{ 0x4b0, GENMASK(31, 28), 0	},
167 	{ 0x474, GENMASK(7, 0), 1	},
168 	{ 0x414, GENMASK(7, 0), 1	},
169 	{ 0x4b4, GENMASK(7, 0), 0	},
170 };
171 
172 static struct aspeed_sig_desc rmii1[] = {
173 	{ 0x504, BIT(6), 0         	},
174 	{ 0x400, GENMASK(3, 0), 0	},
175 	{ 0x400, GENMASK(11, 6), 0	},
176 };
177 
178 static struct aspeed_sig_desc rmii2[] = {
179 	{ 0x504, BIT(7), 0         	},
180 	{ 0x400, GENMASK(15, 12), 0	},
181 	{ 0x400, GENMASK(23, 18), 0	},
182 };
183 
184 static struct aspeed_sig_desc rmii3[] = {
185 	{ 0x514, BIT(0), 0         	},
186 	{ 0x410, GENMASK(27, 22), 0	},
187 	{ 0x410, GENMASK(19, 16), 0	},
188 };
189 
190 static struct aspeed_sig_desc rmii4[] = {
191 	{ 0x514, BIT(1), 0         	},
192 	{ 0x410, GENMASK(7, 2), 1	},
193 	{ 0x410, GENMASK(31, 28), 1	},
194 	{ 0x414, GENMASK(7, 2), 1	},
195 	{ 0x4B0, GENMASK(31, 28), 0	},
196 	{ 0x4B4, GENMASK(7, 2), 0	},
197 };
198 
199 static struct aspeed_sig_desc mdio1_link[] = {
200 	{ 0x430, BIT(17) | BIT(16), 0	},
201 };
202 
203 static struct aspeed_sig_desc mdio2_link[] = {
204 	{ 0x470, BIT(13) | BIT(12), 1	},
205 	{ 0x410, BIT(13) | BIT(12), 0	},
206 };
207 
208 static struct aspeed_sig_desc mdio3_link[] = {
209 	{ 0x470, BIT(1) | BIT(0), 1	},
210 	{ 0x410, BIT(1) | BIT(0), 0	},
211 };
212 
213 static struct aspeed_sig_desc mdio4_link[] = {
214 	{ 0x470, BIT(3) | BIT(2), 1	},
215 	{ 0x410, BIT(3) | BIT(2), 0	},
216 };
217 
218 static struct aspeed_sig_desc sdio2_link[] = {
219 	{ 0x414, GENMASK(23, 16), 1	},
220 	{ 0x4B4, GENMASK(23, 16), 0	},
221 	{ 0x450, BIT(1), 0		},
222 };
223 
224 static struct aspeed_sig_desc sdio1_link[] = {
225 	{ 0x414, GENMASK(15, 8), 0	},
226 };
227 
228 //when sdio1 8bits, sdio2 can't use
229 static struct aspeed_sig_desc sdio1_8bit_link[] = {
230 	{ 0x414, GENMASK(15, 8), 0	},
231 	{ 0x4b4, GENMASK(21, 18), 0	},
232 	{ 0x450, BIT(3), 0	},
233 	{ 0x450, BIT(1), 1	},
234 };
235 
236 static struct aspeed_sig_desc emmc_link[] = {
237 	{ 0x400, GENMASK(31, 24), 0 },
238 };
239 
240 static struct aspeed_sig_desc emmcg8_link[] = {
241 	{ 0x400, GENMASK(31, 24), 0 },
242 	{ 0x404, GENMASK(3, 0), 0 },
243 //because it is strap use 0x4 to clear
244 	{ 0x504, BIT(3), 0 },
245 	{ 0x504, BIT(5), 0 },
246 };
247 
248 static struct aspeed_sig_desc fmcquad_link[] = {
249 	{ 0x438, GENMASK(5, 4), 0 },
250 };
251 
252 static struct aspeed_sig_desc spi1_link[] = {
253 	{ 0x438, GENMASK(13, 11), 0 },
254 };
255 
256 static struct aspeed_sig_desc spi1abr_link[] = {
257 	{ 0x438, BIT(9), 0 },
258 };
259 
260 static struct aspeed_sig_desc spi1cs1_link[] = {
261 	{ 0x438, BIT(8), 0 },
262 };
263 
264 static struct aspeed_sig_desc spi1wp_link[] = {
265 	{ 0x438, BIT(10), 0 },
266 };
267 
268 static struct aspeed_sig_desc spi1quad_link[] = {
269 	{ 0x438, GENMASK(15, 14), 0 },
270 };
271 
272 static struct aspeed_sig_desc spi2_link[] = {
273 	{ 0x434, GENMASK(29, 27) | BIT(24), 0 },
274 };
275 
276 static struct aspeed_sig_desc spi2cs1_link[] = {
277 	{ 0x434, BIT(25), 0 },
278 };
279 
280 static struct aspeed_sig_desc spi2cs2_link[] = {
281 	{ 0x434, BIT(26), 0 },
282 };
283 
284 static struct aspeed_sig_desc spi2quad_link[] = {
285 	{ 0x434, GENMASK(31, 30), 0 },
286 };
287 
288 static struct aspeed_sig_desc fsi1[] = {
289 	{ 0xd48, GENMASK(21, 20), 0 },
290 };
291 
292 static struct aspeed_sig_desc fsi2[] = {
293 	{ 0xd48, GENMASK(23, 22), 0 },
294 };
295 
296 static struct aspeed_sig_desc usb2ah_link[] = {
297 	{ 0x440, BIT(24), 1 },
298 	{ 0x440, BIT(25), 0 },
299 };
300 
301 static struct aspeed_sig_desc usb2bh_link[] = {
302 	{ 0x440, BIT(28), 1 },
303 	{ 0x440, BIT(29), 0 },
304 };
305 
306 static struct aspeed_sig_desc pcie0rc_link[] = {
307 	{ 0x40, BIT(21), 0 },
308 };
309 
310 static struct aspeed_sig_desc pcie1rc_link[] = {
311 	{ 0x40, BIT(19), 0 },
312 	{ 0x500, BIT(24), 0 },	//dedicate rc reset
313 };
314 
315 static const struct aspeed_group_config ast2600_groups[] = {
316 	{ "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
317 	{ "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
318 	{ "MAC3LINK", ARRAY_SIZE(mac3_link), mac3_link },
319 	{ "MAC4LINK", ARRAY_SIZE(mac4_link), mac4_link },
320 	{ "RGMII1", ARRAY_SIZE(rgmii1), rgmii1 },
321 	{ "RGMII2", ARRAY_SIZE(rgmii2), rgmii2 },
322 	{ "RGMII3", ARRAY_SIZE(rgmii3), rgmii3 },
323 	{ "RGMII4", ARRAY_SIZE(rgmii4), rgmii4 },
324 	{ "RMII1", ARRAY_SIZE(rmii1), rmii1 },
325 	{ "RMII2", ARRAY_SIZE(rmii2), rmii2 },
326 	{ "RMII3", ARRAY_SIZE(rmii3), rmii3 },
327 	{ "RMII4", ARRAY_SIZE(rmii4), rmii4 },
328 	{ "MDIO1", ARRAY_SIZE(mdio1_link), mdio1_link },
329 	{ "MDIO2", ARRAY_SIZE(mdio2_link), mdio2_link },
330 	{ "MDIO3", ARRAY_SIZE(mdio3_link), mdio3_link },
331 	{ "MDIO4", ARRAY_SIZE(mdio4_link), mdio4_link },
332 	{ "SD1", ARRAY_SIZE(sdio1_link), sdio1_link },
333 	{ "SD1_8bits", ARRAY_SIZE(sdio1_8bit_link), sdio1_8bit_link },
334 	{ "SD2", ARRAY_SIZE(sdio2_link), sdio2_link },
335 	{ "EMMC", ARRAY_SIZE(emmc_link), emmc_link },
336 	{ "EMMCG8", ARRAY_SIZE(emmcg8_link), emmcg8_link },
337 	{ "FMCQUAD", ARRAY_SIZE(fmcquad_link), fmcquad_link },
338 	{ "SPI1", ARRAY_SIZE(spi1_link), spi1_link },
339 	{ "SPI1ABR", ARRAY_SIZE(spi1abr_link), spi1abr_link },
340 	{ "SPI1CS1", ARRAY_SIZE(spi1cs1_link), spi1cs1_link },
341 	{ "SPI1WP", ARRAY_SIZE(spi1wp_link), spi1wp_link },
342 	{ "SPI1QUAD", ARRAY_SIZE(spi1quad_link), spi1quad_link },
343 	{ "SPI2", ARRAY_SIZE(spi2_link), spi2_link },
344 	{ "SPI2CS1", ARRAY_SIZE(spi2cs1_link), spi2cs1_link },
345 	{ "SPI2CS2", ARRAY_SIZE(spi2cs2_link), spi2cs2_link },
346 	{ "SPI2QUAD", ARRAY_SIZE(spi2quad_link), spi2quad_link },
347 	{ "I2C1", ARRAY_SIZE(i2c1_link), i2c1_link },
348 	{ "I2C2", ARRAY_SIZE(i2c2_link), i2c2_link },
349 	{ "I2C3", ARRAY_SIZE(i2c3_link), i2c3_link },
350 	{ "I2C4", ARRAY_SIZE(i2c4_link), i2c4_link },
351 	{ "I2C5", ARRAY_SIZE(i2c5_link), i2c5_link },
352 	{ "I2C6", ARRAY_SIZE(i2c6_link), i2c6_link },
353 	{ "I2C7", ARRAY_SIZE(i2c7_link), i2c7_link },
354 	{ "I2C8", ARRAY_SIZE(i2c8_link), i2c8_link },
355 	{ "I2C9", ARRAY_SIZE(i2c9_link), i2c9_link },
356 	{ "I2C10", ARRAY_SIZE(i2c10_link), i2c10_link },
357 	{ "I2C11", ARRAY_SIZE(i2c11_link), i2c11_link },
358 	{ "I2C12", ARRAY_SIZE(i2c12_link), i2c12_link },
359 	{ "I2C13", ARRAY_SIZE(i2c13_link), i2c13_link },
360 	{ "I2C14", ARRAY_SIZE(i2c14_link), i2c14_link },
361 	{ "I2C15", ARRAY_SIZE(i2c15_link), i2c15_link },
362 	{ "I2C16", ARRAY_SIZE(i2c16_link), i2c16_link },
363 	{ "FSI1", ARRAY_SIZE(fsi1), fsi1 },
364 	{ "FSI2", ARRAY_SIZE(fsi2), fsi2 },
365 	{ "USB2AH", ARRAY_SIZE(usb2ah_link), usb2ah_link },
366 	{ "USB2BH", ARRAY_SIZE(usb2bh_link), usb2bh_link },
367 	{ "PCIE0RC", ARRAY_SIZE(pcie0rc_link), pcie0rc_link },
368 	{ "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link },
369 };
370 
371 static int ast2600_pinctrl_get_groups_count(struct udevice *dev)
372 {
373 	debug("PINCTRL: get_(functions/groups)_count\n");
374 
375 	return ARRAY_SIZE(ast2600_groups);
376 }
377 
378 static const char *ast2600_pinctrl_get_group_name(struct udevice *dev,
379 						  unsigned selector)
380 {
381 	debug("PINCTRL: get_(function/group)_name %u\n", selector);
382 
383 	return ast2600_groups[selector].group_name;
384 }
385 
386 static int ast2600_pinctrl_group_set(struct udevice *dev, unsigned selector,
387 				     unsigned func_selector)
388 {
389 	struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
390 	const struct aspeed_group_config *config;
391 	const struct aspeed_sig_desc *descs;
392 	u32 ctrl_reg = (u32)priv->scu;
393 	u32 i;
394 
395 	debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector);
396 	if (selector >= ARRAY_SIZE(ast2600_groups))
397 		return -EINVAL;
398 
399 	config = &ast2600_groups[selector];
400 	for (i = 0; i < config->ndescs; i++) {
401 		descs = &config->descs[i];
402 		if (descs->clr) {
403 			clrbits_le32((u32)ctrl_reg + descs->offset,
404 				     descs->reg_set);
405 		} else {
406 			setbits_le32((u32)ctrl_reg + descs->offset,
407 				     descs->reg_set);
408 		}
409 	}
410 
411 	return 0;
412 }
413 
414 static struct pinctrl_ops ast2600_pinctrl_ops = {
415 	.set_state = pinctrl_generic_set_state,
416 	.get_groups_count = ast2600_pinctrl_get_groups_count,
417 	.get_group_name = ast2600_pinctrl_get_group_name,
418 	.get_functions_count = ast2600_pinctrl_get_groups_count,
419 	.get_function_name = ast2600_pinctrl_get_group_name,
420 	.pinmux_group_set = ast2600_pinctrl_group_set,
421 };
422 
423 static const struct udevice_id ast2600_pinctrl_ids[] = {
424 	{ .compatible = "aspeed,g6-pinctrl" },
425 	{ }
426 };
427 
428 U_BOOT_DRIVER(pinctrl_aspeed) = {
429 	.name = "aspeed_ast2600_pinctrl",
430 	.id = UCLASS_PINCTRL,
431 	.of_match = ast2600_pinctrl_ids,
432 	.priv_auto_alloc_size = sizeof(struct ast2600_pinctrl_priv),
433 	.ops = &ast2600_pinctrl_ops,
434 	.probe = ast2600_pinctrl_probe,
435 };
436