1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <errno.h> 9 #include <asm/io.h> 10 #include <linux/bitops.h> 11 #include <asm/arch/pinctrl.h> 12 #include <asm/arch/scu_ast2600.h> 13 #include <dm/pinctrl.h> 14 #include "pinctrl-aspeed.h" 15 /* 16 * This driver works with very simple configuration that has the same name 17 * for group and function. This way it is compatible with the Linux Kernel 18 * driver. 19 */ 20 21 struct ast2600_pinctrl_priv { 22 struct ast2600_scu *scu; 23 }; 24 25 static int ast2600_pinctrl_probe(struct udevice *dev) 26 { 27 struct ast2600_pinctrl_priv *priv = dev_get_priv(dev); 28 struct udevice *clk_dev; 29 int ret = 0; 30 31 /* find SCU base address from clock device */ 32 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 33 &clk_dev); 34 if (ret) { 35 debug("clock device not found\n"); 36 return ret; 37 } 38 39 priv->scu = devfdt_get_addr_ptr(clk_dev); 40 if (IS_ERR(priv->scu)) { 41 debug("%s(): can't get SCU\n", __func__); 42 return PTR_ERR(priv->scu); 43 } 44 45 return 0; 46 } 47 48 static struct aspeed_sig_desc i2c1_link[] = { 49 { 0x418, GENMASK(9, 8), 1 }, 50 { 0x4B8, GENMASK(9, 8), 0 }, 51 }; 52 53 static struct aspeed_sig_desc i2c2_link[] = { 54 { 0x418, GENMASK(11, 10), 1 }, 55 { 0x4B8, GENMASK(11, 10), 0 }, 56 }; 57 58 static struct aspeed_sig_desc i2c3_link[] = { 59 { 0x418, GENMASK(13, 12), 1 }, 60 { 0x4B8, GENMASK(13, 12), 0 }, 61 }; 62 63 static struct aspeed_sig_desc i2c4_link[] = { 64 { 0x418, GENMASK(15, 14), 1 }, 65 { 0x4B8, GENMASK(15, 14), 0 }, 66 }; 67 68 static struct aspeed_sig_desc i2c5_link[] = { 69 { 0x418, GENMASK(17, 16), 0 }, 70 }; 71 72 static struct aspeed_sig_desc i2c6_link[] = { 73 { 0x418, GENMASK(19, 18), 0 }, 74 }; 75 76 static struct aspeed_sig_desc i2c7_link[] = { 77 { 0x418, GENMASK(21, 20), 0 }, 78 }; 79 80 static struct aspeed_sig_desc i2c8_link[] = { 81 { 0x418, GENMASK(23, 22), 0 }, 82 }; 83 84 static struct aspeed_sig_desc i2c9_link[] = { 85 { 0x418, GENMASK(25, 24), 0 }, 86 }; 87 88 static struct aspeed_sig_desc i2c10_link[] = { 89 { 0x418, GENMASK(27, 26), 0 }, 90 }; 91 92 static struct aspeed_sig_desc i2c11_link[] = { 93 { 0x410, GENMASK(1, 0), 1 }, 94 { 0x4B0, GENMASK(1, 0), 0 }, 95 }; 96 97 static struct aspeed_sig_desc i2c12_link[] = { 98 { 0x410, GENMASK(3, 2), 1 }, 99 { 0x4B0, GENMASK(3, 2), 0 }, 100 }; 101 102 static struct aspeed_sig_desc i2c13_link[] = { 103 { 0x410, GENMASK(5, 4), 1 }, 104 { 0x4B0, GENMASK(5, 4), 0 }, 105 }; 106 107 static struct aspeed_sig_desc i2c14_link[] = { 108 { 0x410, GENMASK(7, 6), 1 }, 109 { 0x4B0, GENMASK(7, 6), 0 }, 110 }; 111 112 static struct aspeed_sig_desc i2c15_link[] = { 113 { 0x414, GENMASK(29, 28), 1 }, 114 { 0x4B4, GENMASK(29, 28), 1 }, 115 }; 116 117 static struct aspeed_sig_desc i2c16_link[] = { 118 { 0x414, GENMASK(31, 30), 1 }, 119 { 0x4B4, GENMASK(31, 30), 1 }, 120 }; 121 122 123 static struct aspeed_sig_desc mac1_link[] = { 124 #ifdef CONFIG_FPGA_ASPEED 125 { 0x410, BIT(4), 0 }, 126 #else 127 { 0x400, GENMASK(11, 0), 0 }, 128 { 0x410, BIT(4), 0 }, 129 { 0x470, BIT(4), 1 }, 130 #endif 131 }; 132 133 static struct aspeed_sig_desc mac2_link[] = { 134 { 0x400, GENMASK(23, 12), 0 }, 135 { 0x410, BIT(5), 0 }, 136 { 0x470, BIT(5), 1 }, 137 }; 138 139 static struct aspeed_sig_desc mac3_link[] = { 140 { 0x410, GENMASK(27, 16), 0 }, 141 { 0x410, BIT(6), 0 }, 142 { 0x470, BIT(6), 1 }, 143 }; 144 145 static struct aspeed_sig_desc mac4_link[] = { 146 { 0x410, GENMASK(31, 28), 1 }, 147 { 0x4b0, GENMASK(31, 28), 0 }, 148 { 0x474, GENMASK(7, 0), 1 }, 149 { 0x414, GENMASK(7, 0), 1 }, 150 { 0x4b4, GENMASK(7, 0), 0 }, 151 { 0x410, BIT(7), 0 }, 152 { 0x470, BIT(7), 1 }, 153 }; 154 155 static struct aspeed_sig_desc mdio1_link[] = { 156 { 0x430, BIT(17) | BIT(16), 0 }, 157 }; 158 159 static struct aspeed_sig_desc mdio2_link[] = { 160 { 0x470, BIT(13) | BIT(12), 1 }, 161 { 0x410, BIT(13) | BIT(12), 0 }, 162 }; 163 164 static struct aspeed_sig_desc mdio3_link[] = { 165 { 0x470, BIT(1) | BIT(0), 1 }, 166 { 0x410, BIT(1) | BIT(0), 0 }, 167 }; 168 169 static struct aspeed_sig_desc mdio4_link[] = { 170 { 0x470, BIT(3) | BIT(2), 1 }, 171 { 0x410, BIT(3) | BIT(2), 0 }, 172 }; 173 174 static struct aspeed_sig_desc sdio2_link[] = { 175 { 0x414, GENMASK(23, 16), 1 }, 176 { 0x4B4, GENMASK(23, 16), 0 }, 177 { 0x450, BIT(1), 0 }, 178 }; 179 180 static struct aspeed_sig_desc sdio1_link[] = { 181 { 0x414, GENMASK(15, 8), 0 }, 182 }; 183 184 //when sdio1 8bits, sdio2 can't use 185 static struct aspeed_sig_desc sdio1_8bit_link[] = { 186 { 0x414, GENMASK(15, 8), 0 }, 187 { 0x4b4, GENMASK(21, 18), 0 }, 188 { 0x450, BIT(3), 0 }, 189 { 0x450, BIT(1), 1 }, 190 }; 191 192 static struct aspeed_sig_desc emmc_link[] = { 193 { 0x400, GENMASK(31, 24), 0 }, 194 #if 0 //8bit emmc 195 { 0x404, GENMASK(3, 0), 0 }, 196 { 0x500, BIT(3), 1 }, 197 { 0x500, BIT(5), 1 }, 198 #endif 199 }; 200 201 static struct aspeed_sig_desc fmcquad_link[] = { 202 { 0x438, GENMASK(5, 4), 0 }, 203 }; 204 205 static struct aspeed_sig_desc spi1_link[] = { 206 { 0x438, GENMASK(13, 11), 0 }, 207 }; 208 209 static struct aspeed_sig_desc spi1abr_link[] = { 210 { 0x438, BIT(9), 0 }, 211 }; 212 213 static struct aspeed_sig_desc spi1cs1_link[] = { 214 { 0x438, BIT(8), 0 }, 215 }; 216 217 static struct aspeed_sig_desc spi1wp_link[] = { 218 { 0x438, BIT(10), 0 }, 219 }; 220 221 static struct aspeed_sig_desc spi1quad_link[] = { 222 { 0x438, GENMASK(15, 14), 0 }, 223 }; 224 225 static struct aspeed_sig_desc spi2_link[] = { 226 { 0x434, GENMASK(29, 27) | BIT(24), 0 }, 227 }; 228 229 static struct aspeed_sig_desc spi2cs1_link[] = { 230 { 0x434, BIT(25), 0 }, 231 }; 232 233 static struct aspeed_sig_desc spi2cs2_link[] = { 234 { 0x434, BIT(26), 0 }, 235 }; 236 237 static struct aspeed_sig_desc spi2quad_link[] = { 238 { 0x434, GENMASK(31, 30), 0 }, 239 }; 240 241 static struct aspeed_sig_desc pcie_rc_reset_link[] = { 242 { 0x500, BIT(24), 0 }, 243 }; 244 245 static struct aspeed_sig_desc fsi1[] = { 246 { 0xd48, GENMASK(21, 20), 0 }, 247 }; 248 249 static struct aspeed_sig_desc fsi2[] = { 250 { 0xd48, GENMASK(23, 22), 0 }, 251 }; 252 253 static const struct aspeed_group_config ast2600_groups[] = { 254 { "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link }, 255 { "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link }, 256 { "MAC3LINK", ARRAY_SIZE(mac3_link), mac3_link }, 257 { "MAC4LINK", ARRAY_SIZE(mac4_link), mac4_link }, 258 { "MDIO1", ARRAY_SIZE(mdio1_link), mdio1_link }, 259 { "MDIO2", ARRAY_SIZE(mdio2_link), mdio2_link }, 260 { "MDIO3", ARRAY_SIZE(mdio3_link), mdio3_link }, 261 { "MDIO4", ARRAY_SIZE(mdio4_link), mdio4_link }, 262 { "SD1", ARRAY_SIZE(sdio1_link), sdio1_link }, 263 { "SD1_8bits", ARRAY_SIZE(sdio1_8bit_link), sdio1_8bit_link }, 264 { "SD2", ARRAY_SIZE(sdio2_link), sdio2_link }, 265 { "EMMC", ARRAY_SIZE(emmc_link), emmc_link }, 266 { "FMCQUAD", ARRAY_SIZE(fmcquad_link), fmcquad_link }, 267 { "SPI1", ARRAY_SIZE(spi1_link), spi1_link }, 268 { "SPI1ABR", ARRAY_SIZE(spi1abr_link), spi1abr_link }, 269 { "SPI1CS1", ARRAY_SIZE(spi1cs1_link), spi1cs1_link }, 270 { "SPI1WP", ARRAY_SIZE(spi1wp_link), spi1wp_link }, 271 { "SPI1QUAD", ARRAY_SIZE(spi1quad_link), spi1quad_link }, 272 { "SPI2", ARRAY_SIZE(spi2_link), spi2_link }, 273 { "SPI2CS1", ARRAY_SIZE(spi2cs1_link), spi2cs1_link }, 274 { "SPI2CS2", ARRAY_SIZE(spi2cs2_link), spi2cs2_link }, 275 { "SPI2QUAD", ARRAY_SIZE(spi2quad_link), spi2quad_link }, 276 { "I2C1", ARRAY_SIZE(i2c1_link), i2c1_link }, 277 { "I2C2", ARRAY_SIZE(i2c2_link), i2c2_link }, 278 { "I2C3", ARRAY_SIZE(i2c3_link), i2c3_link }, 279 { "I2C4", ARRAY_SIZE(i2c4_link), i2c4_link }, 280 { "I2C5", ARRAY_SIZE(i2c5_link), i2c5_link }, 281 { "I2C6", ARRAY_SIZE(i2c6_link), i2c6_link }, 282 { "I2C7", ARRAY_SIZE(i2c7_link), i2c7_link }, 283 { "I2C8", ARRAY_SIZE(i2c8_link), i2c8_link }, 284 { "I2C9", ARRAY_SIZE(i2c9_link), i2c9_link }, 285 { "I2C10", ARRAY_SIZE(i2c10_link), i2c10_link }, 286 { "I2C11", ARRAY_SIZE(i2c11_link), i2c11_link }, 287 { "I2C12", ARRAY_SIZE(i2c12_link), i2c12_link }, 288 { "I2C13", ARRAY_SIZE(i2c13_link), i2c13_link }, 289 { "I2C14", ARRAY_SIZE(i2c14_link), i2c14_link }, 290 { "I2C15", ARRAY_SIZE(i2c15_link), i2c15_link }, 291 { "I2C16", ARRAY_SIZE(i2c16_link), i2c16_link }, 292 { "PCIERC", ARRAY_SIZE(pcie_rc_reset_link), pcie_rc_reset_link }, 293 { "FSI1", ARRAY_SIZE(fsi1), fsi1 }, 294 { "FSI2", ARRAY_SIZE(fsi2), fsi2 }, 295 }; 296 297 static int ast2600_pinctrl_get_groups_count(struct udevice *dev) 298 { 299 debug("PINCTRL: get_(functions/groups)_count\n"); 300 301 return ARRAY_SIZE(ast2600_groups); 302 } 303 304 static const char *ast2600_pinctrl_get_group_name(struct udevice *dev, 305 unsigned selector) 306 { 307 debug("PINCTRL: get_(function/group)_name %u\n", selector); 308 309 return ast2600_groups[selector].group_name; 310 } 311 312 static int ast2600_pinctrl_group_set(struct udevice *dev, unsigned selector, 313 unsigned func_selector) 314 { 315 struct ast2600_pinctrl_priv *priv = dev_get_priv(dev); 316 const struct aspeed_group_config *config; 317 const struct aspeed_sig_desc *descs; 318 u32 ctrl_reg = (u32)priv->scu; 319 u32 i; 320 321 debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector); 322 if (selector >= ARRAY_SIZE(ast2600_groups)) 323 return -EINVAL; 324 325 config = &ast2600_groups[selector]; 326 for (i = 0; i < config->ndescs; i++) { 327 descs = &config->descs[i]; 328 if (descs->clr) { 329 clrbits_le32((u32)ctrl_reg + descs->offset, 330 descs->reg_set); 331 } else { 332 setbits_le32((u32)ctrl_reg + descs->offset, 333 descs->reg_set); 334 } 335 } 336 337 return 0; 338 } 339 340 static struct pinctrl_ops ast2600_pinctrl_ops = { 341 .set_state = pinctrl_generic_set_state, 342 .get_groups_count = ast2600_pinctrl_get_groups_count, 343 .get_group_name = ast2600_pinctrl_get_group_name, 344 .get_functions_count = ast2600_pinctrl_get_groups_count, 345 .get_function_name = ast2600_pinctrl_get_group_name, 346 .pinmux_group_set = ast2600_pinctrl_group_set, 347 }; 348 349 static const struct udevice_id ast2600_pinctrl_ids[] = { 350 { .compatible = "aspeed,g6-pinctrl" }, 351 { } 352 }; 353 354 U_BOOT_DRIVER(pinctrl_aspeed) = { 355 .name = "aspeed_ast2600_pinctrl", 356 .id = UCLASS_PINCTRL, 357 .of_match = ast2600_pinctrl_ids, 358 .priv_auto_alloc_size = sizeof(struct ast2600_pinctrl_priv), 359 .ops = &ast2600_pinctrl_ops, 360 .probe = ast2600_pinctrl_probe, 361 }; 362