1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  */
5 
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <linux/bitops.h>
11 #include <asm/arch/pinctrl.h>
12 #include <asm/arch/scu_ast2600.h>
13 #include <dm/pinctrl.h>
14 #include "pinctrl-aspeed.h"
15 /*
16  * This driver works with very simple configuration that has the same name
17  * for group and function. This way it is compatible with the Linux Kernel
18  * driver.
19  */
20 
21 struct ast2600_pinctrl_priv {
22 	struct ast2600_scu *scu;
23 };
24 
25 static int ast2600_pinctrl_probe(struct udevice *dev)
26 {
27 	struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
28 	struct udevice *clk_dev;
29 	int ret = 0;
30 
31 	/* find SCU base address from clock device */
32 	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
33                                           &clk_dev);
34     if (ret) {
35             debug("clock device not found\n");
36             return ret;
37     }
38 
39 	priv->scu = devfdt_get_addr_ptr(clk_dev);
40 	if (IS_ERR(priv->scu)) {
41 	        debug("%s(): can't get SCU\n", __func__);
42 	        return PTR_ERR(priv->scu);
43 	}
44 
45 	return 0;
46 }
47 
48 static struct aspeed_sig_desc i2c1_link[] = {
49 	{ 0x418, GENMASK(9, 8), 1 },
50 	{ 0x4B8, GENMASK(9, 8), 0 },
51 };
52 
53 static struct aspeed_sig_desc i2c2_link[] = {
54 	{ 0x418, GENMASK(11, 10), 1 },
55 	{ 0x4B8, GENMASK(11, 10), 0 },
56 };
57 
58 static struct aspeed_sig_desc i2c3_link[] = {
59 	{ 0x418, GENMASK(13, 12), 1 },
60 	{ 0x4B8, GENMASK(13, 12), 0 },
61 };
62 
63 static struct aspeed_sig_desc i2c4_link[] = {
64 	{ 0x418, GENMASK(15, 14), 1 },
65 	{ 0x4B8, GENMASK(15, 14), 0 },
66 };
67 
68 static struct aspeed_sig_desc i2c5_link[] = {
69 	{ 0x418, GENMASK(17, 16), 0 },
70 };
71 
72 static struct aspeed_sig_desc i2c6_link[] = {
73 	{ 0x418, GENMASK(19, 18), 0 },
74 };
75 
76 static struct aspeed_sig_desc i2c7_link[] = {
77 	{ 0x418, GENMASK(21, 20), 0 },
78 };
79 
80 static struct aspeed_sig_desc i2c8_link[] = {
81 	{ 0x418, GENMASK(23, 22), 0 },
82 };
83 
84 static struct aspeed_sig_desc i2c9_link[] = {
85 	{ 0x418, GENMASK(25, 24), 0 },
86 };
87 
88 static struct aspeed_sig_desc i2c10_link[] = {
89 	{ 0x418, GENMASK(27, 26), 0 },
90 };
91 
92 static struct aspeed_sig_desc i2c11_link[] = {
93 	{ 0x410, GENMASK(1, 0), 1 },
94 	{ 0x4B0, GENMASK(1, 0), 0 },
95 };
96 
97 static struct aspeed_sig_desc i2c12_link[] = {
98 	{ 0x410, GENMASK(3, 2), 1 },
99 	{ 0x4B0, GENMASK(3, 2), 0 },
100 };
101 
102 static struct aspeed_sig_desc i2c13_link[] = {
103 	{ 0x410, GENMASK(5, 4), 1 },
104 	{ 0x4B0, GENMASK(5, 4), 0 },
105 };
106 
107 static struct aspeed_sig_desc i2c14_link[] = {
108 	{ 0x410, GENMASK(7, 6), 1 },
109 	{ 0x4B0, GENMASK(7, 6), 0 },
110 };
111 
112 static struct aspeed_sig_desc i2c15_link[] = {
113 	{ 0x414, GENMASK(29, 28), 1 },
114 	{ 0x4B4, GENMASK(29, 28), 0 },
115 };
116 
117 static struct aspeed_sig_desc i2c16_link[] = {
118 	{ 0x414, GENMASK(31, 30), 1 },
119 	{ 0x4B4, GENMASK(31, 30), 0 },
120 };
121 
122 static struct aspeed_sig_desc si2c1_link[] = {
123 	{ 0x698, GENMASK(9, 8), 0 },
124 };
125 
126 static struct aspeed_sig_desc si2c2_link[] = {
127 	{ 0x698, GENMASK(11, 10), 0 },
128 };
129 
130 static struct aspeed_sig_desc si2c3_link[] = {
131 	{ 0x698, GENMASK(13, 12), 0 },
132 };
133 
134 static struct aspeed_sig_desc si2c4_link[] = {
135 	{ 0x698, GENMASK(15, 14), 0 },
136 };
137 
138 static struct aspeed_sig_desc si2c5_link[] = {
139 	{ 0x4B8, GENMASK(17, 16), 0 },
140 };
141 
142 static struct aspeed_sig_desc si2c6_link[] = {
143 	{ 0x4B8, GENMASK(19, 18), 0 },
144 };
145 
146 static struct aspeed_sig_desc si2c7_link[] = {
147 	{ 0x4B8, GENMASK(21, 20), 0 },
148 };
149 
150 static struct aspeed_sig_desc si2c8_link[] = {
151 	{ 0x4B8, GENMASK(23, 22), 0 },
152 };
153 
154 static struct aspeed_sig_desc si2c9_link[] = {
155 	{ 0x4B8, GENMASK(25, 24), 0 },
156 };
157 
158 static struct aspeed_sig_desc si2c10_link[] = {
159 	{ 0x4B8, GENMASK(27, 26), 1 },
160 };
161 static struct aspeed_sig_desc mac1_link[] = {
162 	{ 0x410, BIT(4), 0 },
163 #ifndef CONFIG_FPGA_ASPEED
164 	{ 0x470, BIT(4), 1 },
165 #endif
166 };
167 
168 static struct aspeed_sig_desc mac2_link[] = {
169 	{ 0x410, BIT(5), 0	},
170 	{ 0x470, BIT(5), 1 },
171 };
172 
173 static struct aspeed_sig_desc mac3_link[] = {
174 	{ 0x410, BIT(6), 0		},
175 	{ 0x470, BIT(6), 1      	},
176 };
177 
178 static struct aspeed_sig_desc mac4_link[] = {
179 	{ 0x410, BIT(7), 0		},
180 	{ 0x470, BIT(7), 1		},
181 };
182 
183 
184 static struct aspeed_sig_desc rgmii1[] = {
185 #ifndef CONFIG_FPGA_ASPEED
186 	{ 0x500, BIT(6), 0         	},
187 	{ 0x400, GENMASK(11, 0), 0 	},
188 #endif
189 };
190 
191 static struct aspeed_sig_desc rgmii2[] = {
192 	{ 0x500, BIT(7), 0		},
193 	{ 0x400, GENMASK(23, 12), 0 	},
194 };
195 
196 static struct aspeed_sig_desc rgmii3[] = {
197 	{ 0x510, BIT(0), 0         },
198 	{ 0x410, GENMASK(27, 16), 0	},
199 };
200 
201 static struct aspeed_sig_desc rgmii4[] = {
202 	{ 0x510, BIT(1), 0         },
203 	{ 0x410, GENMASK(31, 28), 1	},
204 	{ 0x4b0, GENMASK(31, 28), 0	},
205 	{ 0x474, GENMASK(7, 0), 1	},
206 	{ 0x414, GENMASK(7, 0), 1	},
207 	{ 0x4b4, GENMASK(7, 0), 0	},
208 };
209 
210 static struct aspeed_sig_desc rmii1[] = {
211 	{ 0x504, BIT(6), 0         	},
212 	{ 0x400, GENMASK(3, 0), 0	},
213 	{ 0x400, GENMASK(11, 6), 0	},
214 };
215 
216 static struct aspeed_sig_desc rmii2[] = {
217 	{ 0x504, BIT(7), 0         	},
218 	{ 0x400, GENMASK(15, 12), 0	},
219 	{ 0x400, GENMASK(23, 18), 0	},
220 };
221 
222 static struct aspeed_sig_desc rmii3[] = {
223 	{ 0x514, BIT(0), 0         	},
224 	{ 0x410, GENMASK(27, 22), 0	},
225 	{ 0x410, GENMASK(19, 16), 0	},
226 };
227 
228 static struct aspeed_sig_desc rmii4[] = {
229 	{ 0x514, BIT(1), 0         	},
230 	{ 0x410, GENMASK(7, 2), 1	},
231 	{ 0x410, GENMASK(31, 28), 1	},
232 	{ 0x414, GENMASK(7, 2), 1	},
233 	{ 0x4B0, GENMASK(31, 28), 0	},
234 	{ 0x4B4, GENMASK(7, 2), 0	},
235 };
236 
237 static struct aspeed_sig_desc rmii1_rclk_oe[] = {
238 	{ 0x340, BIT(29), 0         	},
239 };
240 static struct aspeed_sig_desc rmii2_rclk_oe[] = {
241 	{ 0x340, BIT(30), 0         	},
242 };
243 
244 static struct aspeed_sig_desc rmii3_rclk_oe[] = {
245 	{ 0x350, BIT(29), 0         	},
246 };
247 static struct aspeed_sig_desc rmii4_rclk_oe[] = {
248 	{ 0x350, BIT(30), 0         	},
249 };
250 
251 static struct aspeed_sig_desc mdio1_link[] = {
252 	{ 0x430, BIT(17) | BIT(16), 0	},
253 };
254 
255 static struct aspeed_sig_desc mdio2_link[] = {
256 	{ 0x470, BIT(13) | BIT(12), 1	},
257 	{ 0x410, BIT(13) | BIT(12), 0	},
258 };
259 
260 static struct aspeed_sig_desc mdio3_link[] = {
261 	{ 0x470, BIT(1) | BIT(0), 1	},
262 	{ 0x410, BIT(1) | BIT(0), 0	},
263 };
264 
265 static struct aspeed_sig_desc mdio4_link[] = {
266 	{ 0x470, BIT(3) | BIT(2), 1	},
267 	{ 0x410, BIT(3) | BIT(2), 0	},
268 };
269 
270 static struct aspeed_sig_desc sdio2_link[] = {
271 	{ 0x414, GENMASK(23, 16), 1	},
272 	{ 0x4B4, GENMASK(23, 16), 0	},
273 	{ 0x450, BIT(1), 0		},
274 };
275 
276 static struct aspeed_sig_desc sdio1_link[] = {
277 	{ 0x414, GENMASK(15, 8), 0	},
278 };
279 
280 //when sdio1 8bits, sdio2 can't use
281 static struct aspeed_sig_desc sdio1_8bit_link[] = {
282 	{ 0x414, GENMASK(15, 8), 0	},
283 	{ 0x4b4, GENMASK(21, 18), 0	},
284 	{ 0x450, BIT(3), 0	},
285 	{ 0x450, BIT(1), 1	},
286 };
287 
288 static struct aspeed_sig_desc emmc_link[] = {
289 	{ 0x400, GENMASK(31, 24), 0 },
290 };
291 
292 static struct aspeed_sig_desc emmcg8_link[] = {
293 	{ 0x400, GENMASK(31, 24), 0 },
294 	{ 0x404, GENMASK(3, 0), 0 },
295 //because it is strap use 0x4 to clear
296 	{ 0x504, BIT(3), 0 },
297 	{ 0x504, BIT(5), 0 },
298 };
299 
300 static struct aspeed_sig_desc fmcquad_link[] = {
301 	{ 0x438, GENMASK(5, 4), 0 },
302 };
303 
304 static struct aspeed_sig_desc spi1_link[] = {
305 	{ 0x438, GENMASK(13, 11), 0 },
306 };
307 
308 static struct aspeed_sig_desc spi1abr_link[] = {
309 	{ 0x438, BIT(9), 0 },
310 };
311 
312 static struct aspeed_sig_desc spi1cs1_link[] = {
313 	{ 0x438, BIT(8), 0 },
314 };
315 
316 static struct aspeed_sig_desc spi1wp_link[] = {
317 	{ 0x438, BIT(10), 0 },
318 };
319 
320 static struct aspeed_sig_desc spi1quad_link[] = {
321 	{ 0x438, GENMASK(15, 14), 0 },
322 };
323 
324 static struct aspeed_sig_desc spi2_link[] = {
325 	{ 0x434, GENMASK(29, 27) | BIT(24), 0 },
326 };
327 
328 static struct aspeed_sig_desc spi2cs1_link[] = {
329 	{ 0x434, BIT(25), 0 },
330 };
331 
332 static struct aspeed_sig_desc spi2cs2_link[] = {
333 	{ 0x434, BIT(26), 0 },
334 };
335 
336 static struct aspeed_sig_desc spi2quad_link[] = {
337 	{ 0x434, GENMASK(31, 30), 0 },
338 };
339 
340 static struct aspeed_sig_desc fsi1[] = {
341 	{ 0xd48, GENMASK(21, 20), 0 },
342 };
343 
344 static struct aspeed_sig_desc fsi2[] = {
345 	{ 0xd48, GENMASK(23, 22), 0 },
346 };
347 
348 static struct aspeed_sig_desc usb2ad_link[] = {
349 	{ 0x440, BIT(24), 0 },
350 	{ 0x440, BIT(25), 1 },
351 };
352 
353 static struct aspeed_sig_desc usb2ah_link[] = {
354 	{ 0x440, BIT(24), 1 },
355 	{ 0x440, BIT(25), 0 },
356 };
357 
358 static struct aspeed_sig_desc usb2bh_link[] = {
359 	{ 0x440, BIT(28), 1 },
360 	{ 0x440, BIT(29), 0 },
361 };
362 
363 static struct aspeed_sig_desc pcie0rc_link[] = {
364 	{ 0x40, BIT(21), 0 },
365 	{ 0xC8, BIT(6), 1 },	//enable ep for as Root Complex
366 };
367 
368 static struct aspeed_sig_desc pcie1rc_link[] = {
369 	{ 0x40, BIT(19), 0 },	//SSPRST# output enable
370 	{ 0x500, BIT(24), 0 },	//dedicate rc reset
371 };
372 
373 static struct aspeed_sig_desc txd1_link[] = {
374 	{ 0x41c, BIT(6), 0 },
375 };
376 
377 static struct aspeed_sig_desc rxd1_link[] = {
378 	{ 0x41c, BIT(7), 0 },
379 };
380 
381 static struct aspeed_sig_desc txd2_link[] = {
382 	{ 0x41c, BIT(14), 0 },
383 };
384 
385 static struct aspeed_sig_desc rxd2_link[] = {
386 	{ 0x41c, BIT(15), 0 },
387 };
388 
389 static struct aspeed_sig_desc txd3_link[] = {
390 	{ 0x418, BIT(28), 0 },
391 };
392 
393 static struct aspeed_sig_desc rxd3_link[] = {
394 	{ 0x418, BIT(29), 0 },
395 };
396 
397 static struct aspeed_sig_desc txd4_link[] = {
398 	{ 0x410, BIT(14), 0 },
399 };
400 
401 static struct aspeed_sig_desc rxd4_link[] = {
402 	{ 0x410, BIT(15), 0 },
403 };
404 
405 static const struct aspeed_group_config ast2600_groups[] = {
406 	{ "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
407 	{ "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
408 	{ "MAC3LINK", ARRAY_SIZE(mac3_link), mac3_link },
409 	{ "MAC4LINK", ARRAY_SIZE(mac4_link), mac4_link },
410 	{ "RGMII1", ARRAY_SIZE(rgmii1), rgmii1 },
411 	{ "RGMII2", ARRAY_SIZE(rgmii2), rgmii2 },
412 	{ "RGMII3", ARRAY_SIZE(rgmii3), rgmii3 },
413 	{ "RGMII4", ARRAY_SIZE(rgmii4), rgmii4 },
414 	{ "RMII1", ARRAY_SIZE(rmii1), rmii1 },
415 	{ "RMII2", ARRAY_SIZE(rmii2), rmii2 },
416 	{ "RMII3", ARRAY_SIZE(rmii3), rmii3 },
417 	{ "RMII4", ARRAY_SIZE(rmii4), rmii4 },
418 	{ "RMII1RCLK", ARRAY_SIZE(rmii1_rclk_oe), rmii1_rclk_oe },
419 	{ "RMII2RCLK", ARRAY_SIZE(rmii2_rclk_oe), rmii2_rclk_oe },
420 	{ "RMII3RCLK", ARRAY_SIZE(rmii3_rclk_oe), rmii3_rclk_oe },
421 	{ "RMII4RCLK", ARRAY_SIZE(rmii4_rclk_oe), rmii4_rclk_oe },
422 	{ "MDIO1", ARRAY_SIZE(mdio1_link), mdio1_link },
423 	{ "MDIO2", ARRAY_SIZE(mdio2_link), mdio2_link },
424 	{ "MDIO3", ARRAY_SIZE(mdio3_link), mdio3_link },
425 	{ "MDIO4", ARRAY_SIZE(mdio4_link), mdio4_link },
426 	{ "SD1", ARRAY_SIZE(sdio1_link), sdio1_link },
427 	{ "SD1_8bits", ARRAY_SIZE(sdio1_8bit_link), sdio1_8bit_link },
428 	{ "SD2", ARRAY_SIZE(sdio2_link), sdio2_link },
429 	{ "EMMC", ARRAY_SIZE(emmc_link), emmc_link },
430 	{ "EMMCG8", ARRAY_SIZE(emmcg8_link), emmcg8_link },
431 	{ "FMCQUAD", ARRAY_SIZE(fmcquad_link), fmcquad_link },
432 	{ "SPI1", ARRAY_SIZE(spi1_link), spi1_link },
433 	{ "SPI1ABR", ARRAY_SIZE(spi1abr_link), spi1abr_link },
434 	{ "SPI1CS1", ARRAY_SIZE(spi1cs1_link), spi1cs1_link },
435 	{ "SPI1WP", ARRAY_SIZE(spi1wp_link), spi1wp_link },
436 	{ "SPI1QUAD", ARRAY_SIZE(spi1quad_link), spi1quad_link },
437 	{ "SPI2", ARRAY_SIZE(spi2_link), spi2_link },
438 	{ "SPI2CS1", ARRAY_SIZE(spi2cs1_link), spi2cs1_link },
439 	{ "SPI2CS2", ARRAY_SIZE(spi2cs2_link), spi2cs2_link },
440 	{ "SPI2QUAD", ARRAY_SIZE(spi2quad_link), spi2quad_link },
441 	{ "I2C1", ARRAY_SIZE(i2c1_link), i2c1_link },
442 	{ "I2C2", ARRAY_SIZE(i2c2_link), i2c2_link },
443 	{ "I2C3", ARRAY_SIZE(i2c3_link), i2c3_link },
444 	{ "I2C4", ARRAY_SIZE(i2c4_link), i2c4_link },
445 	{ "I2C5", ARRAY_SIZE(i2c5_link), i2c5_link },
446 	{ "I2C6", ARRAY_SIZE(i2c6_link), i2c6_link },
447 	{ "I2C7", ARRAY_SIZE(i2c7_link), i2c7_link },
448 	{ "I2C8", ARRAY_SIZE(i2c8_link), i2c8_link },
449 	{ "I2C9", ARRAY_SIZE(i2c9_link), i2c9_link },
450 	{ "I2C10", ARRAY_SIZE(i2c10_link), i2c10_link },
451 	{ "I2C11", ARRAY_SIZE(i2c11_link), i2c11_link },
452 	{ "I2C12", ARRAY_SIZE(i2c12_link), i2c12_link },
453 	{ "I2C13", ARRAY_SIZE(i2c13_link), i2c13_link },
454 	{ "I2C14", ARRAY_SIZE(i2c14_link), i2c14_link },
455 	{ "I2C15", ARRAY_SIZE(i2c15_link), i2c15_link },
456 	{ "I2C16", ARRAY_SIZE(i2c16_link), i2c16_link },
457 	{ "SI2C1", ARRAY_SIZE(si2c1_link), si2c1_link },
458 	{ "SI2C2", ARRAY_SIZE(si2c2_link), si2c2_link },
459 	{ "SI2C3", ARRAY_SIZE(si2c3_link), si2c3_link },
460 	{ "SI2C4", ARRAY_SIZE(si2c4_link), si2c4_link },
461 	{ "SI2C5", ARRAY_SIZE(si2c5_link), si2c5_link },
462 	{ "SI2C6", ARRAY_SIZE(si2c6_link), si2c6_link },
463 	{ "SI2C7", ARRAY_SIZE(si2c7_link), si2c7_link },
464 	{ "SI2C8", ARRAY_SIZE(si2c8_link), si2c8_link },
465 	{ "SI2C9", ARRAY_SIZE(si2c9_link), si2c9_link },
466 	{ "SI2C10", ARRAY_SIZE(si2c10_link), si2c10_link },
467 	{ "FSI1", ARRAY_SIZE(fsi1), fsi1 },
468 	{ "FSI2", ARRAY_SIZE(fsi2), fsi2 },
469 	{ "USB2AD", ARRAY_SIZE(usb2ad_link), usb2ad_link },
470 	{ "USB2AH", ARRAY_SIZE(usb2ah_link), usb2ah_link },
471 	{ "USB2BH", ARRAY_SIZE(usb2bh_link), usb2bh_link },
472 	{ "PCIE0RC", ARRAY_SIZE(pcie0rc_link), pcie0rc_link },
473 	{ "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link },
474 	{ "TXD1", ARRAY_SIZE(txd1_link), txd1_link },
475 	{ "RXD1", ARRAY_SIZE(rxd1_link), rxd1_link },
476 	{ "TXD2", ARRAY_SIZE(txd2_link), txd2_link },
477 	{ "RXD2", ARRAY_SIZE(rxd2_link), rxd2_link },
478 	{ "TXD3", ARRAY_SIZE(txd3_link), txd3_link },
479 	{ "RXD3", ARRAY_SIZE(rxd3_link), rxd3_link },
480 	{ "TXD4", ARRAY_SIZE(txd4_link), txd4_link },
481 	{ "RXD4", ARRAY_SIZE(rxd4_link), rxd4_link },
482 
483 };
484 
485 static int ast2600_pinctrl_get_groups_count(struct udevice *dev)
486 {
487 	debug("PINCTRL: get_(functions/groups)_count\n");
488 
489 	return ARRAY_SIZE(ast2600_groups);
490 }
491 
492 static const char *ast2600_pinctrl_get_group_name(struct udevice *dev,
493 						  unsigned selector)
494 {
495 	debug("PINCTRL: get_(function/group)_name %u\n", selector);
496 
497 	return ast2600_groups[selector].group_name;
498 }
499 
500 static int ast2600_pinctrl_group_set(struct udevice *dev, unsigned selector,
501 				     unsigned func_selector)
502 {
503 	struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
504 	const struct aspeed_group_config *config;
505 	const struct aspeed_sig_desc *descs;
506 	u32 ctrl_reg = (u32)priv->scu;
507 	u32 i;
508 
509 	debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector);
510 	if (selector >= ARRAY_SIZE(ast2600_groups))
511 		return -EINVAL;
512 
513 	config = &ast2600_groups[selector];
514 	for (i = 0; i < config->ndescs; i++) {
515 		descs = &config->descs[i];
516 		if (descs->clr) {
517 			clrbits_le32((u32)ctrl_reg + descs->offset,
518 				     descs->reg_set);
519 		} else {
520 			setbits_le32((u32)ctrl_reg + descs->offset,
521 				     descs->reg_set);
522 		}
523 	}
524 
525 	return 0;
526 }
527 
528 static struct pinctrl_ops ast2600_pinctrl_ops = {
529 	.set_state = pinctrl_generic_set_state,
530 	.get_groups_count = ast2600_pinctrl_get_groups_count,
531 	.get_group_name = ast2600_pinctrl_get_group_name,
532 	.get_functions_count = ast2600_pinctrl_get_groups_count,
533 	.get_function_name = ast2600_pinctrl_get_group_name,
534 	.pinmux_group_set = ast2600_pinctrl_group_set,
535 };
536 
537 static const struct udevice_id ast2600_pinctrl_ids[] = {
538 	{ .compatible = "aspeed,g6-pinctrl" },
539 	{ }
540 };
541 
542 U_BOOT_DRIVER(pinctrl_aspeed) = {
543 	.name = "aspeed_ast2600_pinctrl",
544 	.id = UCLASS_PINCTRL,
545 	.of_match = ast2600_pinctrl_ids,
546 	.priv_auto_alloc_size = sizeof(struct ast2600_pinctrl_priv),
547 	.ops = &ast2600_pinctrl_ops,
548 	.probe = ast2600_pinctrl_probe,
549 };
550