1*6cfc3d66SMarek Vasut // SPDX-License-Identifier: GPL-2.0
2*6cfc3d66SMarek Vasut /*
3*6cfc3d66SMarek Vasut * Renesas RCar Gen3 USB PHY driver
4*6cfc3d66SMarek Vasut *
5*6cfc3d66SMarek Vasut * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6*6cfc3d66SMarek Vasut */
7*6cfc3d66SMarek Vasut
8*6cfc3d66SMarek Vasut #include <common.h>
9*6cfc3d66SMarek Vasut #include <clk.h>
10*6cfc3d66SMarek Vasut #include <div64.h>
11*6cfc3d66SMarek Vasut #include <dm.h>
12*6cfc3d66SMarek Vasut #include <fdtdec.h>
13*6cfc3d66SMarek Vasut #include <generic-phy.h>
14*6cfc3d66SMarek Vasut #include <reset.h>
15*6cfc3d66SMarek Vasut #include <syscon.h>
16*6cfc3d66SMarek Vasut #include <usb.h>
17*6cfc3d66SMarek Vasut #include <asm/io.h>
18*6cfc3d66SMarek Vasut #include <linux/bitops.h>
19*6cfc3d66SMarek Vasut #include <power/regulator.h>
20*6cfc3d66SMarek Vasut
21*6cfc3d66SMarek Vasut /* USB2.0 Host registers (original offset is +0x200) */
22*6cfc3d66SMarek Vasut #define USB2_INT_ENABLE 0x000
23*6cfc3d66SMarek Vasut #define USB2_USBCTR 0x00c
24*6cfc3d66SMarek Vasut #define USB2_SPD_RSM_TIMSET 0x10c
25*6cfc3d66SMarek Vasut #define USB2_OC_TIMSET 0x110
26*6cfc3d66SMarek Vasut #define USB2_COMMCTRL 0x600
27*6cfc3d66SMarek Vasut #define USB2_OBINTSTA 0x604
28*6cfc3d66SMarek Vasut #define USB2_OBINTEN 0x608
29*6cfc3d66SMarek Vasut #define USB2_VBCTRL 0x60c
30*6cfc3d66SMarek Vasut #define USB2_LINECTRL1 0x610
31*6cfc3d66SMarek Vasut #define USB2_ADPCTRL 0x630
32*6cfc3d66SMarek Vasut
33*6cfc3d66SMarek Vasut /* USBCTR */
34*6cfc3d66SMarek Vasut #define USB2_USBCTR_PLL_RST BIT(1)
35*6cfc3d66SMarek Vasut
36*6cfc3d66SMarek Vasut /* SPD_RSM_TIMSET */
37*6cfc3d66SMarek Vasut #define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
38*6cfc3d66SMarek Vasut
39*6cfc3d66SMarek Vasut /* OC_TIMSET */
40*6cfc3d66SMarek Vasut #define USB2_OC_TIMSET_INIT 0x000209ab
41*6cfc3d66SMarek Vasut
42*6cfc3d66SMarek Vasut /* COMMCTRL */
43*6cfc3d66SMarek Vasut #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
44*6cfc3d66SMarek Vasut
45*6cfc3d66SMarek Vasut /* LINECTRL1 */
46*6cfc3d66SMarek Vasut #define USB2_LINECTRL1_DP_RPD BIT(18)
47*6cfc3d66SMarek Vasut #define USB2_LINECTRL1_DM_RPD BIT(16)
48*6cfc3d66SMarek Vasut
49*6cfc3d66SMarek Vasut /* ADPCTRL */
50*6cfc3d66SMarek Vasut #define USB2_ADPCTRL_DRVVBUS BIT(4)
51*6cfc3d66SMarek Vasut
52*6cfc3d66SMarek Vasut struct rcar_gen3_phy {
53*6cfc3d66SMarek Vasut fdt_addr_t regs;
54*6cfc3d66SMarek Vasut struct clk clk;
55*6cfc3d66SMarek Vasut struct udevice *vbus_supply;
56*6cfc3d66SMarek Vasut };
57*6cfc3d66SMarek Vasut
rcar_gen3_phy_phy_init(struct phy * phy)58*6cfc3d66SMarek Vasut static int rcar_gen3_phy_phy_init(struct phy *phy)
59*6cfc3d66SMarek Vasut {
60*6cfc3d66SMarek Vasut struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
61*6cfc3d66SMarek Vasut
62*6cfc3d66SMarek Vasut /* Initialize USB2 part */
63*6cfc3d66SMarek Vasut writel(0, priv->regs + USB2_INT_ENABLE);
64*6cfc3d66SMarek Vasut writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET);
65*6cfc3d66SMarek Vasut writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET);
66*6cfc3d66SMarek Vasut
67*6cfc3d66SMarek Vasut setbits_le32(priv->regs + USB2_LINECTRL1,
68*6cfc3d66SMarek Vasut USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
69*6cfc3d66SMarek Vasut
70*6cfc3d66SMarek Vasut clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
71*6cfc3d66SMarek Vasut
72*6cfc3d66SMarek Vasut setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
73*6cfc3d66SMarek Vasut
74*6cfc3d66SMarek Vasut return 0;
75*6cfc3d66SMarek Vasut }
76*6cfc3d66SMarek Vasut
rcar_gen3_phy_phy_power_on(struct phy * phy)77*6cfc3d66SMarek Vasut static int rcar_gen3_phy_phy_power_on(struct phy *phy)
78*6cfc3d66SMarek Vasut {
79*6cfc3d66SMarek Vasut struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
80*6cfc3d66SMarek Vasut int ret;
81*6cfc3d66SMarek Vasut
82*6cfc3d66SMarek Vasut if (priv->vbus_supply) {
83*6cfc3d66SMarek Vasut ret = regulator_set_enable(priv->vbus_supply, true);
84*6cfc3d66SMarek Vasut if (ret)
85*6cfc3d66SMarek Vasut return ret;
86*6cfc3d66SMarek Vasut }
87*6cfc3d66SMarek Vasut
88*6cfc3d66SMarek Vasut setbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
89*6cfc3d66SMarek Vasut clrbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
90*6cfc3d66SMarek Vasut
91*6cfc3d66SMarek Vasut return 0;
92*6cfc3d66SMarek Vasut }
93*6cfc3d66SMarek Vasut
rcar_gen3_phy_phy_power_off(struct phy * phy)94*6cfc3d66SMarek Vasut static int rcar_gen3_phy_phy_power_off(struct phy *phy)
95*6cfc3d66SMarek Vasut {
96*6cfc3d66SMarek Vasut struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
97*6cfc3d66SMarek Vasut
98*6cfc3d66SMarek Vasut if (!priv->vbus_supply)
99*6cfc3d66SMarek Vasut return 0;
100*6cfc3d66SMarek Vasut
101*6cfc3d66SMarek Vasut return regulator_set_enable(priv->vbus_supply, false);
102*6cfc3d66SMarek Vasut }
103*6cfc3d66SMarek Vasut
104*6cfc3d66SMarek Vasut static const struct phy_ops rcar_gen3_phy_phy_ops = {
105*6cfc3d66SMarek Vasut .init = rcar_gen3_phy_phy_init,
106*6cfc3d66SMarek Vasut .power_on = rcar_gen3_phy_phy_power_on,
107*6cfc3d66SMarek Vasut .power_off = rcar_gen3_phy_phy_power_off,
108*6cfc3d66SMarek Vasut };
109*6cfc3d66SMarek Vasut
rcar_gen3_phy_probe(struct udevice * dev)110*6cfc3d66SMarek Vasut static int rcar_gen3_phy_probe(struct udevice *dev)
111*6cfc3d66SMarek Vasut {
112*6cfc3d66SMarek Vasut struct rcar_gen3_phy *priv = dev_get_priv(dev);
113*6cfc3d66SMarek Vasut int ret;
114*6cfc3d66SMarek Vasut
115*6cfc3d66SMarek Vasut priv->regs = dev_read_addr(dev);
116*6cfc3d66SMarek Vasut if (priv->regs == FDT_ADDR_T_NONE)
117*6cfc3d66SMarek Vasut return -EINVAL;
118*6cfc3d66SMarek Vasut
119*6cfc3d66SMarek Vasut ret = device_get_supply_regulator(dev, "vbus-supply",
120*6cfc3d66SMarek Vasut &priv->vbus_supply);
121*6cfc3d66SMarek Vasut if (ret && ret != -ENOENT) {
122*6cfc3d66SMarek Vasut pr_err("Failed to get PHY regulator\n");
123*6cfc3d66SMarek Vasut return ret;
124*6cfc3d66SMarek Vasut }
125*6cfc3d66SMarek Vasut
126*6cfc3d66SMarek Vasut /* Enable clock */
127*6cfc3d66SMarek Vasut ret = clk_get_by_index(dev, 0, &priv->clk);
128*6cfc3d66SMarek Vasut if (ret)
129*6cfc3d66SMarek Vasut return ret;
130*6cfc3d66SMarek Vasut
131*6cfc3d66SMarek Vasut ret = clk_enable(&priv->clk);
132*6cfc3d66SMarek Vasut if (ret)
133*6cfc3d66SMarek Vasut return ret;
134*6cfc3d66SMarek Vasut
135*6cfc3d66SMarek Vasut return 0;
136*6cfc3d66SMarek Vasut }
137*6cfc3d66SMarek Vasut
rcar_gen3_phy_remove(struct udevice * dev)138*6cfc3d66SMarek Vasut static int rcar_gen3_phy_remove(struct udevice *dev)
139*6cfc3d66SMarek Vasut {
140*6cfc3d66SMarek Vasut struct rcar_gen3_phy *priv = dev_get_priv(dev);
141*6cfc3d66SMarek Vasut
142*6cfc3d66SMarek Vasut clk_disable(&priv->clk);
143*6cfc3d66SMarek Vasut clk_free(&priv->clk);
144*6cfc3d66SMarek Vasut
145*6cfc3d66SMarek Vasut return 0;
146*6cfc3d66SMarek Vasut }
147*6cfc3d66SMarek Vasut
148*6cfc3d66SMarek Vasut static const struct udevice_id rcar_gen3_phy_of_match[] = {
149*6cfc3d66SMarek Vasut { .compatible = "renesas,rcar-gen3-usb2-phy", },
150*6cfc3d66SMarek Vasut { },
151*6cfc3d66SMarek Vasut };
152*6cfc3d66SMarek Vasut
153*6cfc3d66SMarek Vasut U_BOOT_DRIVER(rcar_gen3_phy) = {
154*6cfc3d66SMarek Vasut .name = "rcar-gen3-phy",
155*6cfc3d66SMarek Vasut .id = UCLASS_PHY,
156*6cfc3d66SMarek Vasut .of_match = rcar_gen3_phy_of_match,
157*6cfc3d66SMarek Vasut .ops = &rcar_gen3_phy_phy_ops,
158*6cfc3d66SMarek Vasut .probe = rcar_gen3_phy_probe,
159*6cfc3d66SMarek Vasut .remove = rcar_gen3_phy_remove,
160*6cfc3d66SMarek Vasut .priv_auto_alloc_size = sizeof(struct rcar_gen3_phy),
161*6cfc3d66SMarek Vasut };
162