1*c0132f60SStefan Roese /* 2*c0132f60SStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 3*c0132f60SStefan Roese * 4*c0132f60SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5*c0132f60SStefan Roese */ 6*c0132f60SStefan Roese 7*c0132f60SStefan Roese #ifndef _UTMI_PHY_H_ 8*c0132f60SStefan Roese #define _UTMI_PHY_H_ 9*c0132f60SStefan Roese 10*c0132f60SStefan Roese #define UTMI_USB_CFG_DEVICE_EN_OFFSET 0 11*c0132f60SStefan Roese #define UTMI_USB_CFG_DEVICE_EN_MASK \ 12*c0132f60SStefan Roese (0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET) 13*c0132f60SStefan Roese #define UTMI_USB_CFG_DEVICE_MUX_OFFSET 1 14*c0132f60SStefan Roese #define UTMI_USB_CFG_DEVICE_MUX_MASK \ 15*c0132f60SStefan Roese (0x1 << UTMI_USB_CFG_DEVICE_MUX_OFFSET) 16*c0132f60SStefan Roese #define UTMI_USB_CFG_PLL_OFFSET 25 17*c0132f60SStefan Roese #define UTMI_USB_CFG_PLL_MASK \ 18*c0132f60SStefan Roese (0x1 << UTMI_USB_CFG_PLL_OFFSET) 19*c0132f60SStefan Roese 20*c0132f60SStefan Roese #define UTMI_PHY_CFG_PU_OFFSET 5 21*c0132f60SStefan Roese #define UTMI_PHY_CFG_PU_MASK \ 22*c0132f60SStefan Roese (0x1 << UTMI_PHY_CFG_PU_OFFSET) 23*c0132f60SStefan Roese 24*c0132f60SStefan Roese #define UTMI_PLL_CTRL_REG 0x0 25*c0132f60SStefan Roese #define UTMI_PLL_CTRL_REFDIV_OFFSET 0 26*c0132f60SStefan Roese #define UTMI_PLL_CTRL_REFDIV_MASK \ 27*c0132f60SStefan Roese (0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET) 28*c0132f60SStefan Roese #define UTMI_PLL_CTRL_FBDIV_OFFSET 16 29*c0132f60SStefan Roese #define UTMI_PLL_CTRL_FBDIV_MASK \ 30*c0132f60SStefan Roese (0x1FF << UTMI_PLL_CTRL_FBDIV_OFFSET) 31*c0132f60SStefan Roese #define UTMI_PLL_CTRL_SEL_LPFR_OFFSET 28 32*c0132f60SStefan Roese #define UTMI_PLL_CTRL_SEL_LPFR_MASK \ 33*c0132f60SStefan Roese (0x3 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET) 34*c0132f60SStefan Roese #define UTMI_PLL_CTRL_PLL_RDY_OFFSET 31 35*c0132f60SStefan Roese #define UTMI_PLL_CTRL_PLL_RDY_MASK \ 36*c0132f60SStefan Roese (0x1 << UTMI_PLL_CTRL_PLL_RDY_OFFSET) 37*c0132f60SStefan Roese 38*c0132f60SStefan Roese #define UTMI_CALIB_CTRL_REG 0x8 39*c0132f60SStefan Roese #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 40*c0132f60SStefan Roese #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \ 41*c0132f60SStefan Roese (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) 42*c0132f60SStefan Roese #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 43*c0132f60SStefan Roese #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \ 44*c0132f60SStefan Roese (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) 45*c0132f60SStefan Roese #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 46*c0132f60SStefan Roese #define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \ 47*c0132f60SStefan Roese (0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET) 48*c0132f60SStefan Roese 49*c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_REG 0xC 50*c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12 51*c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \ 52*c0132f60SStefan Roese (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) 53*c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 54*c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \ 55*c0132f60SStefan Roese (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) 56*c0132f60SStefan Roese 57*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_REG 0x14 58*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 59*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_SQ_DET_MASK \ 60*c0132f60SStefan Roese (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) 61*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 62*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \ 63*c0132f60SStefan Roese (0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET) 64*c0132f60SStefan Roese 65*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_REG 0x18 66*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 67*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \ 68*c0132f60SStefan Roese (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) 69*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 70*c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \ 71*c0132f60SStefan Roese (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) 72*c0132f60SStefan Roese 73*c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_REG 0x24 74*c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22 75*c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_SUSPENDM_MASK \ 76*c0132f60SStefan Roese (0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET) 77*c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET 25 78*c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_TEST_SEL_MASK \ 79*c0132f60SStefan Roese (0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET) 80*c0132f60SStefan Roese 81*c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_REG 0x38 82*c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8 83*c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_VDAT_MASK \ 84*c0132f60SStefan Roese (0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET) 85*c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_VSRC_OFFSET 10 86*c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_VSRC_MASK \ 87*c0132f60SStefan Roese (0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET) 88*c0132f60SStefan Roese 89*c0132f60SStefan Roese #endif /* _UTMI_PHY_H_ */ 90*c0132f60SStefan Roese 91