1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c0132f60SStefan Roese /* 3c0132f60SStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 4c0132f60SStefan Roese */ 5c0132f60SStefan Roese 6c0132f60SStefan Roese #ifndef _UTMI_PHY_H_ 7c0132f60SStefan Roese #define _UTMI_PHY_H_ 8c0132f60SStefan Roese 9c0132f60SStefan Roese #define UTMI_USB_CFG_DEVICE_EN_OFFSET 0 10c0132f60SStefan Roese #define UTMI_USB_CFG_DEVICE_EN_MASK \ 11c0132f60SStefan Roese (0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET) 12c0132f60SStefan Roese #define UTMI_USB_CFG_DEVICE_MUX_OFFSET 1 13c0132f60SStefan Roese #define UTMI_USB_CFG_DEVICE_MUX_MASK \ 14c0132f60SStefan Roese (0x1 << UTMI_USB_CFG_DEVICE_MUX_OFFSET) 15c0132f60SStefan Roese #define UTMI_USB_CFG_PLL_OFFSET 25 16c0132f60SStefan Roese #define UTMI_USB_CFG_PLL_MASK \ 17c0132f60SStefan Roese (0x1 << UTMI_USB_CFG_PLL_OFFSET) 18c0132f60SStefan Roese 19c0132f60SStefan Roese #define UTMI_PHY_CFG_PU_OFFSET 5 20c0132f60SStefan Roese #define UTMI_PHY_CFG_PU_MASK \ 21c0132f60SStefan Roese (0x1 << UTMI_PHY_CFG_PU_OFFSET) 22c0132f60SStefan Roese 23c0132f60SStefan Roese #define UTMI_PLL_CTRL_REG 0x0 24c0132f60SStefan Roese #define UTMI_PLL_CTRL_REFDIV_OFFSET 0 25c0132f60SStefan Roese #define UTMI_PLL_CTRL_REFDIV_MASK \ 26c0132f60SStefan Roese (0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET) 27c0132f60SStefan Roese #define UTMI_PLL_CTRL_FBDIV_OFFSET 16 28c0132f60SStefan Roese #define UTMI_PLL_CTRL_FBDIV_MASK \ 29c0132f60SStefan Roese (0x1FF << UTMI_PLL_CTRL_FBDIV_OFFSET) 30c0132f60SStefan Roese #define UTMI_PLL_CTRL_SEL_LPFR_OFFSET 28 31c0132f60SStefan Roese #define UTMI_PLL_CTRL_SEL_LPFR_MASK \ 32c0132f60SStefan Roese (0x3 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET) 33c0132f60SStefan Roese #define UTMI_PLL_CTRL_PLL_RDY_OFFSET 31 34c0132f60SStefan Roese #define UTMI_PLL_CTRL_PLL_RDY_MASK \ 35c0132f60SStefan Roese (0x1 << UTMI_PLL_CTRL_PLL_RDY_OFFSET) 36c0132f60SStefan Roese 37c0132f60SStefan Roese #define UTMI_CALIB_CTRL_REG 0x8 38c0132f60SStefan Roese #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 39c0132f60SStefan Roese #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \ 40c0132f60SStefan Roese (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) 41c0132f60SStefan Roese #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 42c0132f60SStefan Roese #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \ 43c0132f60SStefan Roese (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) 44c0132f60SStefan Roese #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 45c0132f60SStefan Roese #define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \ 46c0132f60SStefan Roese (0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET) 47c0132f60SStefan Roese 48c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_REG 0xC 49c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12 50c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \ 51c0132f60SStefan Roese (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) 52c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 53c0132f60SStefan Roese #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \ 54c0132f60SStefan Roese (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) 55c0132f60SStefan Roese 56c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_REG 0x14 57c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 58c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_SQ_DET_MASK \ 59c0132f60SStefan Roese (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) 60c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 61c0132f60SStefan Roese #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \ 62c0132f60SStefan Roese (0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET) 63c0132f60SStefan Roese 64c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_REG 0x18 65c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 66c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \ 67c0132f60SStefan Roese (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) 68c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 69c0132f60SStefan Roese #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \ 70c0132f60SStefan Roese (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) 71c0132f60SStefan Roese 72c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_REG 0x24 73c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22 74c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_SUSPENDM_MASK \ 75c0132f60SStefan Roese (0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET) 76c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET 25 77c0132f60SStefan Roese #define UTMI_CTRL_STATUS0_TEST_SEL_MASK \ 78c0132f60SStefan Roese (0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET) 79c0132f60SStefan Roese 80c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_REG 0x38 81c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8 82c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_VDAT_MASK \ 83c0132f60SStefan Roese (0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET) 84c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_VSRC_OFFSET 10 85c0132f60SStefan Roese #define UTMI_CHGDTC_CTRL_VSRC_MASK \ 86c0132f60SStefan Roese (0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET) 87c0132f60SStefan Roese 88c0132f60SStefan Roese #endif /* _UTMI_PHY_H_ */ 89c0132f60SStefan Roese 90