1*c0132f60SStefan Roese /* 2*c0132f60SStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 3*c0132f60SStefan Roese * 4*c0132f60SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5*c0132f60SStefan Roese */ 6*c0132f60SStefan Roese 7*c0132f60SStefan Roese #ifndef _SATA_H_ 8*c0132f60SStefan Roese #define _SATA_H_ 9*c0132f60SStefan Roese 10*c0132f60SStefan Roese /* SATA3 Unit address */ 11*c0132f60SStefan Roese #define SATA3_VENDOR_ADDRESS 0xA0 12*c0132f60SStefan Roese #define SATA3_VENDOR_ADDR_OFSSET 0 13*c0132f60SStefan Roese #define SATA3_VENDOR_ADDR_MASK (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET) 14*c0132f60SStefan Roese #define SATA3_VENDOR_DATA 0xA4 15*c0132f60SStefan Roese 16*c0132f60SStefan Roese #define SATA_CONTROL_REG 0x0 17*c0132f60SStefan Roese #define SATA3_CTRL_SATA0_PD_OFFSET 6 18*c0132f60SStefan Roese #define SATA3_CTRL_SATA0_PD_MASK (1 << SATA3_CTRL_SATA0_PD_OFFSET) 19*c0132f60SStefan Roese #define SATA3_CTRL_SATA1_PD_OFFSET 14 20*c0132f60SStefan Roese #define SATA3_CTRL_SATA1_PD_MASK (1 << SATA3_CTRL_SATA1_PD_OFFSET) 21*c0132f60SStefan Roese #define SATA3_CTRL_SATA1_ENABLE_OFFSET 22 22*c0132f60SStefan Roese #define SATA3_CTRL_SATA1_ENABLE_MASK (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET) 23*c0132f60SStefan Roese #define SATA3_CTRL_SATA_SSU_OFFSET 23 24*c0132f60SStefan Roese #define SATA3_CTRL_SATA_SSU_MASK (1 << SATA3_CTRL_SATA_SSU_OFFSET) 25*c0132f60SStefan Roese 26*c0132f60SStefan Roese #define SATA_MBUS_SIZE_SELECT_REG 0x4 27*c0132f60SStefan Roese #define SATA_MBUS_REGRET_EN_OFFSET 7 28*c0132f60SStefan Roese #define SATA_MBUS_REGRET_EN_MASK (0x1 << SATA_MBUS_REGRET_EN_OFFSET) 29*c0132f60SStefan Roese 30*c0132f60SStefan Roese #endif /* _SATA_H_ */ 31