1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c0132f60SStefan Roese /* 3c0132f60SStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 4c0132f60SStefan Roese */ 5c0132f60SStefan Roese 6c0132f60SStefan Roese #ifndef _SATA_H_ 7c0132f60SStefan Roese #define _SATA_H_ 8c0132f60SStefan Roese 9c0132f60SStefan Roese /* SATA3 Unit address */ 10c0132f60SStefan Roese #define SATA3_VENDOR_ADDRESS 0xA0 11c0132f60SStefan Roese #define SATA3_VENDOR_ADDR_OFSSET 0 12c0132f60SStefan Roese #define SATA3_VENDOR_ADDR_MASK (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET) 13c0132f60SStefan Roese #define SATA3_VENDOR_DATA 0xA4 14c0132f60SStefan Roese 15c0132f60SStefan Roese #define SATA_CONTROL_REG 0x0 16c0132f60SStefan Roese #define SATA3_CTRL_SATA0_PD_OFFSET 6 17c0132f60SStefan Roese #define SATA3_CTRL_SATA0_PD_MASK (1 << SATA3_CTRL_SATA0_PD_OFFSET) 18c0132f60SStefan Roese #define SATA3_CTRL_SATA1_PD_OFFSET 14 19c0132f60SStefan Roese #define SATA3_CTRL_SATA1_PD_MASK (1 << SATA3_CTRL_SATA1_PD_OFFSET) 20c0132f60SStefan Roese #define SATA3_CTRL_SATA1_ENABLE_OFFSET 22 21c0132f60SStefan Roese #define SATA3_CTRL_SATA1_ENABLE_MASK (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET) 22c0132f60SStefan Roese #define SATA3_CTRL_SATA_SSU_OFFSET 23 23c0132f60SStefan Roese #define SATA3_CTRL_SATA_SSU_MASK (1 << SATA3_CTRL_SATA_SSU_OFFSET) 24c0132f60SStefan Roese 25c0132f60SStefan Roese #define SATA_MBUS_SIZE_SELECT_REG 0x4 26c0132f60SStefan Roese #define SATA_MBUS_REGRET_EN_OFFSET 7 27c0132f60SStefan Roese #define SATA_MBUS_REGRET_EN_MASK (0x1 << SATA_MBUS_REGRET_EN_OFFSET) 28c0132f60SStefan Roese 29c0132f60SStefan Roese #endif /* _SATA_H_ */ 30