1 /* 2 * Copyright (C) 2015-2016 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #include "comphy.h" 14 #include "comphy_hpipe.h" 15 #include "sata.h" 16 #include "utmi_phy.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define SD_ADDR(base, lane) (base + 0x1000 * lane) 21 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) 22 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) 23 24 struct utmi_phy_data { 25 void __iomem *utmi_base_addr; 26 void __iomem *usb_cfg_addr; 27 void __iomem *utmi_cfg_addr; 28 u32 utmi_phy_port; 29 }; 30 31 /* 32 * For CP-110 we have 2 Selector registers "PHY Selectors", 33 * and "PIPE Selectors". 34 * PIPE selector include USB and PCIe options. 35 * PHY selector include the Ethernet and SATA options, every Ethernet 36 * option has different options, for example: serdes lane2 had option 37 * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI) 38 */ 39 struct comphy_mux_data cp110_comphy_phy_mux_data[] = { 40 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ 41 {PHY_TYPE_SATA1, 0x4} } }, 42 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ 43 {PHY_TYPE_SATA0, 0x4} } }, 44 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ 45 {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, 46 {PHY_TYPE_SATA0, 0x4} } }, 47 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ 48 {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, 49 {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 4 */ 50 {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, 51 {PHY_TYPE_SGMII1, 0x2} } }, 52 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ 53 {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, 54 }; 55 56 struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { 57 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ 58 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ 59 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, 60 {PHY_TYPE_PEX0, 0x4} } }, 61 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ 62 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, 63 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ 64 {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, 65 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ 66 {PHY_TYPE_USB3_HOST1, 0x1}, 67 {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, 68 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ 69 }; 70 71 static u32 polling_with_timeout(void __iomem *addr, u32 val, 72 u32 mask, unsigned long usec_timout) 73 { 74 u32 data; 75 76 do { 77 udelay(1); 78 data = readl(addr) & mask; 79 } while (data != val && --usec_timout > 0); 80 81 if (usec_timout == 0) 82 return data; 83 84 return 0; 85 } 86 87 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, 88 bool is_end_point, void __iomem *hpipe_base, 89 void __iomem *comphy_base) 90 { 91 u32 mask, data, ret = 1; 92 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 93 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 94 void __iomem *addr; 95 u32 pcie_clk = 0; /* set input by default */ 96 97 debug_enter(); 98 99 /* 100 * ToDo: 101 * Add SAR (Sample-At-Reset) configuration for the PCIe clock 102 * direction. SAR code is currently not ported from Marvell 103 * U-Boot to mainline version. 104 * 105 * SerDes Lane 4/5 got the PCIe ref-clock #1, 106 * and SerDes Lane 0 got PCIe ref-clock #0 107 */ 108 debug("PCIe clock = %x\n", pcie_clk); 109 debug("PCIe RC = %d\n", !is_end_point); 110 debug("PCIe width = %d\n", pcie_width); 111 112 /* enable PCIe by4 and by2 */ 113 if (lane == 0) { 114 if (pcie_width == 4) { 115 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 116 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET, 117 COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); 118 } else if (pcie_width == 2) { 119 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 120 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET, 121 COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); 122 } 123 } 124 125 /* 126 * If PCIe clock is output and clock source from SerDes lane 5, 127 * we need to configure the clock-source MUX. 128 * By default, the clock source is from lane 4 129 */ 130 if (pcie_clk && clk_src && (lane == 5)) { 131 reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, 132 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET, 133 DFX_DEV_GEN_PCIE_CLK_SRC_MASK); 134 } 135 136 debug("stage: RFU configurations - hard reset comphy\n"); 137 /* RFU configurations - hard reset comphy */ 138 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 139 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 140 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 141 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 142 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 143 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 144 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 145 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 146 mask |= COMMON_PHY_PHY_MODE_MASK; 147 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; 148 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 149 150 /* release from hard reset */ 151 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 152 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 153 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 154 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 155 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 156 157 /* Wait 1ms - until band gap and ref clock ready */ 158 mdelay(1); 159 /* Start comphy Configuration */ 160 debug("stage: Comphy configuration\n"); 161 /* Set PIPE soft reset */ 162 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; 163 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; 164 /* Set PHY datapath width mode for V0 */ 165 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; 166 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; 167 /* Set Data bus width USB mode for V0 */ 168 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; 169 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; 170 /* Set CORE_CLK output frequency for 250Mhz */ 171 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; 172 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; 173 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); 174 /* Set PLL ready delay for 0x2 */ 175 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; 176 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; 177 if (pcie_width != 1) { 178 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; 179 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; 180 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; 181 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; 182 } 183 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); 184 185 /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ 186 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; 187 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; 188 if (pcie_width != 1) { 189 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; 190 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; 191 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; 192 if (lane == 0) { 193 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; 194 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; 195 } else if (lane == (pcie_width - 1)) { 196 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; 197 } 198 } 199 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); 200 /* Config update polarity equalization */ 201 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, 202 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, 203 HPIPE_CFG_UPDATE_POLARITY_MASK); 204 /* Set PIPE version 4 to mode enable */ 205 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, 206 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, 207 HPIPE_DFE_CTRL_28_PIPE4_MASK); 208 /* TODO: check if pcie clock is output/input - for bringup use input*/ 209 /* Enable PIN clock 100M_125M */ 210 mask = 0; 211 data = 0; 212 /* Only if clock is output, configure the clock-source mux */ 213 if (pcie_clk) { 214 mask |= HPIPE_MISC_CLK100M_125M_MASK; 215 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; 216 } 217 /* 218 * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz 219 * clock 220 */ 221 mask |= HPIPE_MISC_TXDCLK_2X_MASK; 222 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; 223 /* Enable 500MHz Clock */ 224 mask |= HPIPE_MISC_CLK500_EN_MASK; 225 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; 226 if (pcie_clk) { /* output */ 227 /* Set reference clock comes from group 1 */ 228 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 229 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 230 } else { 231 /* Set reference clock comes from group 2 */ 232 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 233 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; 234 } 235 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 236 if (pcie_clk) { /* output */ 237 /* Set reference frequcency select - 0x2 for 25MHz*/ 238 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 239 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 240 } else { 241 /* Set reference frequcency select - 0x0 for 100MHz*/ 242 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 243 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 244 } 245 /* Set PHY mode to PCIe */ 246 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 247 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 248 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 249 250 /* ref clock alignment */ 251 if (pcie_width != 1) { 252 mask = HPIPE_LANE_ALIGN_OFF_MASK; 253 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; 254 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); 255 } 256 257 /* 258 * Set the amount of time spent in the LoZ state - set for 0x7 only if 259 * the PCIe clock is output 260 */ 261 if (pcie_clk) { 262 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, 263 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, 264 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); 265 } 266 267 /* Set Maximal PHY Generation Setting(8Gbps) */ 268 mask = HPIPE_INTERFACE_GEN_MAX_MASK; 269 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; 270 /* Set Link Train Mode (Tx training control pins are used) */ 271 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; 272 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; 273 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); 274 275 /* Set Idle_sync enable */ 276 mask = HPIPE_PCIE_IDLE_SYNC_MASK; 277 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; 278 /* Select bits for PCIE Gen3(32bit) */ 279 mask |= HPIPE_PCIE_SEL_BITS_MASK; 280 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; 281 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); 282 283 /* Enable Tx_adapt_g1 */ 284 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; 285 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; 286 /* Enable Tx_adapt_gn1 */ 287 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; 288 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; 289 /* Disable Tx_adapt_g0 */ 290 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; 291 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; 292 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); 293 294 /* Set reg_tx_train_chk_init */ 295 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; 296 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; 297 /* Enable TX_COE_FM_PIN_PCIE3_EN */ 298 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; 299 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; 300 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); 301 302 debug("stage: TRx training parameters\n"); 303 /* Set Preset sweep configurations */ 304 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; 305 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; 306 307 mask |= HPIPE_TX_NUM_OF_PRESET_MASK; 308 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; 309 310 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; 311 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; 312 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); 313 314 /* Tx train start configuration */ 315 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; 316 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; 317 318 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; 319 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; 320 321 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; 322 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; 323 324 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; 325 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; 326 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); 327 328 /* Enable Tx train P2P */ 329 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; 330 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; 331 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); 332 333 /* Configure Tx train timeout */ 334 mask = HPIPE_TRX_TRAIN_TIMER_MASK; 335 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; 336 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); 337 338 /* Disable G0/G1/GN1 adaptation */ 339 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK 340 | HPIPE_TX_TRAIN_CTRL_G0_OFFSET; 341 data = 0; 342 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); 343 344 /* Disable DTL frequency loop */ 345 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 346 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 347 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 348 349 /* Configure G3 DFE */ 350 mask = HPIPE_G3_DFE_RES_MASK; 351 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; 352 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); 353 354 /* Force DFE resolution (use GEN table value) */ 355 mask = HPIPE_DFE_RES_FORCE_MASK; 356 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 357 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 358 359 /* Configure initial and final coefficient value for receiver */ 360 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; 361 data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; 362 363 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; 364 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; 365 366 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; 367 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; 368 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); 369 370 /* Trigger sampler enable pulse */ 371 mask = HPIPE_SMAPLER_MASK; 372 data = 0x1 << HPIPE_SMAPLER_OFFSET; 373 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 374 udelay(5); 375 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); 376 377 /* FFE resistor tuning for different bandwidth */ 378 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; 379 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; 380 381 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; 382 data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; 383 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); 384 385 if (!is_end_point) { 386 /* Set phy in root complex mode */ 387 mask = HPIPE_CFG_PHY_RC_EP_MASK; 388 data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; 389 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); 390 } 391 392 debug("stage: Comphy power up\n"); 393 394 /* 395 * For PCIe by4 or by2 - release from reset only after finish to 396 * configure all lanes 397 */ 398 if ((pcie_width == 1) || (lane == (pcie_width - 1))) { 399 u32 i, start_lane, end_lane; 400 401 if (pcie_width != 1) { 402 /* allows writing to all lanes in one write */ 403 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 404 0x0 << 405 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, 406 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); 407 start_lane = 0; 408 end_lane = pcie_width; 409 410 /* 411 * Release from PIPE soft reset 412 * for PCIe by4 or by2 - release from soft reset 413 * all lanes - can't use read modify write 414 */ 415 reg_set(HPIPE_ADDR(hpipe_base, 0) + 416 HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); 417 } else { 418 start_lane = lane; 419 end_lane = lane + 1; 420 421 /* 422 * Release from PIPE soft reset 423 * for PCIe by4 or by2 - release from soft reset 424 * all lanes 425 */ 426 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, 427 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, 428 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); 429 } 430 431 432 if (pcie_width != 1) { 433 /* disable writing to all lanes with one write */ 434 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 435 0x3210 << 436 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, 437 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); 438 } 439 440 debug("stage: Check PLL\n"); 441 /* Read lane status */ 442 for (i = start_lane; i < end_lane; i++) { 443 addr = HPIPE_ADDR(hpipe_base, i) + 444 HPIPE_LANE_STATUS1_REG; 445 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; 446 mask = data; 447 data = polling_with_timeout(addr, data, mask, 15000); 448 if (data != 0) { 449 debug("Read from reg = %p - value = 0x%x\n", 450 hpipe_addr + HPIPE_LANE_STATUS1_REG, 451 data); 452 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); 453 ret = 0; 454 } 455 } 456 } 457 458 debug_exit(); 459 return ret; 460 } 461 462 static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, 463 void __iomem *comphy_base) 464 { 465 u32 mask, data, ret = 1; 466 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 467 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 468 void __iomem *addr; 469 470 debug_enter(); 471 debug("stage: RFU configurations - hard reset comphy\n"); 472 /* RFU configurations - hard reset comphy */ 473 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 474 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 475 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 476 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 477 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 478 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 479 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 480 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 481 mask |= COMMON_PHY_PHY_MODE_MASK; 482 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; 483 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 484 485 /* release from hard reset */ 486 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 487 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 488 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 489 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 490 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 491 492 /* Wait 1ms - until band gap and ref clock ready */ 493 mdelay(1); 494 495 /* Start comphy Configuration */ 496 debug("stage: Comphy configuration\n"); 497 /* Set PIPE soft reset */ 498 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; 499 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; 500 /* Set PHY datapath width mode for V0 */ 501 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; 502 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; 503 /* Set Data bus width USB mode for V0 */ 504 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; 505 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; 506 /* Set CORE_CLK output frequency for 250Mhz */ 507 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; 508 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; 509 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); 510 /* Set PLL ready delay for 0x2 */ 511 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, 512 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, 513 HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); 514 /* Set reference clock to come from group 1 - 25Mhz */ 515 reg_set(hpipe_addr + HPIPE_MISC_REG, 516 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 517 HPIPE_MISC_REFCLK_SEL_MASK); 518 /* Set reference frequcency select - 0x2 */ 519 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 520 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 521 /* Set PHY mode to USB - 0x5 */ 522 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 523 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 524 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 525 /* Set the amount of time spent in the LoZ state - set for 0x7 */ 526 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, 527 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, 528 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); 529 /* Set max PHY generation setting - 5Gbps */ 530 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, 531 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, 532 HPIPE_INTERFACE_GEN_MAX_MASK); 533 /* Set select data width 20Bit (SEL_BITS[2:0]) */ 534 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 535 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, 536 HPIPE_LOOPBACK_SEL_MASK); 537 /* select de-emphasize 3.5db */ 538 reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, 539 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, 540 HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); 541 /* override tx margining from the MAC */ 542 reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, 543 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, 544 HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); 545 546 /* Start analog paramters from ETP(HW) */ 547 debug("stage: Analog paramters from ETP(HW)\n"); 548 /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ 549 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; 550 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; 551 /* Set Override PHY DFE control pins for 0x1 */ 552 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; 553 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; 554 /* Set Spread Spectrum Clock Enable fot 0x1 */ 555 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; 556 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; 557 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); 558 /* End of analog parameters */ 559 560 debug("stage: Comphy power up\n"); 561 /* Release from PIPE soft reset */ 562 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, 563 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, 564 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); 565 566 /* wait 15ms - for comphy calibration done */ 567 debug("stage: Check PLL\n"); 568 /* Read lane status */ 569 addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; 570 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; 571 mask = data; 572 data = polling_with_timeout(addr, data, mask, 15000); 573 if (data != 0) { 574 debug("Read from reg = %p - value = 0x%x\n", 575 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); 576 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); 577 ret = 0; 578 } 579 580 debug_exit(); 581 return ret; 582 } 583 584 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, 585 void __iomem *comphy_base, int comphy_index) 586 { 587 u32 mask, data, i, ret = 1; 588 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 589 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 590 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 591 void __iomem *addr; 592 void __iomem *sata_base = NULL; 593 int sata_node = -1; /* Set to -1 in order to read the first sata node */ 594 595 debug_enter(); 596 597 /* 598 * Assumption - each CP has only one SATA controller 599 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 600 * will return the first node always. 601 * In order to parse each CPs SATA node, fdt_node_offset_by_compatible 602 * must be called again (according to the CP id) 603 */ 604 for (i = 0; i < (comphy_index + 1); i++) 605 sata_node = fdt_node_offset_by_compatible( 606 gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); 607 608 if (sata_node == 0) { 609 error("SATA node not found in FDT\n"); 610 return 0; 611 } 612 613 sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent( 614 gd->fdt_blob, sata_node, "reg", 0, NULL, true); 615 if (sata_base == NULL) { 616 error("SATA address not found in FDT\n"); 617 return 0; 618 } 619 620 debug("SATA address found in FDT %p\n", sata_base); 621 622 debug("stage: MAC configuration - power down comphy\n"); 623 /* 624 * MAC configuration powe down comphy use indirect address for 625 * vendor spesific SATA control register 626 */ 627 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 628 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, 629 SATA3_VENDOR_ADDR_MASK); 630 /* SATA 0 power down */ 631 mask = SATA3_CTRL_SATA0_PD_MASK; 632 data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; 633 /* SATA 1 power down */ 634 mask |= SATA3_CTRL_SATA1_PD_MASK; 635 data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; 636 /* SATA SSU disable */ 637 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; 638 data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; 639 /* SATA port 1 disable */ 640 mask |= SATA3_CTRL_SATA_SSU_MASK; 641 data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; 642 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); 643 644 debug("stage: RFU configurations - hard reset comphy\n"); 645 /* RFU configurations - hard reset comphy */ 646 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 647 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 648 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 649 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 650 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 651 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 652 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 653 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 654 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 655 656 /* Set select data width 40Bit - SATA mode only */ 657 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, 658 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, 659 COMMON_PHY_CFG6_IF_40_SEL_MASK); 660 661 /* release from hard reset in SD external */ 662 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 663 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 664 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 665 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 666 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 667 668 /* Wait 1ms - until band gap and ref clock ready */ 669 mdelay(1); 670 671 debug("stage: Comphy configuration\n"); 672 /* Start comphy Configuration */ 673 /* Set reference clock to comes from group 1 - choose 25Mhz */ 674 reg_set(hpipe_addr + HPIPE_MISC_REG, 675 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 676 HPIPE_MISC_REFCLK_SEL_MASK); 677 /* Reference frequency select set 1 (for SATA = 25Mhz) */ 678 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 679 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 680 /* PHY mode select (set SATA = 0x0 */ 681 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 682 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 683 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 684 /* Set max PHY generation setting - 6Gbps */ 685 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, 686 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, 687 HPIPE_INTERFACE_GEN_MAX_MASK); 688 /* Set select data width 40Bit (SEL_BITS[2:0]) */ 689 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 690 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); 691 692 debug("stage: Analog paramters from ETP(HW)\n"); 693 /* Set analog parameters from ETP(HW) */ 694 /* G1 settings */ 695 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 696 data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 697 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 698 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 699 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; 700 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; 701 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; 702 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; 703 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; 704 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; 705 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 706 707 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; 708 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; 709 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; 710 data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; 711 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; 712 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; 713 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; 714 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; 715 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; 716 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; 717 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); 718 719 /* G2 settings */ 720 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; 721 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; 722 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; 723 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; 724 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; 725 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; 726 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; 727 data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; 728 mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; 729 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; 730 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); 731 732 /* G3 settings */ 733 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; 734 data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; 735 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; 736 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; 737 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; 738 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; 739 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; 740 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; 741 mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; 742 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; 743 mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; 744 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; 745 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; 746 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; 747 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); 748 749 /* DTL Control */ 750 mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; 751 data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; 752 mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; 753 data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; 754 mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 755 data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 756 mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; 757 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; 758 mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; 759 data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; 760 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; 761 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; 762 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; 763 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; 764 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 765 766 /* Trigger sampler enable pulse (by toggleing the bit) */ 767 mask = HPIPE_SMAPLER_MASK; 768 data = 0x1 << HPIPE_SMAPLER_OFFSET; 769 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 770 mask = HPIPE_SMAPLER_MASK; 771 data = 0x0 << HPIPE_SMAPLER_OFFSET; 772 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 773 774 /* VDD Calibration Control 3 */ 775 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; 776 data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; 777 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); 778 779 /* DFE Resolution Control */ 780 mask = HPIPE_DFE_RES_FORCE_MASK; 781 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 782 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 783 784 /* DFE F3-F5 Coefficient Control */ 785 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 786 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 787 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 788 data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 789 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 790 791 /* G3 Setting 3 */ 792 mask = HPIPE_G3_FFE_CAP_SEL_MASK; 793 data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; 794 mask |= HPIPE_G3_FFE_RES_SEL_MASK; 795 data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; 796 mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; 797 data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; 798 mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; 799 data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; 800 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; 801 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; 802 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); 803 804 /* G3 Setting 4 */ 805 mask = HPIPE_G3_DFE_RES_MASK; 806 data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; 807 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); 808 809 /* Offset Phase Control */ 810 mask = HPIPE_OS_PH_OFFSET_MASK; 811 data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; 812 mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; 813 data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; 814 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); 815 mask = HPIPE_OS_PH_VALID_MASK; 816 data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; 817 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); 818 mask = HPIPE_OS_PH_VALID_MASK; 819 data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; 820 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); 821 822 /* Set G1 TX amplitude and TX post emphasis value */ 823 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; 824 data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; 825 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; 826 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; 827 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; 828 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; 829 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; 830 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; 831 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); 832 833 /* Set G2 TX amplitude and TX post emphasis value */ 834 mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; 835 data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; 836 mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; 837 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; 838 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; 839 data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; 840 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; 841 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; 842 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); 843 844 /* Set G3 TX amplitude and TX post emphasis value */ 845 mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; 846 data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; 847 mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; 848 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; 849 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; 850 data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; 851 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; 852 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; 853 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; 854 data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; 855 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; 856 data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; 857 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); 858 859 /* SERDES External Configuration 2 register */ 860 mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; 861 data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; 862 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); 863 864 /* DFE reset sequence */ 865 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 866 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, 867 HPIPE_PWR_CTR_RST_DFE_MASK); 868 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 869 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, 870 HPIPE_PWR_CTR_RST_DFE_MASK); 871 /* SW reset for interupt logic */ 872 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 873 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, 874 HPIPE_PWR_CTR_SFT_RST_MASK); 875 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 876 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, 877 HPIPE_PWR_CTR_SFT_RST_MASK); 878 879 debug("stage: Comphy power up\n"); 880 /* 881 * MAC configuration power up comphy - power up PLL/TX/RX 882 * use indirect address for vendor spesific SATA control register 883 */ 884 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 885 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, 886 SATA3_VENDOR_ADDR_MASK); 887 /* SATA 0 power up */ 888 mask = SATA3_CTRL_SATA0_PD_MASK; 889 data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; 890 /* SATA 1 power up */ 891 mask |= SATA3_CTRL_SATA1_PD_MASK; 892 data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; 893 /* SATA SSU enable */ 894 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; 895 data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; 896 /* SATA port 1 enable */ 897 mask |= SATA3_CTRL_SATA_SSU_MASK; 898 data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; 899 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); 900 901 /* MBUS request size and interface select register */ 902 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 903 SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET, 904 SATA3_VENDOR_ADDR_MASK); 905 /* Mbus regret enable */ 906 reg_set(sata_base + SATA3_VENDOR_DATA, 907 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK); 908 909 debug("stage: Check PLL\n"); 910 911 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 912 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & 913 SD_EXTERNAL_STATUS0_PLL_RX_MASK; 914 mask = data; 915 data = polling_with_timeout(addr, data, mask, 15000); 916 if (data != 0) { 917 debug("Read from reg = %p - value = 0x%x\n", 918 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); 919 error("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n", 920 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), 921 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); 922 ret = 0; 923 } 924 925 debug_exit(); 926 return ret; 927 } 928 929 static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, 930 void __iomem *hpipe_base, 931 void __iomem *comphy_base) 932 { 933 u32 mask, data, ret = 1; 934 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 935 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 936 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 937 void __iomem *addr; 938 939 debug_enter(); 940 debug("stage: RFU configurations - hard reset comphy\n"); 941 /* RFU configurations - hard reset comphy */ 942 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 943 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 944 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 945 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 946 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 947 948 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 949 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 950 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 951 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 952 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 953 if (sgmii_speed == PHY_SPEED_1_25G) { 954 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 955 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 956 } else { 957 /* 3.125G */ 958 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 959 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 960 } 961 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 962 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 963 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 964 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 965 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 966 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 967 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 968 969 /* release from hard reset */ 970 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 971 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 972 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 973 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 974 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 975 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 976 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 977 978 /* release from hard reset */ 979 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 980 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 981 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 982 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 983 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 984 985 986 /* Wait 1ms - until band gap and ref clock ready */ 987 mdelay(1); 988 989 /* Start comphy Configuration */ 990 debug("stage: Comphy configuration\n"); 991 /* set reference clock */ 992 mask = HPIPE_MISC_REFCLK_SEL_MASK; 993 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 994 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 995 /* Power and PLL Control */ 996 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 997 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 998 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 999 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1000 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1001 /* Loopback register */ 1002 mask = HPIPE_LOOPBACK_SEL_MASK; 1003 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; 1004 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); 1005 /* rx control 1 */ 1006 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1007 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1008 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1009 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1010 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1011 /* DTL Control */ 1012 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 1013 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 1014 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 1015 1016 /* Set analog paramters from ETP(HW) - for now use the default datas */ 1017 debug("stage: Analog paramters from ETP(HW)\n"); 1018 1019 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, 1020 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, 1021 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); 1022 1023 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1024 /* SERDES External Configuration */ 1025 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1026 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1027 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1028 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1029 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1030 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1031 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1032 1033 /* check PLL rx & tx ready */ 1034 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1035 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1036 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1037 mask = data; 1038 data = polling_with_timeout(addr, data, mask, 15000); 1039 if (data != 0) { 1040 debug("Read from reg = %p - value = 0x%x\n", 1041 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1042 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1043 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1044 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1045 ret = 0; 1046 } 1047 1048 /* RX init */ 1049 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1050 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1051 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1052 1053 /* check that RX init done */ 1054 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1055 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1056 mask = data; 1057 data = polling_with_timeout(addr, data, mask, 100); 1058 if (data != 0) { 1059 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1060 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1061 ret = 0; 1062 } 1063 1064 debug("stage: RF Reset\n"); 1065 /* RF Reset */ 1066 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1067 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1068 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1069 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1070 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1071 1072 debug_exit(); 1073 return ret; 1074 } 1075 1076 static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, 1077 void __iomem *comphy_base, u32 speed) 1078 { 1079 u32 mask, data, ret = 1; 1080 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 1081 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 1082 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 1083 void __iomem *addr; 1084 1085 debug_enter(); 1086 debug("stage: RFU configurations - hard reset comphy\n"); 1087 /* RFU configurations - hard reset comphy */ 1088 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 1089 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 1090 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 1091 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 1092 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 1093 1094 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 1095 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1096 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1097 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 1098 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 1099 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 1100 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 1101 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1102 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1103 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1104 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1105 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 1106 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 1107 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1108 1109 /* release from hard reset */ 1110 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1111 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1112 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1113 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1114 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1115 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1116 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1117 1118 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1119 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1120 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1121 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1122 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1123 1124 1125 /* Wait 1ms - until band gap and ref clock ready */ 1126 mdelay(1); 1127 1128 /* Start comphy Configuration */ 1129 debug("stage: Comphy configuration\n"); 1130 /* set reference clock */ 1131 mask = HPIPE_MISC_ICP_FORCE_MASK; 1132 data = (speed == PHY_SPEED_5_15625G) ? 1133 (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : 1134 (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET); 1135 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 1136 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 1137 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 1138 /* Power and PLL Control */ 1139 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 1140 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 1141 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 1142 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1143 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1144 /* Loopback register */ 1145 mask = HPIPE_LOOPBACK_SEL_MASK; 1146 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; 1147 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); 1148 /* rx control 1 */ 1149 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1150 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1151 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1152 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1153 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1154 /* DTL Control */ 1155 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 1156 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 1157 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 1158 1159 /* Transmitter/Receiver Speed Divider Force */ 1160 if (speed == PHY_SPEED_5_15625G) { 1161 mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; 1162 data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; 1163 mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; 1164 data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; 1165 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; 1166 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; 1167 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; 1168 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; 1169 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); 1170 } 1171 1172 /* Set analog paramters from ETP(HW) */ 1173 debug("stage: Analog paramters from ETP(HW)\n"); 1174 /* SERDES External Configuration 2 */ 1175 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; 1176 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; 1177 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); 1178 /* 0x7-DFE Resolution control */ 1179 mask = HPIPE_DFE_RES_FORCE_MASK; 1180 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 1181 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 1182 /* 0xd-G1_Setting_0 */ 1183 if (speed == PHY_SPEED_5_15625G) { 1184 mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; 1185 data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; 1186 } else { 1187 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; 1188 data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; 1189 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; 1190 data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; 1191 } 1192 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); 1193 /* Genration 1 setting 2 (G1_Setting_2) */ 1194 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; 1195 data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; 1196 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; 1197 data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; 1198 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); 1199 /* Transmitter Slew Rate Control register (tx_reg1) */ 1200 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; 1201 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; 1202 mask |= HPIPE_TX_REG1_SLC_EN_MASK; 1203 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; 1204 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); 1205 /* Impedance Calibration Control register (cal_reg1) */ 1206 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; 1207 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; 1208 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; 1209 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; 1210 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); 1211 /* Generation 1 Setting 5 (g1_setting_5) */ 1212 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; 1213 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; 1214 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); 1215 /* 0xE-G1_Setting_1 */ 1216 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 1217 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 1218 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 1219 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 1220 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; 1221 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; 1222 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 1223 /* 0xA-DFE_Reg3 */ 1224 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 1225 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 1226 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 1227 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 1228 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 1229 1230 /* 0x111-G1_Setting_4 */ 1231 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; 1232 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; 1233 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); 1234 /* Genration 1 setting 3 (G1_Setting_3) */ 1235 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; 1236 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; 1237 if (speed == PHY_SPEED_5_15625G) { 1238 /* Force FFE (Feed Forward Equalization) to 5G */ 1239 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; 1240 data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; 1241 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; 1242 data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; 1243 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; 1244 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; 1245 } 1246 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); 1247 1248 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1249 /* SERDES External Configuration */ 1250 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1251 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1252 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1253 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1254 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1255 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1256 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1257 1258 1259 /* check PLL rx & tx ready */ 1260 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1261 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1262 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1263 mask = data; 1264 data = polling_with_timeout(addr, data, mask, 15000); 1265 if (data != 0) { 1266 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1267 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1268 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1269 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1270 ret = 0; 1271 } 1272 1273 /* RX init */ 1274 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1275 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1276 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1277 1278 1279 /* check that RX init done */ 1280 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1281 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1282 mask = data; 1283 data = polling_with_timeout(addr, data, mask, 100); 1284 if (data != 0) { 1285 debug("Read from reg = %p - value = 0x%x\n", 1286 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1287 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1288 ret = 0; 1289 } 1290 1291 debug("stage: RF Reset\n"); 1292 /* RF Reset */ 1293 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1294 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1295 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1296 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1297 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1298 1299 debug_exit(); 1300 return ret; 1301 } 1302 1303 static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, 1304 void __iomem *comphy_base) 1305 { 1306 u32 mask, data, ret = 1; 1307 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 1308 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 1309 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 1310 void __iomem *addr; 1311 1312 debug_enter(); 1313 debug("stage: RFU configurations - hard reset comphy\n"); 1314 /* RFU configurations - hard reset comphy */ 1315 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 1316 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 1317 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 1318 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 1319 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 1320 1321 if (lane == 2) { 1322 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 1323 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET, 1324 COMMON_PHY_SD_CTRL1_RXAUI0_MASK); 1325 } 1326 if (lane == 4) { 1327 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 1328 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET, 1329 COMMON_PHY_SD_CTRL1_RXAUI1_MASK); 1330 } 1331 1332 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 1333 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1334 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1335 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 1336 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 1337 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 1338 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 1339 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1340 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1341 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1342 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1343 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 1344 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 1345 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; 1346 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; 1347 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1348 1349 /* release from hard reset */ 1350 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1351 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1352 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1353 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1354 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1355 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1356 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1357 1358 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1359 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1360 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1361 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1362 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1363 1364 /* Wait 1ms - until band gap and ref clock ready */ 1365 mdelay(1); 1366 1367 /* Start comphy Configuration */ 1368 debug("stage: Comphy configuration\n"); 1369 /* set reference clock */ 1370 reg_set(hpipe_addr + HPIPE_MISC_REG, 1371 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 1372 HPIPE_MISC_REFCLK_SEL_MASK); 1373 /* Power and PLL Control */ 1374 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 1375 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 1376 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 1377 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1378 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1379 /* Loopback register */ 1380 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 1381 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); 1382 /* rx control 1 */ 1383 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1384 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1385 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1386 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1387 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1388 /* DTL Control */ 1389 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, 1390 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, 1391 HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); 1392 1393 /* Set analog paramters from ETP(HW) */ 1394 debug("stage: Analog paramters from ETP(HW)\n"); 1395 /* SERDES External Configuration 2 */ 1396 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, 1397 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, 1398 SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK); 1399 /* 0x7-DFE Resolution control */ 1400 reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET, 1401 HPIPE_DFE_RES_FORCE_MASK); 1402 /* 0xd-G1_Setting_0 */ 1403 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, 1404 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, 1405 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); 1406 /* 0xE-G1_Setting_1 */ 1407 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 1408 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 1409 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 1410 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 1411 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; 1412 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; 1413 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 1414 /* 0xA-DFE_Reg3 */ 1415 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 1416 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 1417 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 1418 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 1419 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 1420 1421 /* 0x111-G1_Setting_4 */ 1422 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; 1423 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; 1424 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); 1425 1426 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1427 /* SERDES External Configuration */ 1428 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1429 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1430 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1431 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1432 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1433 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1434 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1435 1436 1437 /* check PLL rx & tx ready */ 1438 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1439 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1440 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1441 mask = data; 1442 data = polling_with_timeout(addr, data, mask, 15000); 1443 if (data != 0) { 1444 debug("Read from reg = %p - value = 0x%x\n", 1445 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1446 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1447 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1448 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1449 ret = 0; 1450 } 1451 1452 /* RX init */ 1453 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, 1454 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET, 1455 SD_EXTERNAL_CONFIG1_RX_INIT_MASK); 1456 1457 /* check that RX init done */ 1458 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1459 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1460 mask = data; 1461 data = polling_with_timeout(addr, data, mask, 100); 1462 if (data != 0) { 1463 debug("Read from reg = %p - value = 0x%x\n", 1464 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1465 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1466 ret = 0; 1467 } 1468 1469 debug("stage: RF Reset\n"); 1470 /* RF Reset */ 1471 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1472 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1473 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1474 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1475 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1476 1477 debug_exit(); 1478 return ret; 1479 } 1480 1481 static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, 1482 void __iomem *usb_cfg_addr, 1483 void __iomem *utmi_cfg_addr, 1484 u32 utmi_phy_port) 1485 { 1486 u32 mask, data; 1487 1488 debug_enter(); 1489 debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", 1490 utmi_index); 1491 /* Power down UTMI PHY */ 1492 reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET, 1493 UTMI_PHY_CFG_PU_MASK); 1494 1495 /* 1496 * If UTMI connected to USB Device, configure mux prior to PHY init 1497 * (Device can be connected to UTMI0 or to UTMI1) 1498 */ 1499 if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) { 1500 debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", 1501 utmi_index); 1502 /* USB3 Device UTMI enable */ 1503 mask = UTMI_USB_CFG_DEVICE_EN_MASK; 1504 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; 1505 /* USB3 Device UTMI MUX */ 1506 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; 1507 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; 1508 reg_set(usb_cfg_addr, data, mask); 1509 } 1510 1511 /* Set Test suspendm mode */ 1512 mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; 1513 data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; 1514 /* Enable Test UTMI select */ 1515 mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; 1516 data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; 1517 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); 1518 1519 /* Wait for UTMI power down */ 1520 mdelay(1); 1521 1522 debug_exit(); 1523 return; 1524 } 1525 1526 static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, 1527 void __iomem *usb_cfg_addr, 1528 void __iomem *utmi_cfg_addr, 1529 u32 utmi_phy_port) 1530 { 1531 u32 mask, data; 1532 1533 debug_exit(); 1534 debug("stage: Configure UTMI PHY %d registers\n", utmi_index); 1535 /* Reference Clock Divider Select */ 1536 mask = UTMI_PLL_CTRL_REFDIV_MASK; 1537 data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; 1538 /* Feedback Clock Divider Select - 90 for 25Mhz*/ 1539 mask |= UTMI_PLL_CTRL_FBDIV_MASK; 1540 data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; 1541 /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ 1542 mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; 1543 data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; 1544 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); 1545 1546 /* Impedance Calibration Threshold Setting */ 1547 reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, 1548 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, 1549 UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); 1550 1551 /* Set LS TX driver strength coarse control */ 1552 mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; 1553 data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; 1554 /* Set LS TX driver fine adjustment */ 1555 mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; 1556 data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; 1557 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); 1558 1559 /* Enable SQ */ 1560 mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; 1561 data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; 1562 /* Enable analog squelch detect */ 1563 mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; 1564 data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; 1565 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); 1566 1567 /* Set External squelch calibration number */ 1568 mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; 1569 data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; 1570 /* Enable the External squelch calibration */ 1571 mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; 1572 data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; 1573 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); 1574 1575 /* Set Control VDAT Reference Voltage - 0.325V */ 1576 mask = UTMI_CHGDTC_CTRL_VDAT_MASK; 1577 data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; 1578 /* Set Control VSRC Reference Voltage - 0.6V */ 1579 mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; 1580 data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; 1581 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); 1582 1583 debug_exit(); 1584 return; 1585 } 1586 1587 static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, 1588 void __iomem *usb_cfg_addr, 1589 void __iomem *utmi_cfg_addr, u32 utmi_phy_port) 1590 { 1591 u32 data, mask, ret = 1; 1592 void __iomem *addr; 1593 1594 debug_enter(); 1595 debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", 1596 utmi_index); 1597 /* Power UP UTMI PHY */ 1598 reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET, 1599 UTMI_PHY_CFG_PU_MASK); 1600 /* Disable Test UTMI select */ 1601 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, 1602 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET, 1603 UTMI_CTRL_STATUS0_TEST_SEL_MASK); 1604 1605 debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); 1606 addr = utmi_base_addr + UTMI_CALIB_CTRL_REG; 1607 data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; 1608 mask = data; 1609 data = polling_with_timeout(addr, data, mask, 100); 1610 if (data != 0) { 1611 error("Impedance calibration is not done\n"); 1612 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1613 ret = 0; 1614 } 1615 1616 data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; 1617 mask = data; 1618 data = polling_with_timeout(addr, data, mask, 100); 1619 if (data != 0) { 1620 error("PLL calibration is not done\n"); 1621 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1622 ret = 0; 1623 } 1624 1625 addr = utmi_base_addr + UTMI_PLL_CTRL_REG; 1626 data = UTMI_PLL_CTRL_PLL_RDY_MASK; 1627 mask = data; 1628 data = polling_with_timeout(addr, data, mask, 100); 1629 if (data != 0) { 1630 error("PLL is not ready\n"); 1631 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1632 ret = 0; 1633 } 1634 1635 if (ret) 1636 debug("Passed\n"); 1637 else 1638 debug("\n"); 1639 1640 debug_exit(); 1641 return ret; 1642 } 1643 1644 /* 1645 * comphy_utmi_phy_init initialize the UTMI PHY 1646 * the init split in 3 parts: 1647 * 1. Power down transceiver and PLL 1648 * 2. UTMI PHY configure 1649 * 3. Powe up transceiver and PLL 1650 * Note: - Power down/up should be once for both UTMI PHYs 1651 * - comphy_dedicated_phys_init call this function if at least there is 1652 * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is 1653 * legal 1654 */ 1655 static void comphy_utmi_phy_init(u32 utmi_phy_count, 1656 struct utmi_phy_data *cp110_utmi_data) 1657 { 1658 u32 i; 1659 1660 debug_enter(); 1661 /* UTMI Power down */ 1662 for (i = 0; i < utmi_phy_count; i++) { 1663 comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr, 1664 cp110_utmi_data[i].usb_cfg_addr, 1665 cp110_utmi_data[i].utmi_cfg_addr, 1666 cp110_utmi_data[i].utmi_phy_port); 1667 } 1668 /* PLL Power down */ 1669 debug("stage: UTMI PHY power down PLL\n"); 1670 for (i = 0; i < utmi_phy_count; i++) { 1671 reg_set(cp110_utmi_data[i].usb_cfg_addr, 1672 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); 1673 } 1674 /* UTMI configure */ 1675 for (i = 0; i < utmi_phy_count; i++) { 1676 comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr, 1677 cp110_utmi_data[i].usb_cfg_addr, 1678 cp110_utmi_data[i].utmi_cfg_addr, 1679 cp110_utmi_data[i].utmi_phy_port); 1680 } 1681 /* UTMI Power up */ 1682 for (i = 0; i < utmi_phy_count; i++) { 1683 if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr, 1684 cp110_utmi_data[i].usb_cfg_addr, 1685 cp110_utmi_data[i].utmi_cfg_addr, 1686 cp110_utmi_data[i].utmi_phy_port)) { 1687 error("Failed to initialize UTMI PHY %d\n", i); 1688 continue; 1689 } 1690 printf("UTMI PHY %d initialized to ", i); 1691 if (cp110_utmi_data[i].utmi_phy_port == 1692 UTMI_PHY_TO_USB3_DEVICE0) 1693 printf("USB Device\n"); 1694 else 1695 printf("USB Host%d\n", 1696 cp110_utmi_data[i].utmi_phy_port); 1697 } 1698 /* PLL Power up */ 1699 debug("stage: UTMI PHY power up PLL\n"); 1700 for (i = 0; i < utmi_phy_count; i++) { 1701 reg_set(cp110_utmi_data[i].usb_cfg_addr, 1702 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); 1703 } 1704 1705 debug_exit(); 1706 return; 1707 } 1708 1709 /* 1710 * comphy_dedicated_phys_init initialize the dedicated PHYs 1711 * - not muxed SerDes lanes e.g. UTMI PHY 1712 */ 1713 void comphy_dedicated_phys_init(void) 1714 { 1715 struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; 1716 int node; 1717 int i; 1718 1719 debug_enter(); 1720 debug("Initialize USB UTMI PHYs\n"); 1721 1722 /* Find the UTMI phy node in device tree and go over them */ 1723 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 1724 "marvell,mvebu-utmi-2.6.0"); 1725 1726 i = 0; 1727 while (node > 0) { 1728 /* get base address of UTMI phy */ 1729 cp110_utmi_data[i].utmi_base_addr = 1730 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1731 gd->fdt_blob, node, "reg", 0, NULL, true); 1732 if (cp110_utmi_data[i].utmi_base_addr == NULL) { 1733 error("UTMI PHY base address is invalid\n"); 1734 i++; 1735 continue; 1736 } 1737 1738 /* get usb config address */ 1739 cp110_utmi_data[i].usb_cfg_addr = 1740 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1741 gd->fdt_blob, node, "reg", 1, NULL, true); 1742 if (cp110_utmi_data[i].usb_cfg_addr == NULL) { 1743 error("UTMI PHY base address is invalid\n"); 1744 i++; 1745 continue; 1746 } 1747 1748 /* get UTMI config address */ 1749 cp110_utmi_data[i].utmi_cfg_addr = 1750 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1751 gd->fdt_blob, node, "reg", 2, NULL, true); 1752 if (cp110_utmi_data[i].utmi_cfg_addr == NULL) { 1753 error("UTMI PHY base address is invalid\n"); 1754 i++; 1755 continue; 1756 } 1757 1758 /* 1759 * get the port number (to check if the utmi connected to 1760 * host/device) 1761 */ 1762 cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int( 1763 gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); 1764 if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) { 1765 error("UTMI PHY port type is invalid\n"); 1766 i++; 1767 continue; 1768 } 1769 1770 node = fdt_node_offset_by_compatible( 1771 gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); 1772 i++; 1773 } 1774 1775 if (i > 0) 1776 comphy_utmi_phy_init(i, cp110_utmi_data); 1777 1778 debug_exit(); 1779 } 1780 1781 static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, 1782 struct comphy_map *serdes_map) 1783 { 1784 void __iomem *comphy_base_addr; 1785 struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS]; 1786 struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS]; 1787 u32 lane, comphy_max_count; 1788 1789 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; 1790 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; 1791 1792 /* 1793 * Copy the SerDes map configuration for PIPE map and PHY map 1794 * the comphy_mux_init modify the type of the lane if the type 1795 * is not valid because we have 2 selectores run the 1796 * comphy_mux_init twice and after that update the original 1797 * serdes_map 1798 */ 1799 for (lane = 0; lane < comphy_max_count; lane++) { 1800 comphy_map_pipe_data[lane].type = serdes_map[lane].type; 1801 comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; 1802 comphy_map_phy_data[lane].type = serdes_map[lane].type; 1803 comphy_map_phy_data[lane].speed = serdes_map[lane].speed; 1804 } 1805 ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; 1806 comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data, 1807 comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET); 1808 1809 ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; 1810 comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data, 1811 comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); 1812 /* Fix the type after check the PHY and PIPE configuration */ 1813 for (lane = 0; lane < comphy_max_count; lane++) { 1814 if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && 1815 (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) 1816 serdes_map[lane].type = PHY_TYPE_UNCONNECTED; 1817 } 1818 } 1819 1820 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, 1821 struct comphy_map *serdes_map) 1822 { 1823 struct comphy_map *ptr_comphy_map; 1824 void __iomem *comphy_base_addr, *hpipe_base_addr; 1825 u32 comphy_max_count, lane, ret = 0; 1826 u32 pcie_width = 0; 1827 1828 debug_enter(); 1829 1830 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; 1831 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; 1832 hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; 1833 1834 /* Config Comphy mux configuration */ 1835 comphy_mux_cp110_init(ptr_chip_cfg, serdes_map); 1836 1837 /* Check if the first 4 lanes configured as By-4 */ 1838 for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; 1839 lane++, ptr_comphy_map++) { 1840 if (ptr_comphy_map->type != PHY_TYPE_PEX0) 1841 break; 1842 pcie_width++; 1843 } 1844 1845 for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; 1846 lane++, ptr_comphy_map++) { 1847 debug("Initialize serdes number %d\n", lane); 1848 debug("Serdes type = 0x%x\n", ptr_comphy_map->type); 1849 if (lane == 4) { 1850 /* 1851 * PCIe lanes above the first 4 lanes, can be only 1852 * by1 1853 */ 1854 pcie_width = 1; 1855 } 1856 switch (ptr_comphy_map->type) { 1857 case PHY_TYPE_UNCONNECTED: 1858 case PHY_TYPE_IGNORE: 1859 continue; 1860 break; 1861 case PHY_TYPE_PEX0: 1862 case PHY_TYPE_PEX1: 1863 case PHY_TYPE_PEX2: 1864 case PHY_TYPE_PEX3: 1865 ret = comphy_pcie_power_up( 1866 lane, pcie_width, ptr_comphy_map->clk_src, 1867 serdes_map->end_point, 1868 hpipe_base_addr, comphy_base_addr); 1869 break; 1870 case PHY_TYPE_SATA0: 1871 case PHY_TYPE_SATA1: 1872 case PHY_TYPE_SATA2: 1873 case PHY_TYPE_SATA3: 1874 ret = comphy_sata_power_up( 1875 lane, hpipe_base_addr, comphy_base_addr, 1876 ptr_chip_cfg->comphy_index); 1877 break; 1878 case PHY_TYPE_USB3_HOST0: 1879 case PHY_TYPE_USB3_HOST1: 1880 case PHY_TYPE_USB3_DEVICE: 1881 ret = comphy_usb3_power_up(lane, hpipe_base_addr, 1882 comphy_base_addr); 1883 break; 1884 case PHY_TYPE_SGMII0: 1885 case PHY_TYPE_SGMII1: 1886 case PHY_TYPE_SGMII2: 1887 case PHY_TYPE_SGMII3: 1888 if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { 1889 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", 1890 lane); 1891 ptr_comphy_map->speed = PHY_SPEED_1_25G; 1892 } 1893 ret = comphy_sgmii_power_up( 1894 lane, ptr_comphy_map->speed, hpipe_base_addr, 1895 comphy_base_addr); 1896 break; 1897 case PHY_TYPE_SFI: 1898 ret = comphy_sfi_power_up(lane, hpipe_base_addr, 1899 comphy_base_addr, 1900 ptr_comphy_map->speed); 1901 break; 1902 case PHY_TYPE_RXAUI0: 1903 case PHY_TYPE_RXAUI1: 1904 ret = comphy_rxauii_power_up(lane, hpipe_base_addr, 1905 comphy_base_addr); 1906 break; 1907 default: 1908 debug("Unknown SerDes type, skip initialize SerDes %d\n", 1909 lane); 1910 break; 1911 } 1912 if (ret == 0) { 1913 /* 1914 * If interface wans't initialized, set the lane to 1915 * PHY_TYPE_UNCONNECTED state. 1916 */ 1917 ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; 1918 error("PLL is not locked - Failed to initialize lane %d\n", 1919 lane); 1920 } 1921 } 1922 1923 debug_exit(); 1924 return 0; 1925 } 1926