1 /* 2 * Copyright (C) 2015-2016 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #include "comphy.h" 14 #include "comphy_hpipe.h" 15 #include "sata.h" 16 #include "utmi_phy.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define SD_ADDR(base, lane) (base + 0x1000 * lane) 21 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) 22 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) 23 24 struct utmi_phy_data { 25 void __iomem *utmi_base_addr; 26 void __iomem *usb_cfg_addr; 27 void __iomem *utmi_cfg_addr; 28 u32 utmi_phy_port; 29 }; 30 31 /* 32 * For CP-110 we have 2 Selector registers "PHY Selectors", 33 * and "PIPE Selectors". 34 * PIPE selector include USB and PCIe options. 35 * PHY selector include the Ethernet and SATA options, every Ethernet 36 * option has different options, for example: serdes lane2 had option 37 * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, KR) 38 */ 39 struct comphy_mux_data cp110_comphy_phy_mux_data[] = { 40 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */ 41 {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, 42 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, /* Lane 1 */ 43 {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, 44 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ 45 {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, 46 {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, 47 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */ 48 {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, 49 {PHY_TYPE_KR, 0x1}, {PHY_TYPE_XAUI1, 0x1}, 50 {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, 51 {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ 52 {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, 53 {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, 54 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */ 55 {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, 56 {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, 57 }; 58 59 struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { 60 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ 61 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ 62 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, 63 {PHY_TYPE_PEX0, 0x4} } }, 64 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ 65 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, 66 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ 67 {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, 68 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ 69 {PHY_TYPE_USB3_HOST1, 0x1}, 70 {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, 71 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ 72 }; 73 74 static u32 polling_with_timeout(void __iomem *addr, u32 val, 75 u32 mask, unsigned long usec_timout) 76 { 77 u32 data; 78 79 do { 80 udelay(1); 81 data = readl(addr) & mask; 82 } while (data != val && --usec_timout > 0); 83 84 if (usec_timout == 0) 85 return data; 86 87 return 0; 88 } 89 90 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, 91 bool clk_src, void __iomem *hpipe_base, 92 void __iomem *comphy_base) 93 { 94 u32 mask, data, ret = 1; 95 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 96 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 97 void __iomem *addr; 98 u32 pcie_clk = 0; /* set input by default */ 99 100 debug_enter(); 101 102 /* 103 * ToDo: 104 * Add SAR (Sample-At-Reset) configuration for the PCIe clock 105 * direction. SAR code is currently not ported from Marvell 106 * U-Boot to mainline version. 107 * 108 * SerDes Lane 4/5 got the PCIe ref-clock #1, 109 * and SerDes Lane 0 got PCIe ref-clock #0 110 */ 111 debug("PCIe clock = %x\n", pcie_clk); 112 debug("PCIe width = %d\n", pcie_width); 113 114 /* enable PCIe by4 and by2 */ 115 if (lane == 0) { 116 if (pcie_width == 4) { 117 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 118 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET, 119 COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); 120 } else if (pcie_width == 2) { 121 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 122 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET, 123 COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); 124 } 125 } 126 127 /* 128 * If PCIe clock is output and clock source from SerDes lane 5, 129 * we need to configure the clock-source MUX. 130 * By default, the clock source is from lane 4 131 */ 132 if (pcie_clk && clk_src && (lane == 5)) { 133 reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, 134 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET, 135 DFX_DEV_GEN_PCIE_CLK_SRC_MASK); 136 } 137 138 debug("stage: RFU configurations - hard reset comphy\n"); 139 /* RFU configurations - hard reset comphy */ 140 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 141 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 142 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 143 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 144 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 145 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 146 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 147 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 148 mask |= COMMON_PHY_PHY_MODE_MASK; 149 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; 150 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 151 152 /* release from hard reset */ 153 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 154 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 155 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 156 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 157 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 158 159 /* Wait 1ms - until band gap and ref clock ready */ 160 mdelay(1); 161 /* Start comphy Configuration */ 162 debug("stage: Comphy configuration\n"); 163 /* Set PIPE soft reset */ 164 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; 165 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; 166 /* Set PHY datapath width mode for V0 */ 167 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; 168 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; 169 /* Set Data bus width USB mode for V0 */ 170 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; 171 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; 172 /* Set CORE_CLK output frequency for 250Mhz */ 173 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; 174 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; 175 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); 176 /* Set PLL ready delay for 0x2 */ 177 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; 178 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; 179 if (pcie_width != 1) { 180 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; 181 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; 182 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; 183 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; 184 } 185 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); 186 187 /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ 188 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; 189 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; 190 if (pcie_width != 1) { 191 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; 192 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; 193 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; 194 if (lane == 0) { 195 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; 196 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; 197 } else if (lane == (pcie_width - 1)) { 198 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; 199 } 200 } 201 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); 202 /* Config update polarity equalization */ 203 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, 204 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, 205 HPIPE_CFG_UPDATE_POLARITY_MASK); 206 /* Set PIPE version 4 to mode enable */ 207 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, 208 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, 209 HPIPE_DFE_CTRL_28_PIPE4_MASK); 210 /* TODO: check if pcie clock is output/input - for bringup use input*/ 211 /* Enable PIN clock 100M_125M */ 212 mask = 0; 213 data = 0; 214 /* Only if clock is output, configure the clock-source mux */ 215 if (pcie_clk) { 216 mask |= HPIPE_MISC_CLK100M_125M_MASK; 217 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; 218 } 219 /* 220 * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz 221 * clock 222 */ 223 mask |= HPIPE_MISC_TXDCLK_2X_MASK; 224 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; 225 /* Enable 500MHz Clock */ 226 mask |= HPIPE_MISC_CLK500_EN_MASK; 227 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; 228 if (pcie_clk) { /* output */ 229 /* Set reference clock comes from group 1 */ 230 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 231 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 232 } else { 233 /* Set reference clock comes from group 2 */ 234 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 235 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; 236 } 237 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 238 if (pcie_clk) { /* output */ 239 /* Set reference frequcency select - 0x2 for 25MHz*/ 240 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 241 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 242 } else { 243 /* Set reference frequcency select - 0x0 for 100MHz*/ 244 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 245 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 246 } 247 /* Set PHY mode to PCIe */ 248 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 249 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 250 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 251 252 /* ref clock alignment */ 253 if (pcie_width != 1) { 254 mask = HPIPE_LANE_ALIGN_OFF_MASK; 255 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; 256 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); 257 } 258 259 /* 260 * Set the amount of time spent in the LoZ state - set for 0x7 only if 261 * the PCIe clock is output 262 */ 263 if (pcie_clk) { 264 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, 265 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, 266 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); 267 } 268 269 /* Set Maximal PHY Generation Setting(8Gbps) */ 270 mask = HPIPE_INTERFACE_GEN_MAX_MASK; 271 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; 272 /* Set Link Train Mode (Tx training control pins are used) */ 273 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; 274 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; 275 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); 276 277 /* Set Idle_sync enable */ 278 mask = HPIPE_PCIE_IDLE_SYNC_MASK; 279 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; 280 /* Select bits for PCIE Gen3(32bit) */ 281 mask |= HPIPE_PCIE_SEL_BITS_MASK; 282 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; 283 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); 284 285 /* Enable Tx_adapt_g1 */ 286 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; 287 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; 288 /* Enable Tx_adapt_gn1 */ 289 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; 290 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; 291 /* Disable Tx_adapt_g0 */ 292 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; 293 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; 294 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); 295 296 /* Set reg_tx_train_chk_init */ 297 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; 298 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; 299 /* Enable TX_COE_FM_PIN_PCIE3_EN */ 300 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; 301 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; 302 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); 303 304 debug("stage: TRx training parameters\n"); 305 /* Set Preset sweep configurations */ 306 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; 307 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; 308 309 mask |= HPIPE_TX_NUM_OF_PRESET_MASK; 310 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; 311 312 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; 313 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; 314 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); 315 316 /* Tx train start configuration */ 317 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; 318 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; 319 320 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; 321 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; 322 323 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; 324 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; 325 326 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; 327 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; 328 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); 329 330 /* Enable Tx train P2P */ 331 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; 332 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; 333 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); 334 335 /* Configure Tx train timeout */ 336 mask = HPIPE_TRX_TRAIN_TIMER_MASK; 337 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; 338 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); 339 340 /* Disable G0/G1/GN1 adaptation */ 341 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK 342 | HPIPE_TX_TRAIN_CTRL_G0_OFFSET; 343 data = 0; 344 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); 345 346 /* Disable DTL frequency loop */ 347 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 348 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 349 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 350 351 /* Configure G3 DFE */ 352 mask = HPIPE_G3_DFE_RES_MASK; 353 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; 354 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); 355 356 /* Force DFE resolution (use GEN table value) */ 357 mask = HPIPE_DFE_RES_FORCE_MASK; 358 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 359 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 360 361 /* Configure initial and final coefficient value for receiver */ 362 mask = HPIPE_G3_RX_SELMUPI_MASK; 363 data = 0x1 << HPIPE_G3_RX_SELMUPI_OFFSET; 364 365 mask |= HPIPE_G3_RX_SELMUPF_MASK; 366 data |= 0x1 << HPIPE_G3_RX_SELMUPF_OFFSET; 367 368 mask |= HPIPE_G3_SETTING_BIT_MASK; 369 data |= 0x0 << HPIPE_G3_SETTING_BIT_OFFSET; 370 reg_set(hpipe_addr + HPIPE_G3_SETTINGS_1_REG, data, mask); 371 372 /* Trigger sampler enable pulse */ 373 mask = HPIPE_SMAPLER_MASK; 374 data = 0x1 << HPIPE_SMAPLER_OFFSET; 375 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 376 udelay(5); 377 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); 378 379 /* FFE resistor tuning for different bandwidth */ 380 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; 381 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; 382 383 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; 384 data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; 385 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); 386 387 /* Set phy in root complex mode */ 388 mask = HPIPE_CFG_PHY_RC_EP_MASK; 389 data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; 390 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); 391 392 debug("stage: Comphy power up\n"); 393 394 /* 395 * For PCIe by4 or by2 - release from reset only after finish to 396 * configure all lanes 397 */ 398 if ((pcie_width == 1) || (lane == (pcie_width - 1))) { 399 u32 i, start_lane, end_lane; 400 401 if (pcie_width != 1) { 402 /* allows writing to all lanes in one write */ 403 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 404 0x0 << 405 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, 406 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); 407 start_lane = 0; 408 end_lane = pcie_width; 409 410 /* 411 * Release from PIPE soft reset 412 * for PCIe by4 or by2 - release from soft reset 413 * all lanes - can't use read modify write 414 */ 415 reg_set(HPIPE_ADDR(hpipe_base, 0) + 416 HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); 417 } else { 418 start_lane = lane; 419 end_lane = lane + 1; 420 421 /* 422 * Release from PIPE soft reset 423 * for PCIe by4 or by2 - release from soft reset 424 * all lanes 425 */ 426 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, 427 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, 428 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); 429 } 430 431 432 if (pcie_width != 1) { 433 /* disable writing to all lanes with one write */ 434 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 435 0x3210 << 436 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, 437 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); 438 } 439 440 debug("stage: Check PLL\n"); 441 /* Read lane status */ 442 for (i = start_lane; i < end_lane; i++) { 443 addr = HPIPE_ADDR(hpipe_base, i) + 444 HPIPE_LANE_STATUS1_REG; 445 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; 446 mask = data; 447 data = polling_with_timeout(addr, data, mask, 15000); 448 if (data != 0) { 449 debug("Read from reg = %p - value = 0x%x\n", 450 hpipe_addr + HPIPE_LANE_STATUS1_REG, 451 data); 452 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); 453 ret = 0; 454 } 455 } 456 } 457 458 debug_exit(); 459 return ret; 460 } 461 462 static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, 463 void __iomem *comphy_base) 464 { 465 u32 mask, data, ret = 1; 466 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 467 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 468 void __iomem *addr; 469 470 debug_enter(); 471 debug("stage: RFU configurations - hard reset comphy\n"); 472 /* RFU configurations - hard reset comphy */ 473 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 474 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 475 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 476 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 477 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 478 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 479 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 480 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 481 mask |= COMMON_PHY_PHY_MODE_MASK; 482 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; 483 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 484 485 /* release from hard reset */ 486 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 487 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 488 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 489 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 490 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 491 492 /* Wait 1ms - until band gap and ref clock ready */ 493 mdelay(1); 494 495 /* Start comphy Configuration */ 496 debug("stage: Comphy configuration\n"); 497 /* Set PIPE soft reset */ 498 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; 499 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; 500 /* Set PHY datapath width mode for V0 */ 501 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; 502 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; 503 /* Set Data bus width USB mode for V0 */ 504 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; 505 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; 506 /* Set CORE_CLK output frequency for 250Mhz */ 507 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; 508 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; 509 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); 510 /* Set PLL ready delay for 0x2 */ 511 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, 512 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, 513 HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); 514 /* Set reference clock to come from group 1 - 25Mhz */ 515 reg_set(hpipe_addr + HPIPE_MISC_REG, 516 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 517 HPIPE_MISC_REFCLK_SEL_MASK); 518 /* Set reference frequcency select - 0x2 */ 519 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 520 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 521 /* Set PHY mode to USB - 0x5 */ 522 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 523 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 524 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 525 /* Set the amount of time spent in the LoZ state - set for 0x7 */ 526 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, 527 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, 528 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); 529 /* Set max PHY generation setting - 5Gbps */ 530 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, 531 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, 532 HPIPE_INTERFACE_GEN_MAX_MASK); 533 /* Set select data width 20Bit (SEL_BITS[2:0]) */ 534 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 535 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, 536 HPIPE_LOOPBACK_SEL_MASK); 537 /* select de-emphasize 3.5db */ 538 reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, 539 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, 540 HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); 541 /* override tx margining from the MAC */ 542 reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, 543 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, 544 HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); 545 546 /* Start analog paramters from ETP(HW) */ 547 debug("stage: Analog paramters from ETP(HW)\n"); 548 /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ 549 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; 550 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; 551 /* Set Override PHY DFE control pins for 0x1 */ 552 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; 553 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; 554 /* Set Spread Spectrum Clock Enable fot 0x1 */ 555 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; 556 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; 557 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); 558 /* End of analog parameters */ 559 560 debug("stage: Comphy power up\n"); 561 /* Release from PIPE soft reset */ 562 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, 563 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, 564 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); 565 566 /* wait 15ms - for comphy calibration done */ 567 debug("stage: Check PLL\n"); 568 /* Read lane status */ 569 addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; 570 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; 571 mask = data; 572 data = polling_with_timeout(addr, data, mask, 15000); 573 if (data != 0) { 574 debug("Read from reg = %p - value = 0x%x\n", 575 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); 576 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); 577 ret = 0; 578 } 579 580 debug_exit(); 581 return ret; 582 } 583 584 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, 585 void __iomem *comphy_base, int comphy_index) 586 { 587 u32 mask, data, i, ret = 1; 588 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 589 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 590 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 591 void __iomem *addr; 592 void __iomem *sata_base = NULL; 593 int sata_node = -1; /* Set to -1 in order to read the first sata node */ 594 595 debug_enter(); 596 597 /* 598 * Assumption - each CP has only one SATA controller 599 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 600 * will return the first node always. 601 * In order to parse each CPs SATA node, fdt_node_offset_by_compatible 602 * must be called again (according to the CP id) 603 */ 604 for (i = 0; i < (comphy_index + 1); i++) 605 sata_node = fdt_node_offset_by_compatible( 606 gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); 607 608 if (sata_node == 0) { 609 error("SATA node not found in FDT\n"); 610 return 0; 611 } 612 613 sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent( 614 gd->fdt_blob, sata_node, "reg", 0, NULL, true); 615 if (sata_base == NULL) { 616 error("SATA address not found in FDT\n"); 617 return 0; 618 } 619 620 debug("SATA address found in FDT %p\n", sata_base); 621 622 debug("stage: MAC configuration - power down comphy\n"); 623 /* 624 * MAC configuration powe down comphy use indirect address for 625 * vendor spesific SATA control register 626 */ 627 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 628 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, 629 SATA3_VENDOR_ADDR_MASK); 630 /* SATA 0 power down */ 631 mask = SATA3_CTRL_SATA0_PD_MASK; 632 data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; 633 /* SATA 1 power down */ 634 mask |= SATA3_CTRL_SATA1_PD_MASK; 635 data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; 636 /* SATA SSU disable */ 637 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; 638 data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; 639 /* SATA port 1 disable */ 640 mask |= SATA3_CTRL_SATA_SSU_MASK; 641 data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; 642 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); 643 644 debug("stage: RFU configurations - hard reset comphy\n"); 645 /* RFU configurations - hard reset comphy */ 646 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 647 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 648 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 649 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 650 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 651 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 652 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 653 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 654 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 655 656 /* Set select data width 40Bit - SATA mode only */ 657 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, 658 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, 659 COMMON_PHY_CFG6_IF_40_SEL_MASK); 660 661 /* release from hard reset in SD external */ 662 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 663 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 664 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 665 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 666 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 667 668 /* Wait 1ms - until band gap and ref clock ready */ 669 mdelay(1); 670 671 debug("stage: Comphy configuration\n"); 672 /* Start comphy Configuration */ 673 /* Set reference clock to comes from group 1 - choose 25Mhz */ 674 reg_set(hpipe_addr + HPIPE_MISC_REG, 675 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 676 HPIPE_MISC_REFCLK_SEL_MASK); 677 /* Reference frequency select set 1 (for SATA = 25Mhz) */ 678 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 679 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 680 /* PHY mode select (set SATA = 0x0 */ 681 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 682 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 683 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 684 /* Set max PHY generation setting - 6Gbps */ 685 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, 686 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, 687 HPIPE_INTERFACE_GEN_MAX_MASK); 688 /* Set select data width 40Bit (SEL_BITS[2:0]) */ 689 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 690 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); 691 692 debug("stage: Analog paramters from ETP(HW)\n"); 693 /* 694 * TODO: Set analog paramters from ETP(HW) - for now use the 695 * default datas 696 */ 697 698 /* DFE reset sequence */ 699 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 700 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, 701 HPIPE_PWR_CTR_RST_DFE_MASK); 702 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 703 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, 704 HPIPE_PWR_CTR_RST_DFE_MASK); 705 /* SW reset for interupt logic */ 706 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 707 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, 708 HPIPE_PWR_CTR_SFT_RST_MASK); 709 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 710 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, 711 HPIPE_PWR_CTR_SFT_RST_MASK); 712 713 debug("stage: Comphy power up\n"); 714 /* 715 * MAC configuration power up comphy - power up PLL/TX/RX 716 * use indirect address for vendor spesific SATA control register 717 */ 718 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 719 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, 720 SATA3_VENDOR_ADDR_MASK); 721 /* SATA 0 power up */ 722 mask = SATA3_CTRL_SATA0_PD_MASK; 723 data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; 724 /* SATA 1 power up */ 725 mask |= SATA3_CTRL_SATA1_PD_MASK; 726 data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; 727 /* SATA SSU enable */ 728 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; 729 data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; 730 /* SATA port 1 enable */ 731 mask |= SATA3_CTRL_SATA_SSU_MASK; 732 data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; 733 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); 734 735 /* MBUS request size and interface select register */ 736 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 737 SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET, 738 SATA3_VENDOR_ADDR_MASK); 739 /* Mbus regret enable */ 740 reg_set(sata_base + SATA3_VENDOR_DATA, 741 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK); 742 743 debug("stage: Check PLL\n"); 744 745 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 746 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & 747 SD_EXTERNAL_STATUS0_PLL_RX_MASK; 748 mask = data; 749 data = polling_with_timeout(addr, data, mask, 15000); 750 if (data != 0) { 751 debug("Read from reg = %p - value = 0x%x\n", 752 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); 753 error("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n", 754 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), 755 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); 756 ret = 0; 757 } 758 759 debug_exit(); 760 return ret; 761 } 762 763 static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, 764 void __iomem *hpipe_base, 765 void __iomem *comphy_base) 766 { 767 u32 mask, data, ret = 1; 768 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 769 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 770 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 771 void __iomem *addr; 772 773 debug_enter(); 774 debug("stage: RFU configurations - hard reset comphy\n"); 775 /* RFU configurations - hard reset comphy */ 776 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 777 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 778 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 779 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 780 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 781 782 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 783 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 784 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 785 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 786 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 787 if (sgmii_speed == PHY_SPEED_1_25G) { 788 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 789 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 790 } else { 791 /* 3.125G */ 792 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 793 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 794 } 795 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 796 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 797 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 798 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 799 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 800 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 801 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 802 803 /* release from hard reset */ 804 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 805 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 806 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 807 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 808 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 809 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 810 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 811 812 /* release from hard reset */ 813 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 814 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 815 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 816 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 817 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 818 819 820 /* Wait 1ms - until band gap and ref clock ready */ 821 mdelay(1); 822 823 /* Start comphy Configuration */ 824 debug("stage: Comphy configuration\n"); 825 /* set reference clock */ 826 mask = HPIPE_MISC_REFCLK_SEL_MASK; 827 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 828 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 829 /* Power and PLL Control */ 830 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 831 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 832 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 833 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 834 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 835 /* Loopback register */ 836 mask = HPIPE_LOOPBACK_SEL_MASK; 837 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; 838 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); 839 /* rx control 1 */ 840 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 841 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 842 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 843 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 844 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 845 /* DTL Control */ 846 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 847 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 848 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 849 850 /* Set analog paramters from ETP(HW) - for now use the default datas */ 851 debug("stage: Analog paramters from ETP(HW)\n"); 852 853 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, 854 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, 855 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); 856 857 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 858 /* SERDES External Configuration */ 859 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 860 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 861 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 862 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 863 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 864 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 865 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 866 867 /* check PLL rx & tx ready */ 868 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 869 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 870 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 871 mask = data; 872 data = polling_with_timeout(addr, data, mask, 15000); 873 if (data != 0) { 874 debug("Read from reg = %p - value = 0x%x\n", 875 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 876 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 877 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 878 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 879 ret = 0; 880 } 881 882 /* RX init */ 883 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 884 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 885 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 886 887 /* check that RX init done */ 888 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 889 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 890 mask = data; 891 data = polling_with_timeout(addr, data, mask, 100); 892 if (data != 0) { 893 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 894 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 895 ret = 0; 896 } 897 898 debug("stage: RF Reset\n"); 899 /* RF Reset */ 900 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 901 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 902 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 903 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 904 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 905 906 debug_exit(); 907 return ret; 908 } 909 910 static int comphy_kr_power_up(u32 lane, void __iomem *hpipe_base, 911 void __iomem *comphy_base) 912 { 913 u32 mask, data, ret = 1; 914 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 915 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 916 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 917 void __iomem *addr; 918 919 debug_enter(); 920 debug("stage: RFU configurations - hard reset comphy\n"); 921 /* RFU configurations - hard reset comphy */ 922 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 923 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 924 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 925 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 926 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 927 928 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 929 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 930 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 931 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 932 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 933 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 934 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 935 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 936 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 937 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 938 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 939 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 940 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 941 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 942 943 /* release from hard reset */ 944 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 945 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 946 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 947 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 948 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 949 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 950 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 951 952 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 953 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 954 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 955 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 956 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 957 958 959 /* Wait 1ms - until band gap and ref clock ready */ 960 mdelay(1); 961 962 /* Start comphy Configuration */ 963 debug("stage: Comphy configuration\n"); 964 /* set reference clock */ 965 mask = HPIPE_MISC_ICP_FORCE_MASK; 966 data = 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; 967 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 968 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 969 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 970 /* Power and PLL Control */ 971 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 972 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 973 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 974 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 975 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 976 /* Loopback register */ 977 mask = HPIPE_LOOPBACK_SEL_MASK; 978 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; 979 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); 980 /* rx control 1 */ 981 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 982 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 983 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 984 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 985 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 986 /* DTL Control */ 987 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 988 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 989 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 990 991 /* Set analog paramters from ETP(HW) */ 992 debug("stage: Analog paramters from ETP(HW)\n"); 993 /* SERDES External Configuration 2 */ 994 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; 995 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; 996 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); 997 /* 0x7-DFE Resolution control */ 998 mask = HPIPE_DFE_RES_FORCE_MASK; 999 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 1000 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 1001 /* 0xd-G1_Setting_0 */ 1002 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; 1003 data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; 1004 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; 1005 data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; 1006 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); 1007 /* Genration 1 setting 2 (G1_Setting_2) */ 1008 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; 1009 data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; 1010 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; 1011 data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; 1012 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); 1013 /* Transmitter Slew Rate Control register (tx_reg1) */ 1014 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; 1015 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; 1016 mask |= HPIPE_TX_REG1_SLC_EN_MASK; 1017 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; 1018 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); 1019 /* Impedance Calibration Control register (cal_reg1) */ 1020 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; 1021 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; 1022 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; 1023 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; 1024 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); 1025 /* Generation 1 Setting 5 (g1_setting_5) */ 1026 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; 1027 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; 1028 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); 1029 /* 0xE-G1_Setting_1 */ 1030 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 1031 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 1032 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 1033 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 1034 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; 1035 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; 1036 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 1037 /* 0xA-DFE_Reg3 */ 1038 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 1039 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 1040 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 1041 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 1042 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 1043 1044 /* 0x111-G1_Setting_4 */ 1045 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; 1046 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; 1047 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); 1048 /* Genration 1 setting 3 (G1_Setting_3) */ 1049 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; 1050 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; 1051 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); 1052 1053 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1054 /* SERDES External Configuration */ 1055 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1056 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1057 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1058 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1059 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1060 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1061 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1062 1063 1064 /* check PLL rx & tx ready */ 1065 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1066 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1067 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1068 mask = data; 1069 data = polling_with_timeout(addr, data, mask, 15000); 1070 if (data != 0) { 1071 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1072 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1073 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1074 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1075 ret = 0; 1076 } 1077 1078 /* RX init */ 1079 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1080 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1081 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1082 1083 1084 /* check that RX init done */ 1085 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1086 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1087 mask = data; 1088 data = polling_with_timeout(addr, data, mask, 100); 1089 if (data != 0) { 1090 debug("Read from reg = %p - value = 0x%x\n", 1091 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1092 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1093 ret = 0; 1094 } 1095 1096 debug("stage: RF Reset\n"); 1097 /* RF Reset */ 1098 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1099 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1100 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1101 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1102 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1103 1104 debug_exit(); 1105 return ret; 1106 } 1107 1108 static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, 1109 void __iomem *comphy_base) 1110 { 1111 u32 mask, data, ret = 1; 1112 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 1113 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 1114 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 1115 void __iomem *addr; 1116 1117 debug_enter(); 1118 debug("stage: RFU configurations - hard reset comphy\n"); 1119 /* RFU configurations - hard reset comphy */ 1120 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 1121 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 1122 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 1123 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 1124 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 1125 1126 if (lane == 2) { 1127 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 1128 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET, 1129 COMMON_PHY_SD_CTRL1_RXAUI0_MASK); 1130 } 1131 if (lane == 4) { 1132 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 1133 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET, 1134 COMMON_PHY_SD_CTRL1_RXAUI1_MASK); 1135 } 1136 1137 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 1138 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1139 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1140 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 1141 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 1142 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 1143 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 1144 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1145 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1146 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1147 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1148 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 1149 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 1150 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; 1151 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; 1152 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1153 1154 /* release from hard reset */ 1155 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1156 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1157 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1158 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1159 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1160 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1161 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1162 1163 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1164 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1165 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1166 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1167 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1168 1169 /* Wait 1ms - until band gap and ref clock ready */ 1170 mdelay(1); 1171 1172 /* Start comphy Configuration */ 1173 debug("stage: Comphy configuration\n"); 1174 /* set reference clock */ 1175 reg_set(hpipe_addr + HPIPE_MISC_REG, 1176 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 1177 HPIPE_MISC_REFCLK_SEL_MASK); 1178 /* Power and PLL Control */ 1179 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 1180 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 1181 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 1182 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1183 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1184 /* Loopback register */ 1185 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 1186 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); 1187 /* rx control 1 */ 1188 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1189 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1190 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1191 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1192 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1193 /* DTL Control */ 1194 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, 1195 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, 1196 HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); 1197 1198 /* Set analog paramters from ETP(HW) */ 1199 debug("stage: Analog paramters from ETP(HW)\n"); 1200 /* SERDES External Configuration 2 */ 1201 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, 1202 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, 1203 SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK); 1204 /* 0x7-DFE Resolution control */ 1205 reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET, 1206 HPIPE_DFE_RES_FORCE_MASK); 1207 /* 0xd-G1_Setting_0 */ 1208 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, 1209 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, 1210 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); 1211 /* 0xE-G1_Setting_1 */ 1212 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 1213 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 1214 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 1215 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 1216 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; 1217 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; 1218 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 1219 /* 0xA-DFE_Reg3 */ 1220 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 1221 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 1222 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 1223 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 1224 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 1225 1226 /* 0x111-G1_Setting_4 */ 1227 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; 1228 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; 1229 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); 1230 1231 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1232 /* SERDES External Configuration */ 1233 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1234 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1235 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1236 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1237 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1238 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1239 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1240 1241 1242 /* check PLL rx & tx ready */ 1243 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1244 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1245 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1246 mask = data; 1247 data = polling_with_timeout(addr, data, mask, 15000); 1248 if (data != 0) { 1249 debug("Read from reg = %p - value = 0x%x\n", 1250 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1251 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1252 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1253 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1254 ret = 0; 1255 } 1256 1257 /* RX init */ 1258 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, 1259 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET, 1260 SD_EXTERNAL_CONFIG1_RX_INIT_MASK); 1261 1262 /* check that RX init done */ 1263 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1264 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1265 mask = data; 1266 data = polling_with_timeout(addr, data, mask, 100); 1267 if (data != 0) { 1268 debug("Read from reg = %p - value = 0x%x\n", 1269 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1270 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1271 ret = 0; 1272 } 1273 1274 debug("stage: RF Reset\n"); 1275 /* RF Reset */ 1276 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1277 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1278 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1279 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1280 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1281 1282 debug_exit(); 1283 return ret; 1284 } 1285 1286 static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, 1287 void __iomem *usb_cfg_addr, 1288 void __iomem *utmi_cfg_addr, 1289 u32 utmi_phy_port) 1290 { 1291 u32 mask, data; 1292 1293 debug_enter(); 1294 debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", 1295 utmi_index); 1296 /* Power down UTMI PHY */ 1297 reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET, 1298 UTMI_PHY_CFG_PU_MASK); 1299 1300 /* 1301 * If UTMI connected to USB Device, configure mux prior to PHY init 1302 * (Device can be connected to UTMI0 or to UTMI1) 1303 */ 1304 if (utmi_phy_port == UTMI_PHY_TO_USB_DEVICE0) { 1305 debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", 1306 utmi_index); 1307 /* USB3 Device UTMI enable */ 1308 mask = UTMI_USB_CFG_DEVICE_EN_MASK; 1309 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; 1310 /* USB3 Device UTMI MUX */ 1311 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; 1312 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; 1313 reg_set(usb_cfg_addr, data, mask); 1314 } 1315 1316 /* Set Test suspendm mode */ 1317 mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; 1318 data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; 1319 /* Enable Test UTMI select */ 1320 mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; 1321 data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; 1322 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); 1323 1324 /* Wait for UTMI power down */ 1325 mdelay(1); 1326 1327 debug_exit(); 1328 return; 1329 } 1330 1331 static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, 1332 void __iomem *usb_cfg_addr, 1333 void __iomem *utmi_cfg_addr, 1334 u32 utmi_phy_port) 1335 { 1336 u32 mask, data; 1337 1338 debug_exit(); 1339 debug("stage: Configure UTMI PHY %d registers\n", utmi_index); 1340 /* Reference Clock Divider Select */ 1341 mask = UTMI_PLL_CTRL_REFDIV_MASK; 1342 data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; 1343 /* Feedback Clock Divider Select - 90 for 25Mhz*/ 1344 mask |= UTMI_PLL_CTRL_FBDIV_MASK; 1345 data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; 1346 /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ 1347 mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; 1348 data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; 1349 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); 1350 1351 /* Impedance Calibration Threshold Setting */ 1352 reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, 1353 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, 1354 UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); 1355 1356 /* Set LS TX driver strength coarse control */ 1357 mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; 1358 data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; 1359 /* Set LS TX driver fine adjustment */ 1360 mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; 1361 data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; 1362 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); 1363 1364 /* Enable SQ */ 1365 mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; 1366 data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; 1367 /* Enable analog squelch detect */ 1368 mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; 1369 data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; 1370 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); 1371 1372 /* Set External squelch calibration number */ 1373 mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; 1374 data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; 1375 /* Enable the External squelch calibration */ 1376 mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; 1377 data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; 1378 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); 1379 1380 /* Set Control VDAT Reference Voltage - 0.325V */ 1381 mask = UTMI_CHGDTC_CTRL_VDAT_MASK; 1382 data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; 1383 /* Set Control VSRC Reference Voltage - 0.6V */ 1384 mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; 1385 data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; 1386 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); 1387 1388 debug_exit(); 1389 return; 1390 } 1391 1392 static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, 1393 void __iomem *usb_cfg_addr, 1394 void __iomem *utmi_cfg_addr, u32 utmi_phy_port) 1395 { 1396 u32 data, mask, ret = 1; 1397 void __iomem *addr; 1398 1399 debug_enter(); 1400 debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", 1401 utmi_index); 1402 /* Power UP UTMI PHY */ 1403 reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET, 1404 UTMI_PHY_CFG_PU_MASK); 1405 /* Disable Test UTMI select */ 1406 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, 1407 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET, 1408 UTMI_CTRL_STATUS0_TEST_SEL_MASK); 1409 1410 debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); 1411 addr = utmi_base_addr + UTMI_CALIB_CTRL_REG; 1412 data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; 1413 mask = data; 1414 data = polling_with_timeout(addr, data, mask, 100); 1415 if (data != 0) { 1416 error("Impedance calibration is not done\n"); 1417 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1418 ret = 0; 1419 } 1420 1421 data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; 1422 mask = data; 1423 data = polling_with_timeout(addr, data, mask, 100); 1424 if (data != 0) { 1425 error("PLL calibration is not done\n"); 1426 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1427 ret = 0; 1428 } 1429 1430 addr = utmi_base_addr + UTMI_PLL_CTRL_REG; 1431 data = UTMI_PLL_CTRL_PLL_RDY_MASK; 1432 mask = data; 1433 data = polling_with_timeout(addr, data, mask, 100); 1434 if (data != 0) { 1435 error("PLL is not ready\n"); 1436 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1437 ret = 0; 1438 } 1439 1440 if (ret) 1441 debug("Passed\n"); 1442 else 1443 debug("\n"); 1444 1445 debug_exit(); 1446 return ret; 1447 } 1448 1449 /* 1450 * comphy_utmi_phy_init initialize the UTMI PHY 1451 * the init split in 3 parts: 1452 * 1. Power down transceiver and PLL 1453 * 2. UTMI PHY configure 1454 * 3. Powe up transceiver and PLL 1455 * Note: - Power down/up should be once for both UTMI PHYs 1456 * - comphy_dedicated_phys_init call this function if at least there is 1457 * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is 1458 * legal 1459 */ 1460 static void comphy_utmi_phy_init(u32 utmi_phy_count, 1461 struct utmi_phy_data *cp110_utmi_data) 1462 { 1463 u32 i; 1464 1465 debug_enter(); 1466 /* UTMI Power down */ 1467 for (i = 0; i < utmi_phy_count; i++) { 1468 comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr, 1469 cp110_utmi_data[i].usb_cfg_addr, 1470 cp110_utmi_data[i].utmi_cfg_addr, 1471 cp110_utmi_data[i].utmi_phy_port); 1472 } 1473 /* PLL Power down */ 1474 debug("stage: UTMI PHY power down PLL\n"); 1475 for (i = 0; i < utmi_phy_count; i++) { 1476 reg_set(cp110_utmi_data[i].usb_cfg_addr, 1477 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); 1478 } 1479 /* UTMI configure */ 1480 for (i = 0; i < utmi_phy_count; i++) { 1481 comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr, 1482 cp110_utmi_data[i].usb_cfg_addr, 1483 cp110_utmi_data[i].utmi_cfg_addr, 1484 cp110_utmi_data[i].utmi_phy_port); 1485 } 1486 /* UTMI Power up */ 1487 for (i = 0; i < utmi_phy_count; i++) { 1488 if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr, 1489 cp110_utmi_data[i].usb_cfg_addr, 1490 cp110_utmi_data[i].utmi_cfg_addr, 1491 cp110_utmi_data[i].utmi_phy_port)) { 1492 error("Failed to initialize UTMI PHY %d\n", i); 1493 continue; 1494 } 1495 printf("UTMI PHY %d initialized to ", i); 1496 if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_TO_USB_DEVICE0) 1497 printf("USB Device\n"); 1498 else 1499 printf("USB Host%d\n", 1500 cp110_utmi_data[i].utmi_phy_port); 1501 } 1502 /* PLL Power up */ 1503 debug("stage: UTMI PHY power up PLL\n"); 1504 for (i = 0; i < utmi_phy_count; i++) { 1505 reg_set(cp110_utmi_data[i].usb_cfg_addr, 1506 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); 1507 } 1508 1509 debug_exit(); 1510 return; 1511 } 1512 1513 /* 1514 * comphy_dedicated_phys_init initialize the dedicated PHYs 1515 * - not muxed SerDes lanes e.g. UTMI PHY 1516 */ 1517 void comphy_dedicated_phys_init(void) 1518 { 1519 struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; 1520 int node; 1521 int i; 1522 1523 debug_enter(); 1524 debug("Initialize USB UTMI PHYs\n"); 1525 1526 /* Find the UTMI phy node in device tree and go over them */ 1527 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 1528 "marvell,mvebu-utmi-2.6.0"); 1529 1530 i = 0; 1531 while (node > 0) { 1532 /* get base address of UTMI phy */ 1533 cp110_utmi_data[i].utmi_base_addr = 1534 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1535 gd->fdt_blob, node, "reg", 0, NULL, true); 1536 if (cp110_utmi_data[i].utmi_base_addr == NULL) { 1537 error("UTMI PHY base address is invalid\n"); 1538 i++; 1539 continue; 1540 } 1541 1542 /* get usb config address */ 1543 cp110_utmi_data[i].usb_cfg_addr = 1544 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1545 gd->fdt_blob, node, "reg", 1, NULL, true); 1546 if (cp110_utmi_data[i].usb_cfg_addr == NULL) { 1547 error("UTMI PHY base address is invalid\n"); 1548 i++; 1549 continue; 1550 } 1551 1552 /* get UTMI config address */ 1553 cp110_utmi_data[i].utmi_cfg_addr = 1554 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1555 gd->fdt_blob, node, "reg", 2, NULL, true); 1556 if (cp110_utmi_data[i].utmi_cfg_addr == NULL) { 1557 error("UTMI PHY base address is invalid\n"); 1558 i++; 1559 continue; 1560 } 1561 1562 /* 1563 * get the port number (to check if the utmi connected to 1564 * host/device) 1565 */ 1566 cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int( 1567 gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); 1568 if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) { 1569 error("UTMI PHY port type is invalid\n"); 1570 i++; 1571 continue; 1572 } 1573 1574 node = fdt_node_offset_by_compatible( 1575 gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); 1576 i++; 1577 } 1578 1579 if (i > 0) 1580 comphy_utmi_phy_init(i, cp110_utmi_data); 1581 1582 debug_exit(); 1583 } 1584 1585 static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, 1586 struct comphy_map *serdes_map) 1587 { 1588 void __iomem *comphy_base_addr; 1589 struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS]; 1590 struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS]; 1591 u32 lane, comphy_max_count; 1592 1593 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; 1594 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; 1595 1596 /* 1597 * Copy the SerDes map configuration for PIPE map and PHY map 1598 * the comphy_mux_init modify the type of the lane if the type 1599 * is not valid because we have 2 selectores run the 1600 * comphy_mux_init twice and after that update the original 1601 * serdes_map 1602 */ 1603 for (lane = 0; lane < comphy_max_count; lane++) { 1604 comphy_map_pipe_data[lane].type = serdes_map[lane].type; 1605 comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; 1606 comphy_map_phy_data[lane].type = serdes_map[lane].type; 1607 comphy_map_phy_data[lane].speed = serdes_map[lane].speed; 1608 } 1609 ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; 1610 comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data, 1611 comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET); 1612 1613 ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; 1614 comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data, 1615 comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); 1616 /* Fix the type after check the PHY and PIPE configuration */ 1617 for (lane = 0; lane < comphy_max_count; lane++) { 1618 if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && 1619 (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) 1620 serdes_map[lane].type = PHY_TYPE_UNCONNECTED; 1621 } 1622 } 1623 1624 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, 1625 struct comphy_map *serdes_map) 1626 { 1627 struct comphy_map *ptr_comphy_map; 1628 void __iomem *comphy_base_addr, *hpipe_base_addr; 1629 u32 comphy_max_count, lane, ret = 0; 1630 u32 pcie_width = 0; 1631 1632 debug_enter(); 1633 1634 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; 1635 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; 1636 hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; 1637 1638 /* Config Comphy mux configuration */ 1639 comphy_mux_cp110_init(ptr_chip_cfg, serdes_map); 1640 1641 /* Check if the first 4 lanes configured as By-4 */ 1642 for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; 1643 lane++, ptr_comphy_map++) { 1644 if (ptr_comphy_map->type != PHY_TYPE_PEX0) 1645 break; 1646 pcie_width++; 1647 } 1648 1649 for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; 1650 lane++, ptr_comphy_map++) { 1651 debug("Initialize serdes number %d\n", lane); 1652 debug("Serdes type = 0x%x\n", ptr_comphy_map->type); 1653 if (lane == 4) { 1654 /* 1655 * PCIe lanes above the first 4 lanes, can be only 1656 * by1 1657 */ 1658 pcie_width = 1; 1659 } 1660 switch (ptr_comphy_map->type) { 1661 case PHY_TYPE_UNCONNECTED: 1662 continue; 1663 break; 1664 case PHY_TYPE_PEX0: 1665 case PHY_TYPE_PEX1: 1666 case PHY_TYPE_PEX2: 1667 case PHY_TYPE_PEX3: 1668 ret = comphy_pcie_power_up( 1669 lane, pcie_width, ptr_comphy_map->clk_src, 1670 hpipe_base_addr, comphy_base_addr); 1671 break; 1672 case PHY_TYPE_SATA0: 1673 case PHY_TYPE_SATA1: 1674 case PHY_TYPE_SATA2: 1675 case PHY_TYPE_SATA3: 1676 ret = comphy_sata_power_up( 1677 lane, hpipe_base_addr, comphy_base_addr, 1678 ptr_chip_cfg->comphy_index); 1679 break; 1680 case PHY_TYPE_USB3_HOST0: 1681 case PHY_TYPE_USB3_HOST1: 1682 case PHY_TYPE_USB3_DEVICE: 1683 ret = comphy_usb3_power_up(lane, hpipe_base_addr, 1684 comphy_base_addr); 1685 break; 1686 case PHY_TYPE_SGMII0: 1687 case PHY_TYPE_SGMII1: 1688 case PHY_TYPE_SGMII2: 1689 case PHY_TYPE_SGMII3: 1690 if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { 1691 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", 1692 lane); 1693 ptr_comphy_map->speed = PHY_SPEED_1_25G; 1694 } 1695 ret = comphy_sgmii_power_up( 1696 lane, ptr_comphy_map->speed, hpipe_base_addr, 1697 comphy_base_addr); 1698 break; 1699 case PHY_TYPE_KR: 1700 ret = comphy_kr_power_up(lane, hpipe_base_addr, 1701 comphy_base_addr); 1702 break; 1703 case PHY_TYPE_RXAUI0: 1704 case PHY_TYPE_RXAUI1: 1705 ret = comphy_rxauii_power_up(lane, hpipe_base_addr, 1706 comphy_base_addr); 1707 break; 1708 default: 1709 debug("Unknown SerDes type, skip initialize SerDes %d\n", 1710 lane); 1711 break; 1712 } 1713 if (ret == 0) { 1714 /* 1715 * If interface wans't initialiuzed, set the lane to 1716 * PHY_TYPE_UNCONNECTED state. 1717 */ 1718 ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; 1719 error("PLL is not locked - Failed to initialize lane %d\n", 1720 lane); 1721 } 1722 } 1723 1724 debug_exit(); 1725 return 0; 1726 } 1727