1 /*
2  * Copyright (C) 2015-2016 Marvell International Ltd.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <fdtdec.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
12 
13 #include "comphy.h"
14 #include "comphy_hpipe.h"
15 #include "sata.h"
16 #include "utmi_phy.h"
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 #define SD_ADDR(base, lane)			(base + 0x1000 * lane)
21 #define HPIPE_ADDR(base, lane)			(SD_ADDR(base, lane) + 0x800)
22 #define COMPHY_ADDR(base, lane)			(base + 0x28 * lane)
23 
24 struct utmi_phy_data {
25 	void __iomem *utmi_base_addr;
26 	void __iomem *usb_cfg_addr;
27 	void __iomem *utmi_cfg_addr;
28 	u32 utmi_phy_port;
29 };
30 
31 /*
32  * For CP-110 we have 2 Selector registers "PHY Selectors",
33  * and "PIPE Selectors".
34  * PIPE selector include USB and PCIe options.
35  * PHY selector include the Ethernet and SATA options, every Ethernet
36  * option has different options, for example: serdes lane2 had option
37  * Eth_port_0 that include (SGMII0, RXAUI0, SFI)
38  */
39 struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
40 	{4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
41 	     {PHY_TYPE_SATA1, 0x4} } },
42 	{4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
43 	     {PHY_TYPE_SATA0, 0x4} } },
44 	{6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
45 	     {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
46 	     {PHY_TYPE_SATA0, 0x4} } },
47 	{8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
48 	     {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
49 	{7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
50 	     {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
51 	     {PHY_TYPE_SGMII1, 0x1} } },
52 	{6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
53 	     {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
54 };
55 
56 struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
57 	{2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
58 	{4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
59 	     {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
60 	     {PHY_TYPE_PEX0, 0x4} } },
61 	{3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
62 	     {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
63 	{3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
64 	     {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
65 	{4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
66 	     {PHY_TYPE_USB3_HOST1, 0x1},
67 	     {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
68 	{2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
69 };
70 
71 static u32 polling_with_timeout(void __iomem *addr, u32 val,
72 				u32 mask, unsigned long usec_timout)
73 {
74 	u32 data;
75 
76 	do {
77 		udelay(1);
78 		data = readl(addr) & mask;
79 	} while (data != val  && --usec_timout > 0);
80 
81 	if (usec_timout == 0)
82 		return data;
83 
84 	return 0;
85 }
86 
87 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
88 				bool is_end_point, void __iomem *hpipe_base,
89 				void __iomem *comphy_base)
90 {
91 	u32 mask, data, ret = 1;
92 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
93 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
94 	void __iomem *addr;
95 	u32 pcie_clk = 0; /* set input by default */
96 
97 	debug_enter();
98 
99 	/*
100 	 * ToDo:
101 	 * Add SAR (Sample-At-Reset) configuration for the PCIe clock
102 	 * direction. SAR code is currently not ported from Marvell
103 	 * U-Boot to mainline version.
104 	 *
105 	 * SerDes Lane 4/5 got the PCIe ref-clock #1,
106 	 * and SerDes Lane 0 got PCIe ref-clock #0
107 	 */
108 	debug("PCIe clock = %x\n", pcie_clk);
109 	debug("PCIe RC    = %d\n", !is_end_point);
110 	debug("PCIe width = %d\n", pcie_width);
111 
112 	/* enable PCIe by4 and by2 */
113 	if (lane == 0) {
114 		if (pcie_width == 4) {
115 			reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
116 				0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET,
117 				COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
118 		} else if (pcie_width == 2) {
119 			reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
120 				0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET,
121 				COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
122 		}
123 	}
124 
125 	/*
126 	 * If PCIe clock is output and clock source from SerDes lane 5,
127 	 * we need to configure the clock-source MUX.
128 	 * By default, the clock source is from lane 4
129 	 */
130 	if (pcie_clk && clk_src && (lane == 5)) {
131 		reg_set((void __iomem *)DFX_DEV_GEN_CTRL12,
132 			0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET,
133 			DFX_DEV_GEN_PCIE_CLK_SRC_MASK);
134 	}
135 
136 	debug("stage: RFU configurations - hard reset comphy\n");
137 	/* RFU configurations - hard reset comphy */
138 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
139 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
140 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
141 	data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
142 	mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
143 	data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
144 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
145 	data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
146 	mask |= COMMON_PHY_PHY_MODE_MASK;
147 	data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
148 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
149 
150 	/* release from hard reset */
151 	mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
152 	data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
153 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
154 	data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
155 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
156 
157 	/* Wait 1ms - until band gap and ref clock ready */
158 	mdelay(1);
159 	/* Start comphy Configuration */
160 	debug("stage: Comphy configuration\n");
161 	/* Set PIPE soft reset */
162 	mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
163 	data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
164 	/* Set PHY datapath width mode for V0 */
165 	mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
166 	data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
167 	/* Set Data bus width USB mode for V0 */
168 	mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
169 	data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
170 	/* Set CORE_CLK output frequency for 250Mhz */
171 	mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
172 	data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
173 	reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
174 	/* Set PLL ready delay for 0x2 */
175 	data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
176 	mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
177 	if (pcie_width != 1) {
178 		data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET;
179 		mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK;
180 		data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
181 		mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
182 	}
183 	reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
184 
185 	/* Set PIPE mode interface to PCIe3 - 0x1  & set lane order */
186 	data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
187 	mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
188 	if (pcie_width != 1) {
189 		mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK;
190 		mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK;
191 		mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
192 		if (lane == 0) {
193 			data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET;
194 			data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
195 		} else if (lane == (pcie_width - 1)) {
196 			data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
197 		}
198 	}
199 	reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
200 	/* Config update polarity equalization */
201 	reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG,
202 		0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET,
203 		HPIPE_CFG_UPDATE_POLARITY_MASK);
204 	/* Set PIPE version 4 to mode enable */
205 	reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG,
206 		0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET,
207 		HPIPE_DFE_CTRL_28_PIPE4_MASK);
208 	/* TODO: check if pcie clock is output/input - for bringup use input*/
209 	/* Enable PIN clock 100M_125M */
210 	mask = 0;
211 	data = 0;
212 	/* Only if clock is output, configure the clock-source mux */
213 	if (pcie_clk) {
214 		mask |= HPIPE_MISC_CLK100M_125M_MASK;
215 		data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
216 	}
217 	/*
218 	 * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz
219 	 * clock
220 	 */
221 	mask |= HPIPE_MISC_TXDCLK_2X_MASK;
222 	data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
223 	/* Enable 500MHz Clock */
224 	mask |= HPIPE_MISC_CLK500_EN_MASK;
225 	data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
226 	if (pcie_clk) { /* output */
227 		/* Set reference clock comes from group 1 */
228 		mask |= HPIPE_MISC_REFCLK_SEL_MASK;
229 		data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
230 	} else {
231 		/* Set reference clock comes from group 2 */
232 		mask |= HPIPE_MISC_REFCLK_SEL_MASK;
233 		data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
234 	}
235 	mask |= HPIPE_MISC_ICP_FORCE_MASK;
236 	data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
237 	reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
238 	if (pcie_clk) { /* output */
239 		/* Set reference frequcency select - 0x2 for 25MHz*/
240 		mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
241 		data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
242 	} else {
243 		/* Set reference frequcency select - 0x0 for 100MHz*/
244 		mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
245 		data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
246 	}
247 	/* Set PHY mode to PCIe */
248 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
249 	data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
250 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
251 
252 	/* ref clock alignment */
253 	if (pcie_width != 1) {
254 		mask = HPIPE_LANE_ALIGN_OFF_MASK;
255 		data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET;
256 		reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
257 	}
258 
259 	/*
260 	 * Set the amount of time spent in the LoZ state - set for 0x7 only if
261 	 * the PCIe clock is output
262 	 */
263 	if (pcie_clk) {
264 		reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
265 			0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
266 			HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
267 	}
268 
269 	/* Set Maximal PHY Generation Setting(8Gbps) */
270 	mask = HPIPE_INTERFACE_GEN_MAX_MASK;
271 	data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
272 	/* Bypass frame detection and sync detection for RX DATA */
273 	mask = HPIPE_INTERFACE_DET_BYPASS_MASK;
274 	data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
275 	/* Set Link Train Mode (Tx training control pins are used) */
276 	mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
277 	data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
278 	reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
279 
280 	/* Set Idle_sync enable */
281 	mask = HPIPE_PCIE_IDLE_SYNC_MASK;
282 	data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
283 	/* Select bits for PCIE Gen3(32bit) */
284 	mask |= HPIPE_PCIE_SEL_BITS_MASK;
285 	data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
286 	reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
287 
288 	/* Enable Tx_adapt_g1 */
289 	mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
290 	data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
291 	/* Enable Tx_adapt_gn1 */
292 	mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
293 	data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
294 	/* Disable Tx_adapt_g0 */
295 	mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
296 	data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
297 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
298 
299 	/* Set reg_tx_train_chk_init */
300 	mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
301 	data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
302 	/* Enable TX_COE_FM_PIN_PCIE3_EN */
303 	mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
304 	data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
305 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
306 
307 	debug("stage: TRx training parameters\n");
308 	/* Set Preset sweep configurations */
309 	mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK;
310 	data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET;
311 
312 	mask |= HPIPE_TX_NUM_OF_PRESET_MASK;
313 	data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET;
314 
315 	mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK;
316 	data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET;
317 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
318 
319 	/* Tx train start configuration */
320 	mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK;
321 	data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET;
322 
323 	mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK;
324 	data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET;
325 
326 	mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK;
327 	data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET;
328 
329 	mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
330 	data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET;
331 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
332 
333 	/* Enable Tx train P2P */
334 	mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
335 	data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
336 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
337 
338 	/* Configure Tx train timeout */
339 	mask = HPIPE_TRX_TRAIN_TIMER_MASK;
340 	data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET;
341 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
342 
343 	/* Disable G0/G1/GN1 adaptation */
344 	mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK
345 		| HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
346 	data = 0;
347 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
348 
349 	/* Disable DTL frequency loop */
350 	mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
351 	data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
352 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
353 
354 	/* Configure G3 DFE */
355 	mask = HPIPE_G3_DFE_RES_MASK;
356 	data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
357 	reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
358 
359 	/* Use TX/RX training result for DFE */
360 	mask = HPIPE_DFE_RES_FORCE_MASK;
361 	data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
362 	reg_set(hpipe_addr + HPIPE_DFE_REG0,  data, mask);
363 
364 	/* Configure initial and final coefficient value for receiver */
365 	mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
366 	data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
367 
368 	mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
369 	data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
370 
371 	mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
372 	data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
373 	reg_set(hpipe_addr + HPIPE_G3_SET_1_REG,  data, mask);
374 
375 	/* Trigger sampler enable pulse */
376 	mask = HPIPE_SMAPLER_MASK;
377 	data = 0x1 << HPIPE_SMAPLER_OFFSET;
378 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
379 	udelay(5);
380 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask);
381 
382 	/* FFE resistor tuning for different bandwidth  */
383 	mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
384 	data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
385 
386 	mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
387 	data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
388 	reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
389 
390 	/* Pattern lock lost timeout disable */
391 	mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
392 	data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
393 	reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
394 
395 	/* Configure DFE adaptations */
396 	mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
397 	data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
398 	mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
399 	data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
400 	mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
401 	data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
402 	reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
403 	mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
404 	data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
405 	reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
406 
407 	/* Genration 2 setting 1*/
408 	mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
409 	data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
410 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
411 	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
412 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
413 	data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
414 	reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
415 
416 	/* DFE enable */
417 	mask = HPIPE_G2_DFE_RES_MASK;
418 	data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
419 	reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
420 
421 	/* Configure DFE Resolution */
422 	mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
423 	data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
424 	reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
425 
426 	/* VDD calibration control */
427 	mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
428 	data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
429 	reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
430 
431 	/* Set PLL Charge-pump Current Control */
432 	mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
433 	data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
434 	reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
435 
436 	/* Set lane rqualization remote setting */
437 	mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
438 	data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
439 	mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
440 	data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
441 	mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
442 	data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
443 	reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
444 
445 	if (!is_end_point) {
446 		/* Set phy in root complex mode */
447 		mask = HPIPE_CFG_PHY_RC_EP_MASK;
448 		data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
449 		reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
450 	}
451 
452 	debug("stage: Comphy power up\n");
453 
454 	/*
455 	 * For PCIe by4 or by2 - release from reset only after finish to
456 	 * configure all lanes
457 	 */
458 	if ((pcie_width == 1) || (lane == (pcie_width - 1))) {
459 		u32 i, start_lane, end_lane;
460 
461 		if (pcie_width != 1) {
462 			/* allows writing to all lanes in one write */
463 			reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
464 				0x0 <<
465 				COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
466 				COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
467 			start_lane = 0;
468 			end_lane = pcie_width;
469 
470 			/*
471 			 * Release from PIPE soft reset
472 			 * for PCIe by4 or by2 - release from soft reset
473 			 * all lanes - can't use read modify write
474 			 */
475 			reg_set(HPIPE_ADDR(hpipe_base, 0) +
476 				HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff);
477 		} else {
478 			start_lane = lane;
479 			end_lane = lane + 1;
480 
481 			/*
482 			 * Release from PIPE soft reset
483 			 * for PCIe by4 or by2 - release from soft reset
484 			 * all lanes
485 			 */
486 			reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
487 				0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
488 				HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
489 		}
490 
491 
492 		if (pcie_width != 1) {
493 			/* disable writing to all lanes with one write */
494 			reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
495 				0x3210 <<
496 				COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
497 				COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
498 		}
499 
500 		debug("stage: Check PLL\n");
501 		/* Read lane status */
502 		for (i = start_lane; i < end_lane; i++) {
503 			addr = HPIPE_ADDR(hpipe_base, i) +
504 				HPIPE_LANE_STATUS1_REG;
505 			data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
506 			mask = data;
507 			data = polling_with_timeout(addr, data, mask, 15000);
508 			if (data != 0) {
509 				debug("Read from reg = %p - value = 0x%x\n",
510 				      hpipe_addr + HPIPE_LANE_STATUS1_REG,
511 				      data);
512 				error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
513 				ret = 0;
514 			}
515 		}
516 	}
517 
518 	debug_exit();
519 	return ret;
520 }
521 
522 static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
523 				void __iomem *comphy_base)
524 {
525 	u32 mask, data, ret = 1;
526 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
527 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
528 	void __iomem *addr;
529 
530 	debug_enter();
531 	debug("stage: RFU configurations - hard reset comphy\n");
532 	/* RFU configurations - hard reset comphy */
533 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
534 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
535 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
536 	data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
537 	mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
538 	data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
539 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
540 	data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
541 	mask |= COMMON_PHY_PHY_MODE_MASK;
542 	data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
543 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
544 
545 	/* release from hard reset */
546 	mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
547 	data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
548 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
549 	data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
550 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
551 
552 	/* Wait 1ms - until band gap and ref clock ready */
553 	mdelay(1);
554 
555 	/* Start comphy Configuration */
556 	debug("stage: Comphy configuration\n");
557 	/* Set PIPE soft reset */
558 	mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
559 	data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
560 	/* Set PHY datapath width mode for V0 */
561 	mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
562 	data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
563 	/* Set Data bus width USB mode for V0 */
564 	mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
565 	data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
566 	/* Set CORE_CLK output frequency for 250Mhz */
567 	mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
568 	data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
569 	reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
570 	/* Set PLL ready delay for 0x2 */
571 	reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
572 		0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
573 		HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
574 	/* Set reference clock to come from group 1 - 25Mhz */
575 	reg_set(hpipe_addr + HPIPE_MISC_REG,
576 		0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
577 		HPIPE_MISC_REFCLK_SEL_MASK);
578 	/* Set reference frequcency select - 0x2 */
579 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
580 	data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
581 	/* Set PHY mode to USB - 0x5 */
582 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
583 	data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
584 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
585 	/* Set the amount of time spent in the LoZ state - set for 0x7 */
586 	reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
587 		0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
588 		HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
589 	/* Set max PHY generation setting - 5Gbps */
590 	reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
591 		0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
592 		HPIPE_INTERFACE_GEN_MAX_MASK);
593 	/* Set select data width 20Bit (SEL_BITS[2:0]) */
594 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
595 		0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
596 		HPIPE_LOOPBACK_SEL_MASK);
597 	/* select de-emphasize 3.5db */
598 	reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
599 		0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
600 		HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
601 	/* override tx margining from the MAC */
602 	reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
603 		0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
604 		HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
605 
606 	/* Start analog paramters from ETP(HW) */
607 	debug("stage: Analog paramters from ETP(HW)\n");
608 	/* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
609 	mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
610 	data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
611 	/* Set Override PHY DFE control pins for 0x1 */
612 	mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
613 	data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
614 	/* Set Spread Spectrum Clock Enable fot 0x1 */
615 	mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
616 	data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
617 	reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
618 	/* End of analog parameters */
619 
620 	debug("stage: Comphy power up\n");
621 	/* Release from PIPE soft reset */
622 	reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
623 		0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
624 		HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
625 
626 	/* wait 15ms - for comphy calibration done */
627 	debug("stage: Check PLL\n");
628 	/* Read lane status */
629 	addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
630 	data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
631 	mask = data;
632 	data = polling_with_timeout(addr, data, mask, 15000);
633 	if (data != 0) {
634 		debug("Read from reg = %p - value = 0x%x\n",
635 		      hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
636 		error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
637 		ret = 0;
638 	}
639 
640 	debug_exit();
641 	return ret;
642 }
643 
644 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
645 				void __iomem *comphy_base, int cp_index)
646 {
647 	u32 mask, data, i, ret = 1;
648 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
649 	void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
650 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
651 	void __iomem *addr;
652 	void __iomem *sata_base = NULL;
653 	int sata_node = -1; /* Set to -1 in order to read the first sata node */
654 
655 	debug_enter();
656 
657 	/*
658 	 * Assumption - each CP has only one SATA controller
659 	 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1
660 	 * will return the first node always.
661 	 * In order to parse each CPs SATA node, fdt_node_offset_by_compatible
662 	 * must be called again (according to the CP id)
663 	 */
664 	for (i = 0; i < (cp_index + 1); i++)
665 		sata_node = fdt_node_offset_by_compatible(
666 			gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
667 
668 	if (sata_node == 0) {
669 		error("SATA node not found in FDT\n");
670 		return 0;
671 	}
672 
673 	sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
674 		gd->fdt_blob, sata_node, "reg", 0, NULL, true);
675 	if (sata_base == NULL) {
676 		error("SATA address not found in FDT\n");
677 		return 0;
678 	}
679 
680 	debug("SATA address found in FDT %p\n", sata_base);
681 
682 	debug("stage: MAC configuration - power down comphy\n");
683 	/*
684 	 * MAC configuration powe down comphy use indirect address for
685 	 * vendor spesific SATA control register
686 	 */
687 	reg_set(sata_base + SATA3_VENDOR_ADDRESS,
688 		SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
689 		SATA3_VENDOR_ADDR_MASK);
690 	/* SATA 0 power down */
691 	mask = SATA3_CTRL_SATA0_PD_MASK;
692 	data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
693 	/* SATA 1 power down */
694 	mask |= SATA3_CTRL_SATA1_PD_MASK;
695 	data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
696 	/* SATA SSU disable */
697 	mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
698 	data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
699 	/* SATA port 1 disable */
700 	mask |= SATA3_CTRL_SATA_SSU_MASK;
701 	data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
702 	reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
703 
704 	debug("stage: RFU configurations - hard reset comphy\n");
705 	/* RFU configurations - hard reset comphy */
706 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
707 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
708 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
709 	data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
710 	mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
711 	data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
712 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
713 	data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
714 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
715 
716 	/* Set select data  width 40Bit - SATA mode only */
717 	reg_set(comphy_addr + COMMON_PHY_CFG6_REG,
718 		0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET,
719 		COMMON_PHY_CFG6_IF_40_SEL_MASK);
720 
721 	/* release from hard reset in SD external */
722 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
723 	data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
724 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
725 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
726 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
727 
728 	/* Wait 1ms - until band gap and ref clock ready */
729 	mdelay(1);
730 
731 	debug("stage: Comphy configuration\n");
732 	/* Start comphy Configuration */
733 	/* Set reference clock to comes from group 1 - choose 25Mhz */
734 	reg_set(hpipe_addr + HPIPE_MISC_REG,
735 		0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
736 		HPIPE_MISC_REFCLK_SEL_MASK);
737 	/* Reference frequency select set 1 (for SATA = 25Mhz) */
738 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
739 	data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
740 	/* PHY mode select (set SATA = 0x0 */
741 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
742 	data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
743 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
744 	/* Set max PHY generation setting - 6Gbps */
745 	reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
746 		0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
747 		HPIPE_INTERFACE_GEN_MAX_MASK);
748 	/* Set select data  width 40Bit (SEL_BITS[2:0]) */
749 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
750 		0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
751 
752 	debug("stage: Analog paramters from ETP(HW)\n");
753 	/* Set analog parameters from ETP(HW) */
754 	/* G1 settings */
755 	mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
756 	data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
757 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
758 	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
759 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
760 	data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
761 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
762 	data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
763 	mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
764 	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
765 	reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
766 
767 	mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
768 	data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
769 	mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
770 	data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
771 	mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
772 	data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
773 	mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK;
774 	data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET;
775 	mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK;
776 	data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET;
777 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
778 
779 	/* G2 settings */
780 	mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
781 	data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
782 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
783 	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
784 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
785 	data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
786 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
787 	data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET;
788 	mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK;
789 	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET;
790 	reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
791 
792 	/* G3 settings */
793 	mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
794 	data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
795 	mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
796 	data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
797 	mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK;
798 	data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET;
799 	mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK;
800 	data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET;
801 	mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK;
802 	data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET;
803 	mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK;
804 	data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET;
805 	mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
806 	data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
807 	reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
808 
809 	/* DTL Control */
810 	mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK;
811 	data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET;
812 	mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK;
813 	data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET;
814 	mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
815 	data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
816 	mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK;
817 	data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET;
818 	mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK;
819 	data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET;
820 	mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK;
821 	data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET;
822 	mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
823 	data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET;
824 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
825 
826 	/* Trigger sampler enable pulse (by toggleing the bit) */
827 	mask = HPIPE_SMAPLER_MASK;
828 	data = 0x1 << HPIPE_SMAPLER_OFFSET;
829 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
830 	mask = HPIPE_SMAPLER_MASK;
831 	data = 0x0 << HPIPE_SMAPLER_OFFSET;
832 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
833 
834 	/* VDD Calibration Control 3 */
835 	mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
836 	data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
837 	reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
838 
839 	/* DFE Resolution Control */
840 	mask = HPIPE_DFE_RES_FORCE_MASK;
841 	data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
842 	reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
843 
844 	/* DFE F3-F5 Coefficient Control */
845 	mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
846 	data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
847 	mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
848 	data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
849 	reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
850 
851 	/* G3 Setting 3 */
852 	mask = HPIPE_G3_FFE_CAP_SEL_MASK;
853 	data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET;
854 	mask |= HPIPE_G3_FFE_RES_SEL_MASK;
855 	data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET;
856 	mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK;
857 	data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET;
858 	mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
859 	data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
860 	mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
861 	data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
862 	reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
863 
864 	/* G3 Setting 4 */
865 	mask = HPIPE_G3_DFE_RES_MASK;
866 	data = 0x2 << HPIPE_G3_DFE_RES_OFFSET;
867 	reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
868 
869 	/* Offset Phase Control */
870 	mask = HPIPE_OS_PH_OFFSET_MASK;
871 	data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET;
872 	mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK;
873 	data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET;
874 	reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
875 	mask = HPIPE_OS_PH_VALID_MASK;
876 	data = 0x1 << HPIPE_OS_PH_VALID_OFFSET;
877 	reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
878 	mask = HPIPE_OS_PH_VALID_MASK;
879 	data = 0x0 << HPIPE_OS_PH_VALID_OFFSET;
880 	reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
881 
882 	/* Set G1 TX amplitude and TX post emphasis value */
883 	mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
884 	data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
885 	mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK;
886 	data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET;
887 	mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
888 	data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
889 	mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK;
890 	data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET;
891 	reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
892 
893 	/* Set G2 TX amplitude and TX post emphasis value */
894 	mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK;
895 	data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET;
896 	mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK;
897 	data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET;
898 	mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK;
899 	data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET;
900 	mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK;
901 	data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET;
902 	reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask);
903 
904 	/* Set G3 TX amplitude and TX post emphasis value */
905 	mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK;
906 	data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET;
907 	mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK;
908 	data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET;
909 	mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK;
910 	data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET;
911 	mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK;
912 	data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET;
913 	mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK;
914 	data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET;
915 	mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK;
916 	data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET;
917 	reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask);
918 
919 	/* SERDES External Configuration 2 register */
920 	mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK;
921 	data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET;
922 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
923 
924 	/* DFE reset sequence */
925 	reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
926 		0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
927 		HPIPE_PWR_CTR_RST_DFE_MASK);
928 	reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
929 		0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
930 		HPIPE_PWR_CTR_RST_DFE_MASK);
931 	/* SW reset for interupt logic */
932 	reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
933 		0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
934 		HPIPE_PWR_CTR_SFT_RST_MASK);
935 	reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
936 		0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
937 		HPIPE_PWR_CTR_SFT_RST_MASK);
938 
939 	debug("stage: Comphy power up\n");
940 	/*
941 	 * MAC configuration power up comphy - power up PLL/TX/RX
942 	 * use indirect address for vendor spesific SATA control register
943 	 */
944 	reg_set(sata_base + SATA3_VENDOR_ADDRESS,
945 		SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
946 		SATA3_VENDOR_ADDR_MASK);
947 	/* SATA 0 power up */
948 	mask = SATA3_CTRL_SATA0_PD_MASK;
949 	data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
950 	/* SATA 1 power up */
951 	mask |= SATA3_CTRL_SATA1_PD_MASK;
952 	data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
953 	/* SATA SSU enable */
954 	mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
955 	data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
956 	/* SATA port 1 enable */
957 	mask |= SATA3_CTRL_SATA_SSU_MASK;
958 	data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
959 	reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
960 
961 	/* MBUS request size and interface select register */
962 	reg_set(sata_base + SATA3_VENDOR_ADDRESS,
963 		SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
964 		SATA3_VENDOR_ADDR_MASK);
965 	/* Mbus regret enable */
966 	reg_set(sata_base + SATA3_VENDOR_DATA,
967 		0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK);
968 
969 	debug("stage: Check PLL\n");
970 
971 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
972 	data = SD_EXTERNAL_STATUS0_PLL_TX_MASK &
973 		SD_EXTERNAL_STATUS0_PLL_RX_MASK;
974 	mask = data;
975 	data = polling_with_timeout(addr, data, mask, 15000);
976 	if (data != 0) {
977 		debug("Read from reg = %p - value = 0x%x\n",
978 		      hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
979 		error("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n",
980 		      (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK),
981 		      (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK));
982 		ret = 0;
983 	}
984 
985 	debug_exit();
986 	return ret;
987 }
988 
989 static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed,
990 				 void __iomem *hpipe_base,
991 				 void __iomem *comphy_base)
992 {
993 	u32 mask, data, ret = 1;
994 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
995 	void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
996 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
997 	void __iomem *addr;
998 
999 	debug_enter();
1000 	debug("stage: RFU configurations - hard reset comphy\n");
1001 	/* RFU configurations - hard reset comphy */
1002 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1003 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1004 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1005 	data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1006 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1007 
1008 	/* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
1009 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1010 	data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1011 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
1012 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
1013 	if (sgmii_speed == PHY_SPEED_1_25G) {
1014 		data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1015 		data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1016 	} else {
1017 		/* 3.125G */
1018 		data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1019 		data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1020 	}
1021 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1022 	data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1023 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1024 	data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1025 	mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
1026 	data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
1027 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1028 
1029 	/* release from hard reset */
1030 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1031 	data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1032 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1033 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1034 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1035 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1036 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1037 
1038 	/* release from hard reset */
1039 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1040 	data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1041 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1042 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1043 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1044 
1045 
1046 	/* Wait 1ms - until band gap and ref clock ready */
1047 	mdelay(1);
1048 
1049 	/* Start comphy Configuration */
1050 	debug("stage: Comphy configuration\n");
1051 	/* set reference clock */
1052 	mask = HPIPE_MISC_REFCLK_SEL_MASK;
1053 	data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
1054 	reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
1055 	/* Power and PLL Control */
1056 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1057 	data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1058 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1059 	data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1060 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1061 	/* Loopback register */
1062 	mask = HPIPE_LOOPBACK_SEL_MASK;
1063 	data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
1064 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
1065 	/* rx control 1 */
1066 	mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
1067 	data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
1068 	mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
1069 	data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
1070 	reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1071 	/* DTL Control */
1072 	mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
1073 	data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
1074 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
1075 
1076 	/* Set analog paramters from ETP(HW) - for now use the default datas */
1077 	debug("stage: Analog paramters from ETP(HW)\n");
1078 
1079 	reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
1080 		0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
1081 		HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
1082 
1083 	debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1084 	/* SERDES External Configuration */
1085 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1086 	data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1087 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1088 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1089 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1090 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1091 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1092 
1093 	/* check PLL rx & tx ready */
1094 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1095 	data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1096 		SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1097 	mask = data;
1098 	data = polling_with_timeout(addr, data, mask, 15000);
1099 	if (data != 0) {
1100 		debug("Read from reg = %p - value = 0x%x\n",
1101 		      sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1102 		error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
1103 		      (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1104 		      (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1105 		ret = 0;
1106 	}
1107 
1108 	/* RX init */
1109 	mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1110 	data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1111 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1112 
1113 	/* check that RX init done */
1114 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1115 	data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1116 	mask = data;
1117 	data = polling_with_timeout(addr, data, mask, 100);
1118 	if (data != 0) {
1119 		debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1120 		error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
1121 		ret = 0;
1122 	}
1123 
1124 	debug("stage: RF Reset\n");
1125 	/* RF Reset */
1126 	mask =  SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1127 	data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1128 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1129 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1130 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1131 
1132 	debug_exit();
1133 	return ret;
1134 }
1135 
1136 static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base,
1137 			       void __iomem *comphy_base, u32 speed)
1138 {
1139 	u32 mask, data, ret = 1;
1140 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
1141 	void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
1142 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
1143 	void __iomem *addr;
1144 
1145 	debug_enter();
1146 	debug("stage: RFU configurations - hard reset comphy\n");
1147 	/* RFU configurations - hard reset comphy */
1148 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1149 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1150 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1151 	data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1152 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1153 
1154 	/* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
1155 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1156 	data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1157 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
1158 	data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1159 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
1160 	data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1161 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1162 	data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1163 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1164 	data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1165 	mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
1166 	data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
1167 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1168 
1169 	/* release from hard reset */
1170 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1171 	data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1172 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1173 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1174 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1175 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1176 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1177 
1178 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1179 	data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1180 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1181 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1182 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1183 
1184 
1185 	/* Wait 1ms - until band gap and ref clock ready */
1186 	mdelay(1);
1187 
1188 	/* Start comphy Configuration */
1189 	debug("stage: Comphy configuration\n");
1190 	/* set reference clock */
1191 	mask = HPIPE_MISC_ICP_FORCE_MASK;
1192 	data = (speed == PHY_SPEED_5_15625G) ?
1193 		(0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) :
1194 		(0x1 << HPIPE_MISC_ICP_FORCE_OFFSET);
1195 	mask |= HPIPE_MISC_REFCLK_SEL_MASK;
1196 	data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
1197 	reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
1198 	/* Power and PLL Control */
1199 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1200 	data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1201 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1202 	data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1203 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1204 	/* Loopback register */
1205 	mask = HPIPE_LOOPBACK_SEL_MASK;
1206 	data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
1207 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
1208 	/* rx control 1 */
1209 	mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
1210 	data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
1211 	mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
1212 	data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
1213 	reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1214 	/* DTL Control */
1215 	mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
1216 	data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
1217 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
1218 
1219 	/* Transmitter/Receiver Speed Divider Force */
1220 	if (speed == PHY_SPEED_5_15625G) {
1221 		mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK;
1222 		data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET;
1223 		mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK;
1224 		data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET;
1225 		mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK;
1226 		data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET;
1227 		mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK;
1228 		data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET;
1229 	} else {
1230 		mask = HPIPE_TXDIGCK_DIV_FORCE_MASK;
1231 		data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET;
1232 	}
1233 	reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);
1234 
1235 	/* Set analog paramters from ETP(HW) */
1236 	debug("stage: Analog paramters from ETP(HW)\n");
1237 	/* SERDES External Configuration 2 */
1238 	mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK;
1239 	data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET;
1240 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
1241 	/* 0x7-DFE Resolution control */
1242 	mask = HPIPE_DFE_RES_FORCE_MASK;
1243 	data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
1244 	reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1245 	/* 0xd-G1_Setting_0 */
1246 	if (speed == PHY_SPEED_5_15625G) {
1247 		mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
1248 		data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
1249 	} else {
1250 		mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
1251 		data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
1252 		mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
1253 		data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
1254 	}
1255 	reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
1256 	/* Genration 1 setting 2 (G1_Setting_2) */
1257 	mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK;
1258 	data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET;
1259 	mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK;
1260 	data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET;
1261 	reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
1262 	/* Transmitter Slew Rate Control register (tx_reg1) */
1263 	mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK;
1264 	data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET;
1265 	mask |= HPIPE_TX_REG1_SLC_EN_MASK;
1266 	data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET;
1267 	reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask);
1268 	/* Impedance Calibration Control register (cal_reg1) */
1269 	mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK;
1270 	data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
1271 	mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK;
1272 	data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET;
1273 	reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask);
1274 	/* Generation 1 Setting 5 (g1_setting_5) */
1275 	mask = HPIPE_G1_SETTING_5_G1_ICP_MASK;
1276 	data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
1277 	reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
1278 	/* 0xE-G1_Setting_1 */
1279 	mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
1280 	data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1281 	if (speed == PHY_SPEED_5_15625G) {
1282 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1283 		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1284 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
1285 		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
1286 	} else {
1287 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1288 		data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1289 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
1290 		data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
1291 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
1292 		data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
1293 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
1294 		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
1295 		mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
1296 		data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
1297 	}
1298 	reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1299 
1300 	/* 0xA-DFE_Reg3 */
1301 	mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1302 	data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1303 	mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1304 	data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1305 	reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1306 
1307 	/* 0x111-G1_Setting_4 */
1308 	mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1309 	data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1310 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1311 	/* Genration 1 setting 3 (G1_Setting_3) */
1312 	mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK;
1313 	data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET;
1314 	if (speed == PHY_SPEED_5_15625G) {
1315 		/* Force FFE (Feed Forward Equalization) to 5G */
1316 		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
1317 		data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
1318 		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
1319 		data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
1320 		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
1321 		data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
1322 	}
1323 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1324 
1325 	/* Connfigure RX training timer */
1326 	mask = HPIPE_RX_TRAIN_TIMER_MASK;
1327 	data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET;
1328 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1329 
1330 	/* Enable TX train peak to peak hold */
1331 	mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
1332 	data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
1333 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1334 
1335 	/* Configure TX preset index */
1336 	mask = HPIPE_TX_PRESET_INDEX_MASK;
1337 	data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET;
1338 	reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask);
1339 
1340 	/* Disable pattern lock lost timeout */
1341 	mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
1342 	data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
1343 	reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1344 
1345 	/* Configure TX training pattern and TX training 16bit auto */
1346 	mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK;
1347 	data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET;
1348 	mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK;
1349 	data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET;
1350 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1351 
1352 	/* Configure Training patten number */
1353 	mask = HPIPE_TRAIN_PAT_NUM_MASK;
1354 	data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET;
1355 	reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask);
1356 
1357 	/* Configure differencial manchester encoter to ethernet mode */
1358 	mask = HPIPE_DME_ETHERNET_MODE_MASK;
1359 	data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET;
1360 	reg_set(hpipe_addr + HPIPE_DME_REG, data, mask);
1361 
1362 	/* Configure VDD Continuous Calibration */
1363 	mask = HPIPE_CAL_VDD_CONT_MODE_MASK;
1364 	data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET;
1365 	reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask);
1366 
1367 	/* Trigger sampler enable pulse (by toggleing the bit) */
1368 	mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK;
1369 	data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET;
1370 	mask |= HPIPE_SMAPLER_MASK;
1371 	data |= 0x1 << HPIPE_SMAPLER_OFFSET;
1372 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1373 	mask = HPIPE_SMAPLER_MASK;
1374 	data = 0x0 << HPIPE_SMAPLER_OFFSET;
1375 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1376 
1377 	/* Set External RX Regulator Control */
1378 	mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
1379 	data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
1380 	reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1381 
1382 	debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1383 	/* SERDES External Configuration */
1384 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1385 	data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1386 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1387 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1388 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1389 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1390 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1391 
1392 
1393 	/* check PLL rx & tx ready */
1394 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1395 	data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1396 		SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1397 	mask = data;
1398 	data = polling_with_timeout(addr, data, mask, 15000);
1399 	if (data != 0) {
1400 		debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1401 		error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
1402 		      (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1403 		      (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1404 		ret = 0;
1405 	}
1406 
1407 	/* RX init */
1408 	mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1409 	data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1410 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1411 
1412 
1413 	/* check that RX init done */
1414 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1415 	data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1416 	mask = data;
1417 	data = polling_with_timeout(addr, data, mask, 100);
1418 	if (data != 0) {
1419 		debug("Read from reg = %p - value = 0x%x\n",
1420 		      sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1421 		error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
1422 		ret = 0;
1423 	}
1424 
1425 	debug("stage: RF Reset\n");
1426 	/* RF Reset */
1427 	mask =  SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1428 	data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1429 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1430 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1431 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1432 
1433 	debug_exit();
1434 	return ret;
1435 }
1436 
1437 static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base,
1438 				  void __iomem *comphy_base)
1439 {
1440 	u32 mask, data, ret = 1;
1441 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
1442 	void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
1443 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
1444 	void __iomem *addr;
1445 
1446 	debug_enter();
1447 	debug("stage: RFU configurations - hard reset comphy\n");
1448 	/* RFU configurations - hard reset comphy */
1449 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1450 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1451 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1452 	data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1453 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1454 
1455 	if (lane == 2) {
1456 		reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1457 			0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
1458 			COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
1459 	}
1460 	if (lane == 4) {
1461 		reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1462 			0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
1463 			COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
1464 	}
1465 
1466 	/* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
1467 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1468 	data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1469 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
1470 	data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1471 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
1472 	data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1473 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1474 	data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1475 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1476 	data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1477 	mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
1478 	data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
1479 	mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
1480 	data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
1481 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1482 
1483 	/* release from hard reset */
1484 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1485 	data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1486 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1487 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1488 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1489 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1490 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1491 
1492 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1493 	data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1494 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1495 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1496 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1497 
1498 	/* Wait 1ms - until band gap and ref clock ready */
1499 	mdelay(1);
1500 
1501 	/* Start comphy Configuration */
1502 	debug("stage: Comphy configuration\n");
1503 	/* set reference clock */
1504 	reg_set(hpipe_addr + HPIPE_MISC_REG,
1505 		0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
1506 		HPIPE_MISC_REFCLK_SEL_MASK);
1507 	/* Power and PLL Control */
1508 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1509 	data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1510 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1511 	data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1512 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1513 	/* Loopback register */
1514 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
1515 		0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
1516 	/* rx control 1 */
1517 	mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
1518 	data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
1519 	mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
1520 	data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
1521 	reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1522 	/* DTL Control */
1523 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
1524 		0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
1525 		HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
1526 
1527 	/* Set analog paramters from ETP(HW) */
1528 	debug("stage: Analog paramters from ETP(HW)\n");
1529 	/* SERDES External Configuration 2 */
1530 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
1531 		0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
1532 		SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
1533 	/* 0x7-DFE Resolution control */
1534 	reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
1535 		HPIPE_DFE_RES_FORCE_MASK);
1536 	/* 0xd-G1_Setting_0 */
1537 	reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
1538 		0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
1539 		HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
1540 	/* 0xE-G1_Setting_1 */
1541 	mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1542 	data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1543 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
1544 	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
1545 	mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
1546 	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1547 	reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1548 	/* 0xA-DFE_Reg3 */
1549 	mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1550 	data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1551 	mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1552 	data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1553 	reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1554 
1555 	/* 0x111-G1_Setting_4 */
1556 	mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1557 	data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1558 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1559 
1560 	debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1561 	/* SERDES External Configuration */
1562 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1563 	data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1564 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1565 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1566 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1567 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1568 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1569 
1570 
1571 	/* check PLL rx & tx ready */
1572 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1573 	data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1574 		SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1575 	mask = data;
1576 	data = polling_with_timeout(addr, data, mask, 15000);
1577 	if (data != 0) {
1578 		debug("Read from reg = %p - value = 0x%x\n",
1579 		      sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1580 		error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
1581 		      (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1582 		      (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1583 		ret = 0;
1584 	}
1585 
1586 	/* RX init */
1587 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
1588 		0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
1589 		SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
1590 
1591 	/* check that RX init done */
1592 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1593 	data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1594 	mask = data;
1595 	data = polling_with_timeout(addr, data, mask, 100);
1596 	if (data != 0) {
1597 		debug("Read from reg = %p - value = 0x%x\n",
1598 		      sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1599 		error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
1600 		ret = 0;
1601 	}
1602 
1603 	debug("stage: RF Reset\n");
1604 	/* RF Reset */
1605 	mask =  SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1606 	data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1607 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1608 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1609 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1610 
1611 	debug_exit();
1612 	return ret;
1613 }
1614 
1615 static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
1616 				   void __iomem *usb_cfg_addr,
1617 				   void __iomem *utmi_cfg_addr,
1618 				   u32 utmi_phy_port)
1619 {
1620 	u32 mask, data;
1621 
1622 	debug_enter();
1623 	debug("stage:  UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n",
1624 	      utmi_index);
1625 	/* Power down UTMI PHY */
1626 	reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET,
1627 		UTMI_PHY_CFG_PU_MASK);
1628 
1629 	/*
1630 	 * If UTMI connected to USB Device, configure mux prior to PHY init
1631 	 * (Device can be connected to UTMI0 or to UTMI1)
1632 	 */
1633 	if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) {
1634 		debug("stage:  UTMI %d - Enable Device mode and configure UTMI mux\n",
1635 		      utmi_index);
1636 		/* USB3 Device UTMI enable */
1637 		mask = UTMI_USB_CFG_DEVICE_EN_MASK;
1638 		data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
1639 		/* USB3 Device UTMI MUX */
1640 		mask |= UTMI_USB_CFG_DEVICE_MUX_MASK;
1641 		data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET;
1642 		reg_set(usb_cfg_addr,  data, mask);
1643 	}
1644 
1645 	/* Set Test suspendm mode */
1646 	mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK;
1647 	data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET;
1648 	/* Enable Test UTMI select */
1649 	mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK;
1650 	data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET;
1651 	reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask);
1652 
1653 	/* Wait for UTMI power down */
1654 	mdelay(1);
1655 
1656 	debug_exit();
1657 	return;
1658 }
1659 
1660 static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
1661 				   void __iomem *usb_cfg_addr,
1662 				   void __iomem *utmi_cfg_addr,
1663 				   u32 utmi_phy_port)
1664 {
1665 	u32 mask, data;
1666 
1667 	debug_exit();
1668 	debug("stage: Configure UTMI PHY %d registers\n", utmi_index);
1669 	/* Reference Clock Divider Select */
1670 	mask = UTMI_PLL_CTRL_REFDIV_MASK;
1671 	data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET;
1672 	/* Feedback Clock Divider Select - 90 for 25Mhz*/
1673 	mask |= UTMI_PLL_CTRL_FBDIV_MASK;
1674 	data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET;
1675 	/* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
1676 	mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
1677 	data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
1678 	reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask);
1679 
1680 	/* Impedance Calibration Threshold Setting */
1681 	reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
1682 		0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
1683 		UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
1684 
1685 	/* Set LS TX driver strength coarse control */
1686 	mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
1687 	data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
1688 	/* Set LS TX driver fine adjustment */
1689 	mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
1690 	data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
1691 	reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
1692 
1693 	/* Enable SQ */
1694 	mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
1695 	data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
1696 	/* Enable analog squelch detect */
1697 	mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
1698 	data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
1699 	reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
1700 
1701 	/* Set External squelch calibration number */
1702 	mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK;
1703 	data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET;
1704 	/* Enable the External squelch calibration */
1705 	mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK;
1706 	data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET;
1707 	reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask);
1708 
1709 	/* Set Control VDAT Reference Voltage - 0.325V */
1710 	mask = UTMI_CHGDTC_CTRL_VDAT_MASK;
1711 	data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET;
1712 	/* Set Control VSRC Reference Voltage - 0.6V */
1713 	mask |= UTMI_CHGDTC_CTRL_VSRC_MASK;
1714 	data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET;
1715 	reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask);
1716 
1717 	debug_exit();
1718 	return;
1719 }
1720 
1721 static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
1722 				void __iomem *usb_cfg_addr,
1723 				void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
1724 {
1725 	u32 data, mask, ret = 1;
1726 	void __iomem *addr;
1727 
1728 	debug_enter();
1729 	debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n",
1730 	      utmi_index);
1731 	/* Power UP UTMI PHY */
1732 	reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET,
1733 		UTMI_PHY_CFG_PU_MASK);
1734 	/* Disable Test UTMI select */
1735 	reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG,
1736 		0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET,
1737 		UTMI_CTRL_STATUS0_TEST_SEL_MASK);
1738 
1739 	debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
1740 	addr = utmi_base_addr + UTMI_CALIB_CTRL_REG;
1741 	data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
1742 	mask = data;
1743 	data = polling_with_timeout(addr, data, mask, 100);
1744 	if (data != 0) {
1745 		error("Impedance calibration is not done\n");
1746 		debug("Read from reg = %p - value = 0x%x\n", addr, data);
1747 		ret = 0;
1748 	}
1749 
1750 	data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK;
1751 	mask = data;
1752 	data = polling_with_timeout(addr, data, mask, 100);
1753 	if (data != 0) {
1754 		error("PLL calibration is not done\n");
1755 		debug("Read from reg = %p - value = 0x%x\n", addr, data);
1756 		ret = 0;
1757 	}
1758 
1759 	addr = utmi_base_addr + UTMI_PLL_CTRL_REG;
1760 	data = UTMI_PLL_CTRL_PLL_RDY_MASK;
1761 	mask = data;
1762 	data = polling_with_timeout(addr, data, mask, 100);
1763 	if (data != 0) {
1764 		error("PLL is not ready\n");
1765 		debug("Read from reg = %p - value = 0x%x\n", addr, data);
1766 		ret = 0;
1767 	}
1768 
1769 	if (ret)
1770 		debug("Passed\n");
1771 	else
1772 		debug("\n");
1773 
1774 	debug_exit();
1775 	return ret;
1776 }
1777 
1778 /*
1779  * comphy_utmi_phy_init initialize the UTMI PHY
1780  * the init split in 3 parts:
1781  * 1. Power down transceiver and PLL
1782  * 2. UTMI PHY configure
1783  * 3. Powe up transceiver and PLL
1784  * Note: - Power down/up should be once for both UTMI PHYs
1785  *       - comphy_dedicated_phys_init call this function if at least there is
1786  *         one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
1787  *         legal
1788  */
1789 static void comphy_utmi_phy_init(u32 utmi_phy_count,
1790 				 struct utmi_phy_data *cp110_utmi_data)
1791 {
1792 	u32 i;
1793 
1794 	debug_enter();
1795 	/* UTMI Power down */
1796 	for (i = 0; i < utmi_phy_count; i++) {
1797 		comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr,
1798 				       cp110_utmi_data[i].usb_cfg_addr,
1799 				       cp110_utmi_data[i].utmi_cfg_addr,
1800 				       cp110_utmi_data[i].utmi_phy_port);
1801 	}
1802 	/* PLL Power down */
1803 	debug("stage: UTMI PHY power down PLL\n");
1804 	for (i = 0; i < utmi_phy_count; i++) {
1805 		reg_set(cp110_utmi_data[i].usb_cfg_addr,
1806 			0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
1807 	}
1808 	/* UTMI configure */
1809 	for (i = 0; i < utmi_phy_count; i++) {
1810 		comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr,
1811 				       cp110_utmi_data[i].usb_cfg_addr,
1812 				       cp110_utmi_data[i].utmi_cfg_addr,
1813 				       cp110_utmi_data[i].utmi_phy_port);
1814 	}
1815 	/* UTMI Power up */
1816 	for (i = 0; i < utmi_phy_count; i++) {
1817 		if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr,
1818 					  cp110_utmi_data[i].usb_cfg_addr,
1819 					  cp110_utmi_data[i].utmi_cfg_addr,
1820 					  cp110_utmi_data[i].utmi_phy_port)) {
1821 			error("Failed to initialize UTMI PHY %d\n", i);
1822 			continue;
1823 		}
1824 		printf("UTMI PHY %d initialized to ", i);
1825 		if (cp110_utmi_data[i].utmi_phy_port ==
1826 		    UTMI_PHY_TO_USB3_DEVICE0)
1827 			printf("USB Device\n");
1828 		else
1829 			printf("USB Host%d\n",
1830 			       cp110_utmi_data[i].utmi_phy_port);
1831 	}
1832 	/* PLL Power up */
1833 	debug("stage: UTMI PHY power up PLL\n");
1834 	for (i = 0; i < utmi_phy_count; i++) {
1835 		reg_set(cp110_utmi_data[i].usb_cfg_addr,
1836 			0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
1837 	}
1838 
1839 	debug_exit();
1840 	return;
1841 }
1842 
1843 /*
1844  * comphy_dedicated_phys_init initialize the dedicated PHYs
1845  * - not muxed SerDes lanes e.g. UTMI PHY
1846  */
1847 void comphy_dedicated_phys_init(void)
1848 {
1849 	struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
1850 	int node;
1851 	int i;
1852 
1853 	debug_enter();
1854 	debug("Initialize USB UTMI PHYs\n");
1855 
1856 	/* Find the UTMI phy node in device tree and go over them */
1857 	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
1858 					     "marvell,mvebu-utmi-2.6.0");
1859 
1860 	i = 0;
1861 	while (node > 0) {
1862 		/* get base address of UTMI phy */
1863 		cp110_utmi_data[i].utmi_base_addr =
1864 			(void __iomem *)fdtdec_get_addr_size_auto_noparent(
1865 				gd->fdt_blob, node, "reg", 0, NULL, true);
1866 		if (cp110_utmi_data[i].utmi_base_addr == NULL) {
1867 			error("UTMI PHY base address is invalid\n");
1868 			i++;
1869 			continue;
1870 		}
1871 
1872 		/* get usb config address */
1873 		cp110_utmi_data[i].usb_cfg_addr =
1874 			(void __iomem *)fdtdec_get_addr_size_auto_noparent(
1875 				gd->fdt_blob, node, "reg", 1, NULL, true);
1876 		if (cp110_utmi_data[i].usb_cfg_addr == NULL) {
1877 			error("UTMI PHY base address is invalid\n");
1878 			i++;
1879 			continue;
1880 		}
1881 
1882 		/* get UTMI config address */
1883 		cp110_utmi_data[i].utmi_cfg_addr =
1884 			(void __iomem *)fdtdec_get_addr_size_auto_noparent(
1885 				gd->fdt_blob, node, "reg", 2, NULL, true);
1886 		if (cp110_utmi_data[i].utmi_cfg_addr == NULL) {
1887 			error("UTMI PHY base address is invalid\n");
1888 			i++;
1889 			continue;
1890 		}
1891 
1892 		/*
1893 		 * get the port number (to check if the utmi connected to
1894 		 * host/device)
1895 		 */
1896 		cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int(
1897 			gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
1898 		if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) {
1899 			error("UTMI PHY port type is invalid\n");
1900 			i++;
1901 			continue;
1902 		}
1903 
1904 		node = fdt_node_offset_by_compatible(
1905 			gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0");
1906 		i++;
1907 	}
1908 
1909 	if (i > 0)
1910 		comphy_utmi_phy_init(i, cp110_utmi_data);
1911 
1912 	debug_exit();
1913 }
1914 
1915 static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
1916 				  struct comphy_map *serdes_map)
1917 {
1918 	void __iomem *comphy_base_addr;
1919 	struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS];
1920 	struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS];
1921 	u32 lane, comphy_max_count;
1922 
1923 	comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
1924 	comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
1925 
1926 	/*
1927 	 * Copy the SerDes map configuration for PIPE map and PHY map
1928 	 * the comphy_mux_init modify the type of the lane if the type
1929 	 * is not valid because we have 2 selectores run the
1930 	 * comphy_mux_init twice and after that update the original
1931 	 * serdes_map
1932 	 */
1933 	for (lane = 0; lane < comphy_max_count; lane++) {
1934 		comphy_map_pipe_data[lane].type = serdes_map[lane].type;
1935 		comphy_map_pipe_data[lane].speed = serdes_map[lane].speed;
1936 		comphy_map_phy_data[lane].type = serdes_map[lane].type;
1937 		comphy_map_phy_data[lane].speed = serdes_map[lane].speed;
1938 	}
1939 	ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data;
1940 	comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data,
1941 			comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET);
1942 
1943 	ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data;
1944 	comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data,
1945 			comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
1946 	/* Fix the type after check the PHY and PIPE configuration */
1947 	for (lane = 0; lane < comphy_max_count; lane++) {
1948 		if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
1949 		    (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
1950 			serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
1951 	}
1952 }
1953 
1954 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
1955 		      struct comphy_map *serdes_map)
1956 {
1957 	struct comphy_map *ptr_comphy_map;
1958 	void __iomem *comphy_base_addr, *hpipe_base_addr;
1959 	u32 comphy_max_count, lane, ret = 0;
1960 	u32 pcie_width = 0;
1961 
1962 	debug_enter();
1963 
1964 	comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
1965 	comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
1966 	hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
1967 
1968 	/* Config Comphy mux configuration */
1969 	comphy_mux_cp110_init(ptr_chip_cfg, serdes_map);
1970 
1971 	/* Check if the first 4 lanes configured as By-4 */
1972 	for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
1973 	     lane++, ptr_comphy_map++) {
1974 		if (ptr_comphy_map->type != PHY_TYPE_PEX0)
1975 			break;
1976 		pcie_width++;
1977 	}
1978 
1979 	for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count;
1980 	     lane++, ptr_comphy_map++) {
1981 		debug("Initialize serdes number %d\n", lane);
1982 		debug("Serdes type = 0x%x\n", ptr_comphy_map->type);
1983 		if (lane == 4) {
1984 			/*
1985 			 * PCIe lanes above the first 4 lanes, can be only
1986 			 * by1
1987 			 */
1988 			pcie_width = 1;
1989 		}
1990 		switch (ptr_comphy_map->type) {
1991 		case PHY_TYPE_UNCONNECTED:
1992 		case PHY_TYPE_IGNORE:
1993 			continue;
1994 			break;
1995 		case PHY_TYPE_PEX0:
1996 		case PHY_TYPE_PEX1:
1997 		case PHY_TYPE_PEX2:
1998 		case PHY_TYPE_PEX3:
1999 			ret = comphy_pcie_power_up(
2000 				lane, pcie_width, ptr_comphy_map->clk_src,
2001 				serdes_map->end_point,
2002 				hpipe_base_addr, comphy_base_addr);
2003 			break;
2004 		case PHY_TYPE_SATA0:
2005 		case PHY_TYPE_SATA1:
2006 		case PHY_TYPE_SATA2:
2007 		case PHY_TYPE_SATA3:
2008 			ret = comphy_sata_power_up(
2009 				lane, hpipe_base_addr, comphy_base_addr,
2010 				ptr_chip_cfg->cp_index);
2011 			break;
2012 		case PHY_TYPE_USB3_HOST0:
2013 		case PHY_TYPE_USB3_HOST1:
2014 		case PHY_TYPE_USB3_DEVICE:
2015 			ret = comphy_usb3_power_up(lane, hpipe_base_addr,
2016 						   comphy_base_addr);
2017 			break;
2018 		case PHY_TYPE_SGMII0:
2019 		case PHY_TYPE_SGMII1:
2020 		case PHY_TYPE_SGMII2:
2021 		case PHY_TYPE_SGMII3:
2022 			if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
2023 				debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
2024 				      lane);
2025 				ptr_comphy_map->speed = PHY_SPEED_1_25G;
2026 			}
2027 			ret = comphy_sgmii_power_up(
2028 				lane, ptr_comphy_map->speed, hpipe_base_addr,
2029 				comphy_base_addr);
2030 			break;
2031 		case PHY_TYPE_SFI:
2032 			ret = comphy_sfi_power_up(lane, hpipe_base_addr,
2033 						  comphy_base_addr,
2034 						  ptr_comphy_map->speed);
2035 			break;
2036 		case PHY_TYPE_RXAUI0:
2037 		case PHY_TYPE_RXAUI1:
2038 			ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
2039 						     comphy_base_addr);
2040 			break;
2041 		default:
2042 			debug("Unknown SerDes type, skip initialize SerDes %d\n",
2043 			      lane);
2044 			break;
2045 		}
2046 		if (ret == 0) {
2047 			/*
2048 			 * If interface wans't initialized, set the lane to
2049 			 * PHY_TYPE_UNCONNECTED state.
2050 			 */
2051 			ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
2052 			error("PLL is not locked - Failed to initialize lane %d\n",
2053 			      lane);
2054 		}
2055 	}
2056 
2057 	debug_exit();
2058 	return 0;
2059 }
2060