1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015-2016 Marvell International Ltd.
4  */
5 
6 #include <common.h>
7 #include <fdtdec.h>
8 #include <asm/io.h>
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/soc.h>
11 
12 #include "comphy_core.h"
13 #include "comphy_hpipe.h"
14 #include "sata.h"
15 #include "utmi_phy.h"
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 #define SD_ADDR(base, lane)			(base + 0x1000 * lane)
20 #define HPIPE_ADDR(base, lane)			(SD_ADDR(base, lane) + 0x800)
21 #define COMPHY_ADDR(base, lane)			(base + 0x28 * lane)
22 
23 struct utmi_phy_data {
24 	void __iomem *utmi_base_addr;
25 	void __iomem *usb_cfg_addr;
26 	void __iomem *utmi_cfg_addr;
27 	u32 utmi_phy_port;
28 };
29 
30 /*
31  * For CP-110 we have 2 Selector registers "PHY Selectors",
32  * and "PIPE Selectors".
33  * PIPE selector include USB and PCIe options.
34  * PHY selector include the Ethernet and SATA options, every Ethernet
35  * option has different options, for example: serdes lane2 had option
36  * Eth_port_0 that include (SGMII0, RXAUI0, SFI)
37  */
38 struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
39 	{4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
40 	     {PHY_TYPE_SATA1, 0x4} } },
41 	{4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
42 	     {PHY_TYPE_SATA0, 0x4} } },
43 	{6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
44 	     {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
45 	     {PHY_TYPE_SATA0, 0x4} } },
46 	{8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
47 	     {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
48 	{7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
49 	     {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
50 	     {PHY_TYPE_SGMII1, 0x1} } },
51 	{6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
52 	     {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
53 };
54 
55 struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
56 	{2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
57 	{4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
58 	     {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
59 	     {PHY_TYPE_PEX0, 0x4} } },
60 	{3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
61 	     {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
62 	{3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
63 	     {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
64 	{4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
65 	     {PHY_TYPE_USB3_HOST1, 0x1},
66 	     {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
67 	{2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
68 };
69 
70 static u32 polling_with_timeout(void __iomem *addr, u32 val,
71 				u32 mask, unsigned long usec_timout)
72 {
73 	u32 data;
74 
75 	do {
76 		udelay(1);
77 		data = readl(addr) & mask;
78 	} while (data != val  && --usec_timout > 0);
79 
80 	if (usec_timout == 0)
81 		return data;
82 
83 	return 0;
84 }
85 
86 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
87 				bool is_end_point, void __iomem *hpipe_base,
88 				void __iomem *comphy_base)
89 {
90 	u32 mask, data, ret = 1;
91 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
92 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
93 	void __iomem *addr;
94 	u32 pcie_clk = 0; /* set input by default */
95 
96 	debug_enter();
97 
98 	/*
99 	 * ToDo:
100 	 * Add SAR (Sample-At-Reset) configuration for the PCIe clock
101 	 * direction. SAR code is currently not ported from Marvell
102 	 * U-Boot to mainline version.
103 	 *
104 	 * SerDes Lane 4/5 got the PCIe ref-clock #1,
105 	 * and SerDes Lane 0 got PCIe ref-clock #0
106 	 */
107 	debug("PCIe clock = %x\n", pcie_clk);
108 	debug("PCIe RC    = %d\n", !is_end_point);
109 	debug("PCIe width = %d\n", pcie_width);
110 
111 	/* enable PCIe by4 and by2 */
112 	if (lane == 0) {
113 		if (pcie_width == 4) {
114 			reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
115 				0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET,
116 				COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
117 		} else if (pcie_width == 2) {
118 			reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
119 				0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET,
120 				COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
121 		}
122 	}
123 
124 	/*
125 	 * If PCIe clock is output and clock source from SerDes lane 5,
126 	 * we need to configure the clock-source MUX.
127 	 * By default, the clock source is from lane 4
128 	 */
129 	if (pcie_clk && clk_src && (lane == 5)) {
130 		reg_set((void __iomem *)DFX_DEV_GEN_CTRL12,
131 			0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET,
132 			DFX_DEV_GEN_PCIE_CLK_SRC_MASK);
133 	}
134 
135 	debug("stage: RFU configurations - hard reset comphy\n");
136 	/* RFU configurations - hard reset comphy */
137 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
138 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
139 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
140 	data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
141 	mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
142 	data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
143 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
144 	data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
145 	mask |= COMMON_PHY_PHY_MODE_MASK;
146 	data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
147 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
148 
149 	/* release from hard reset */
150 	mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
151 	data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
152 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
153 	data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
154 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
155 
156 	/* Wait 1ms - until band gap and ref clock ready */
157 	mdelay(1);
158 	/* Start comphy Configuration */
159 	debug("stage: Comphy configuration\n");
160 	/* Set PIPE soft reset */
161 	mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
162 	data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
163 	/* Set PHY datapath width mode for V0 */
164 	mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
165 	data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
166 	/* Set Data bus width USB mode for V0 */
167 	mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
168 	data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
169 	/* Set CORE_CLK output frequency for 250Mhz */
170 	mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
171 	data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
172 	reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
173 	/* Set PLL ready delay for 0x2 */
174 	data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
175 	mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
176 	if (pcie_width != 1) {
177 		data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET;
178 		mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK;
179 		data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
180 		mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
181 	}
182 	reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
183 
184 	/* Set PIPE mode interface to PCIe3 - 0x1  & set lane order */
185 	data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
186 	mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
187 	if (pcie_width != 1) {
188 		mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK;
189 		mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK;
190 		mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
191 		if (lane == 0) {
192 			data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET;
193 			data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
194 		} else if (lane == (pcie_width - 1)) {
195 			data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
196 		}
197 	}
198 	reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
199 	/* Config update polarity equalization */
200 	reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG,
201 		0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET,
202 		HPIPE_CFG_UPDATE_POLARITY_MASK);
203 	/* Set PIPE version 4 to mode enable */
204 	reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG,
205 		0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET,
206 		HPIPE_DFE_CTRL_28_PIPE4_MASK);
207 	/* TODO: check if pcie clock is output/input - for bringup use input*/
208 	/* Enable PIN clock 100M_125M */
209 	mask = 0;
210 	data = 0;
211 	/* Only if clock is output, configure the clock-source mux */
212 	if (pcie_clk) {
213 		mask |= HPIPE_MISC_CLK100M_125M_MASK;
214 		data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
215 	}
216 	/*
217 	 * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz
218 	 * clock
219 	 */
220 	mask |= HPIPE_MISC_TXDCLK_2X_MASK;
221 	data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
222 	/* Enable 500MHz Clock */
223 	mask |= HPIPE_MISC_CLK500_EN_MASK;
224 	data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
225 	if (pcie_clk) { /* output */
226 		/* Set reference clock comes from group 1 */
227 		mask |= HPIPE_MISC_REFCLK_SEL_MASK;
228 		data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
229 	} else {
230 		/* Set reference clock comes from group 2 */
231 		mask |= HPIPE_MISC_REFCLK_SEL_MASK;
232 		data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
233 	}
234 	mask |= HPIPE_MISC_ICP_FORCE_MASK;
235 	data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
236 	reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
237 	if (pcie_clk) { /* output */
238 		/* Set reference frequcency select - 0x2 for 25MHz*/
239 		mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
240 		data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
241 	} else {
242 		/* Set reference frequcency select - 0x0 for 100MHz*/
243 		mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
244 		data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
245 	}
246 	/* Set PHY mode to PCIe */
247 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
248 	data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
249 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
250 
251 	/* ref clock alignment */
252 	if (pcie_width != 1) {
253 		mask = HPIPE_LANE_ALIGN_OFF_MASK;
254 		data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET;
255 		reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
256 	}
257 
258 	/*
259 	 * Set the amount of time spent in the LoZ state - set for 0x7 only if
260 	 * the PCIe clock is output
261 	 */
262 	if (pcie_clk) {
263 		reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
264 			0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
265 			HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
266 	}
267 
268 	/* Set Maximal PHY Generation Setting(8Gbps) */
269 	mask = HPIPE_INTERFACE_GEN_MAX_MASK;
270 	data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
271 	/* Bypass frame detection and sync detection for RX DATA */
272 	mask = HPIPE_INTERFACE_DET_BYPASS_MASK;
273 	data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
274 	/* Set Link Train Mode (Tx training control pins are used) */
275 	mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
276 	data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
277 	reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
278 
279 	/* Set Idle_sync enable */
280 	mask = HPIPE_PCIE_IDLE_SYNC_MASK;
281 	data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
282 	/* Select bits for PCIE Gen3(32bit) */
283 	mask |= HPIPE_PCIE_SEL_BITS_MASK;
284 	data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
285 	reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
286 
287 	/* Enable Tx_adapt_g1 */
288 	mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
289 	data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
290 	/* Enable Tx_adapt_gn1 */
291 	mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
292 	data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
293 	/* Disable Tx_adapt_g0 */
294 	mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
295 	data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
296 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
297 
298 	/* Set reg_tx_train_chk_init */
299 	mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
300 	data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
301 	/* Enable TX_COE_FM_PIN_PCIE3_EN */
302 	mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
303 	data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
304 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
305 
306 	debug("stage: TRx training parameters\n");
307 	/* Set Preset sweep configurations */
308 	mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK;
309 	data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET;
310 
311 	mask |= HPIPE_TX_NUM_OF_PRESET_MASK;
312 	data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET;
313 
314 	mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK;
315 	data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET;
316 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
317 
318 	/* Tx train start configuration */
319 	mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK;
320 	data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET;
321 
322 	mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK;
323 	data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET;
324 
325 	mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK;
326 	data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET;
327 
328 	mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
329 	data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET;
330 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
331 
332 	/* Enable Tx train P2P */
333 	mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
334 	data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
335 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
336 
337 	/* Configure Tx train timeout */
338 	mask = HPIPE_TRX_TRAIN_TIMER_MASK;
339 	data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET;
340 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
341 
342 	/* Disable G0/G1/GN1 adaptation */
343 	mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK
344 		| HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
345 	data = 0;
346 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
347 
348 	/* Disable DTL frequency loop */
349 	mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
350 	data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
351 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
352 
353 	/* Configure G3 DFE */
354 	mask = HPIPE_G3_DFE_RES_MASK;
355 	data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
356 	reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
357 
358 	/* Use TX/RX training result for DFE */
359 	mask = HPIPE_DFE_RES_FORCE_MASK;
360 	data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
361 	reg_set(hpipe_addr + HPIPE_DFE_REG0,  data, mask);
362 
363 	/* Configure initial and final coefficient value for receiver */
364 	mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
365 	data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
366 
367 	mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
368 	data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
369 
370 	mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
371 	data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
372 	reg_set(hpipe_addr + HPIPE_G3_SET_1_REG,  data, mask);
373 
374 	/* Trigger sampler enable pulse */
375 	mask = HPIPE_SMAPLER_MASK;
376 	data = 0x1 << HPIPE_SMAPLER_OFFSET;
377 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
378 	udelay(5);
379 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask);
380 
381 	/* FFE resistor tuning for different bandwidth  */
382 	mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
383 	data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
384 
385 	mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
386 	data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
387 	reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
388 
389 	/* Pattern lock lost timeout disable */
390 	mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
391 	data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
392 	reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
393 
394 	/* Configure DFE adaptations */
395 	mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
396 	data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
397 	mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
398 	data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
399 	mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
400 	data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
401 	reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
402 	mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
403 	data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
404 	reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
405 
406 	/* Genration 2 setting 1*/
407 	mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
408 	data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
409 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
410 	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
411 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
412 	data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
413 	reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
414 
415 	/* DFE enable */
416 	mask = HPIPE_G2_DFE_RES_MASK;
417 	data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
418 	reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
419 
420 	/* Configure DFE Resolution */
421 	mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
422 	data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
423 	reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
424 
425 	/* VDD calibration control */
426 	mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
427 	data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
428 	reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
429 
430 	/* Set PLL Charge-pump Current Control */
431 	mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
432 	data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
433 	reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
434 
435 	/* Set lane rqualization remote setting */
436 	mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
437 	data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
438 	mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
439 	data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
440 	mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
441 	data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
442 	reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
443 
444 	if (!is_end_point) {
445 		/* Set phy in root complex mode */
446 		mask = HPIPE_CFG_PHY_RC_EP_MASK;
447 		data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
448 		reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
449 	}
450 
451 	debug("stage: Comphy power up\n");
452 
453 	/*
454 	 * For PCIe by4 or by2 - release from reset only after finish to
455 	 * configure all lanes
456 	 */
457 	if ((pcie_width == 1) || (lane == (pcie_width - 1))) {
458 		u32 i, start_lane, end_lane;
459 
460 		if (pcie_width != 1) {
461 			/* allows writing to all lanes in one write */
462 			reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
463 				0x0 <<
464 				COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
465 				COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
466 			start_lane = 0;
467 			end_lane = pcie_width;
468 
469 			/*
470 			 * Release from PIPE soft reset
471 			 * for PCIe by4 or by2 - release from soft reset
472 			 * all lanes - can't use read modify write
473 			 */
474 			reg_set(HPIPE_ADDR(hpipe_base, 0) +
475 				HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff);
476 		} else {
477 			start_lane = lane;
478 			end_lane = lane + 1;
479 
480 			/*
481 			 * Release from PIPE soft reset
482 			 * for PCIe by4 or by2 - release from soft reset
483 			 * all lanes
484 			 */
485 			reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
486 				0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
487 				HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
488 		}
489 
490 
491 		if (pcie_width != 1) {
492 			/* disable writing to all lanes with one write */
493 			reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
494 				0x3210 <<
495 				COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
496 				COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
497 		}
498 
499 		debug("stage: Check PLL\n");
500 		/* Read lane status */
501 		for (i = start_lane; i < end_lane; i++) {
502 			addr = HPIPE_ADDR(hpipe_base, i) +
503 				HPIPE_LANE_STATUS1_REG;
504 			data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
505 			mask = data;
506 			data = polling_with_timeout(addr, data, mask, 15000);
507 			if (data != 0) {
508 				debug("Read from reg = %p - value = 0x%x\n",
509 				      hpipe_addr + HPIPE_LANE_STATUS1_REG,
510 				      data);
511 				pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
512 				ret = 0;
513 			}
514 		}
515 	}
516 
517 	debug_exit();
518 	return ret;
519 }
520 
521 static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
522 				void __iomem *comphy_base)
523 {
524 	u32 mask, data, ret = 1;
525 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
526 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
527 	void __iomem *addr;
528 
529 	debug_enter();
530 	debug("stage: RFU configurations - hard reset comphy\n");
531 	/* RFU configurations - hard reset comphy */
532 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
533 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
534 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
535 	data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
536 	mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
537 	data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
538 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
539 	data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
540 	mask |= COMMON_PHY_PHY_MODE_MASK;
541 	data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
542 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
543 
544 	/* release from hard reset */
545 	mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
546 	data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
547 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
548 	data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
549 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
550 
551 	/* Wait 1ms - until band gap and ref clock ready */
552 	mdelay(1);
553 
554 	/* Start comphy Configuration */
555 	debug("stage: Comphy configuration\n");
556 	/* Set PIPE soft reset */
557 	mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
558 	data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
559 	/* Set PHY datapath width mode for V0 */
560 	mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
561 	data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
562 	/* Set Data bus width USB mode for V0 */
563 	mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
564 	data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
565 	/* Set CORE_CLK output frequency for 250Mhz */
566 	mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
567 	data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
568 	reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
569 	/* Set PLL ready delay for 0x2 */
570 	reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
571 		0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
572 		HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
573 	/* Set reference clock to come from group 1 - 25Mhz */
574 	reg_set(hpipe_addr + HPIPE_MISC_REG,
575 		0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
576 		HPIPE_MISC_REFCLK_SEL_MASK);
577 	/* Set reference frequcency select - 0x2 */
578 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
579 	data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
580 	/* Set PHY mode to USB - 0x5 */
581 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
582 	data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
583 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
584 	/* Set the amount of time spent in the LoZ state - set for 0x7 */
585 	reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
586 		0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
587 		HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
588 	/* Set max PHY generation setting - 5Gbps */
589 	reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
590 		0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
591 		HPIPE_INTERFACE_GEN_MAX_MASK);
592 	/* Set select data width 20Bit (SEL_BITS[2:0]) */
593 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
594 		0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
595 		HPIPE_LOOPBACK_SEL_MASK);
596 	/* select de-emphasize 3.5db */
597 	reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
598 		0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
599 		HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
600 	/* override tx margining from the MAC */
601 	reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
602 		0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
603 		HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
604 
605 	/* Start analog paramters from ETP(HW) */
606 	debug("stage: Analog paramters from ETP(HW)\n");
607 	/* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
608 	mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
609 	data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
610 	/* Set Override PHY DFE control pins for 0x1 */
611 	mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
612 	data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
613 	/* Set Spread Spectrum Clock Enable fot 0x1 */
614 	mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
615 	data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
616 	reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
617 	/* End of analog parameters */
618 
619 	debug("stage: Comphy power up\n");
620 	/* Release from PIPE soft reset */
621 	reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
622 		0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
623 		HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
624 
625 	/* wait 15ms - for comphy calibration done */
626 	debug("stage: Check PLL\n");
627 	/* Read lane status */
628 	addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
629 	data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
630 	mask = data;
631 	data = polling_with_timeout(addr, data, mask, 15000);
632 	if (data != 0) {
633 		debug("Read from reg = %p - value = 0x%x\n",
634 		      hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
635 		pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
636 		ret = 0;
637 	}
638 
639 	debug_exit();
640 	return ret;
641 }
642 
643 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
644 				void __iomem *comphy_base, int cp_index,
645 				u32 invert)
646 {
647 	u32 mask, data, i, ret = 1;
648 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
649 	void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
650 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
651 	void __iomem *addr;
652 	void __iomem *sata_base = NULL;
653 	int sata_node = -1; /* Set to -1 in order to read the first sata node */
654 
655 	debug_enter();
656 
657 	/*
658 	 * Assumption - each CP has only one SATA controller
659 	 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1
660 	 * will return the first node always.
661 	 * In order to parse each CPs SATA node, fdt_node_offset_by_compatible
662 	 * must be called again (according to the CP id)
663 	 */
664 	for (i = 0; i < (cp_index + 1); i++)
665 		sata_node = fdt_node_offset_by_compatible(
666 			gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
667 
668 	if (sata_node == 0) {
669 		pr_err("SATA node not found in FDT\n");
670 		return 0;
671 	}
672 
673 	sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
674 		gd->fdt_blob, sata_node, "reg", 0, NULL, true);
675 	if (sata_base == NULL) {
676 		pr_err("SATA address not found in FDT\n");
677 		return 0;
678 	}
679 
680 	debug("SATA address found in FDT %p\n", sata_base);
681 
682 	debug("stage: MAC configuration - power down comphy\n");
683 	/*
684 	 * MAC configuration powe down comphy use indirect address for
685 	 * vendor spesific SATA control register
686 	 */
687 	reg_set(sata_base + SATA3_VENDOR_ADDRESS,
688 		SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
689 		SATA3_VENDOR_ADDR_MASK);
690 	/* SATA 0 power down */
691 	mask = SATA3_CTRL_SATA0_PD_MASK;
692 	data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
693 	/* SATA 1 power down */
694 	mask |= SATA3_CTRL_SATA1_PD_MASK;
695 	data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
696 	/* SATA SSU disable */
697 	mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
698 	data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
699 	/* SATA port 1 disable */
700 	mask |= SATA3_CTRL_SATA_SSU_MASK;
701 	data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
702 	reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
703 
704 	debug("stage: RFU configurations - hard reset comphy\n");
705 	/* RFU configurations - hard reset comphy */
706 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
707 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
708 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
709 	data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
710 	mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
711 	data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
712 	mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
713 	data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
714 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
715 
716 	/* Set select data  width 40Bit - SATA mode only */
717 	reg_set(comphy_addr + COMMON_PHY_CFG6_REG,
718 		0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET,
719 		COMMON_PHY_CFG6_IF_40_SEL_MASK);
720 
721 	/* release from hard reset in SD external */
722 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
723 	data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
724 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
725 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
726 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
727 
728 	/* Wait 1ms - until band gap and ref clock ready */
729 	mdelay(1);
730 
731 	debug("stage: Comphy configuration\n");
732 	/* Start comphy Configuration */
733 	/* Set reference clock to comes from group 1 - choose 25Mhz */
734 	reg_set(hpipe_addr + HPIPE_MISC_REG,
735 		0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
736 		HPIPE_MISC_REFCLK_SEL_MASK);
737 	/* Reference frequency select set 1 (for SATA = 25Mhz) */
738 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
739 	data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
740 	/* PHY mode select (set SATA = 0x0 */
741 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
742 	data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
743 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
744 	/* Set max PHY generation setting - 6Gbps */
745 	reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
746 		0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
747 		HPIPE_INTERFACE_GEN_MAX_MASK);
748 	/* Set select data  width 40Bit (SEL_BITS[2:0]) */
749 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
750 		0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
751 
752 	debug("stage: Analog paramters from ETP(HW)\n");
753 	/* Set analog parameters from ETP(HW) */
754 	/* G1 settings */
755 	mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
756 	data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
757 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
758 	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
759 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
760 	data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
761 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
762 	data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
763 	mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
764 	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
765 	reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
766 
767 	mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
768 	data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
769 	mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
770 	data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
771 	mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
772 	data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
773 	mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK;
774 	data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET;
775 	mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK;
776 	data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET;
777 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
778 
779 	/* G2 settings */
780 	mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
781 	data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
782 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
783 	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
784 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
785 	data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
786 	mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
787 	data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET;
788 	mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK;
789 	data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET;
790 	reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
791 
792 	/* G3 settings */
793 	mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
794 	data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
795 	mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
796 	data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
797 	mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK;
798 	data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET;
799 	mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK;
800 	data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET;
801 	mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK;
802 	data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET;
803 	mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK;
804 	data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET;
805 	mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
806 	data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
807 	reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
808 
809 	/* DTL Control */
810 	mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK;
811 	data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET;
812 	mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK;
813 	data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET;
814 	mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
815 	data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
816 	mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK;
817 	data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET;
818 	mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK;
819 	data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET;
820 	mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK;
821 	data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET;
822 	mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
823 	data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET;
824 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
825 
826 	/* Trigger sampler enable pulse (by toggleing the bit) */
827 	mask = HPIPE_SMAPLER_MASK;
828 	data = 0x1 << HPIPE_SMAPLER_OFFSET;
829 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
830 	mask = HPIPE_SMAPLER_MASK;
831 	data = 0x0 << HPIPE_SMAPLER_OFFSET;
832 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
833 
834 	/* VDD Calibration Control 3 */
835 	mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
836 	data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
837 	reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
838 
839 	/* DFE Resolution Control */
840 	mask = HPIPE_DFE_RES_FORCE_MASK;
841 	data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
842 	reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
843 
844 	/* DFE F3-F5 Coefficient Control */
845 	mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
846 	data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
847 	mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
848 	data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
849 	reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
850 
851 	/* G3 Setting 3 */
852 	mask = HPIPE_G3_FFE_CAP_SEL_MASK;
853 	data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET;
854 	mask |= HPIPE_G3_FFE_RES_SEL_MASK;
855 	data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET;
856 	mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK;
857 	data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET;
858 	mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
859 	data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
860 	mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
861 	data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
862 	reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
863 
864 	/* G3 Setting 4 */
865 	mask = HPIPE_G3_DFE_RES_MASK;
866 	data = 0x2 << HPIPE_G3_DFE_RES_OFFSET;
867 	reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
868 
869 	/* Offset Phase Control */
870 	mask = HPIPE_OS_PH_OFFSET_MASK;
871 	data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET;
872 	mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK;
873 	data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET;
874 	reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
875 	mask = HPIPE_OS_PH_VALID_MASK;
876 	data = 0x1 << HPIPE_OS_PH_VALID_OFFSET;
877 	reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
878 	mask = HPIPE_OS_PH_VALID_MASK;
879 	data = 0x0 << HPIPE_OS_PH_VALID_OFFSET;
880 	reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
881 
882 	/* Set G1 TX amplitude and TX post emphasis value */
883 	mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
884 	data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
885 	mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK;
886 	data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET;
887 	mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
888 	data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
889 	mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK;
890 	data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET;
891 	reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
892 
893 	/* Set G2 TX amplitude and TX post emphasis value */
894 	mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK;
895 	data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET;
896 	mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK;
897 	data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET;
898 	mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK;
899 	data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET;
900 	mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK;
901 	data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET;
902 	reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask);
903 
904 	/* Set G3 TX amplitude and TX post emphasis value */
905 	mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK;
906 	data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET;
907 	mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK;
908 	data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET;
909 	mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK;
910 	data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET;
911 	mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK;
912 	data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET;
913 	mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK;
914 	data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET;
915 	mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK;
916 	data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET;
917 	reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask);
918 
919 	/* SERDES External Configuration 2 register */
920 	mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK;
921 	data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET;
922 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
923 
924 	/* DFE reset sequence */
925 	reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
926 		0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
927 		HPIPE_PWR_CTR_RST_DFE_MASK);
928 	reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
929 		0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
930 		HPIPE_PWR_CTR_RST_DFE_MASK);
931 
932 	/* Set RX / TX swaps */
933 	data = mask = 0;
934 	if (invert & PHY_POLARITY_TXD_INVERT) {
935 		data |= (1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET);
936 		mask |= HPIPE_SYNC_PATTERN_TXD_SWAP_MASK;
937 	}
938 	if (invert & PHY_POLARITY_RXD_INVERT) {
939 		data |= (1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET);
940 		mask |= HPIPE_SYNC_PATTERN_RXD_SWAP_MASK;
941 	}
942 	reg_set(hpipe_addr + HPIPE_SYNC_PATTERN_REG, data, mask);
943 
944 	/* SW reset for interupt logic */
945 	reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
946 		0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
947 		HPIPE_PWR_CTR_SFT_RST_MASK);
948 	reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
949 		0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
950 		HPIPE_PWR_CTR_SFT_RST_MASK);
951 
952 	debug("stage: Comphy power up\n");
953 	/*
954 	 * MAC configuration power up comphy - power up PLL/TX/RX
955 	 * use indirect address for vendor spesific SATA control register
956 	 */
957 	reg_set(sata_base + SATA3_VENDOR_ADDRESS,
958 		SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
959 		SATA3_VENDOR_ADDR_MASK);
960 	/* SATA 0 power up */
961 	mask = SATA3_CTRL_SATA0_PD_MASK;
962 	data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
963 	/* SATA 1 power up */
964 	mask |= SATA3_CTRL_SATA1_PD_MASK;
965 	data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
966 	/* SATA SSU enable */
967 	mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
968 	data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
969 	/* SATA port 1 enable */
970 	mask |= SATA3_CTRL_SATA_SSU_MASK;
971 	data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
972 	reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
973 
974 	/* MBUS request size and interface select register */
975 	reg_set(sata_base + SATA3_VENDOR_ADDRESS,
976 		SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
977 		SATA3_VENDOR_ADDR_MASK);
978 	/* Mbus regret enable */
979 	reg_set(sata_base + SATA3_VENDOR_DATA,
980 		0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK);
981 
982 	debug("stage: Check PLL\n");
983 
984 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
985 	data = SD_EXTERNAL_STATUS0_PLL_TX_MASK &
986 		SD_EXTERNAL_STATUS0_PLL_RX_MASK;
987 	mask = data;
988 	data = polling_with_timeout(addr, data, mask, 15000);
989 	if (data != 0) {
990 		debug("Read from reg = %p - value = 0x%x\n",
991 		      hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
992 		pr_err("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n",
993 		      (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK),
994 		      (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK));
995 		ret = 0;
996 	}
997 
998 	debug_exit();
999 	return ret;
1000 }
1001 
1002 static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed,
1003 				 void __iomem *hpipe_base,
1004 				 void __iomem *comphy_base)
1005 {
1006 	u32 mask, data, ret = 1;
1007 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
1008 	void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
1009 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
1010 	void __iomem *addr;
1011 
1012 	debug_enter();
1013 	debug("stage: RFU configurations - hard reset comphy\n");
1014 	/* RFU configurations - hard reset comphy */
1015 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1016 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1017 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1018 	data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1019 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1020 
1021 	/* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
1022 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1023 	data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1024 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
1025 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
1026 	if (sgmii_speed == PHY_SPEED_1_25G) {
1027 		data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1028 		data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1029 	} else {
1030 		/* 3.125G */
1031 		data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1032 		data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1033 	}
1034 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1035 	data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1036 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1037 	data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1038 	mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
1039 	data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
1040 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1041 
1042 	/* release from hard reset */
1043 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1044 	data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1045 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1046 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1047 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1048 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1049 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1050 
1051 	/* release from hard reset */
1052 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1053 	data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1054 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1055 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1056 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1057 
1058 
1059 	/* Wait 1ms - until band gap and ref clock ready */
1060 	mdelay(1);
1061 
1062 	/* Start comphy Configuration */
1063 	debug("stage: Comphy configuration\n");
1064 	/* set reference clock */
1065 	mask = HPIPE_MISC_REFCLK_SEL_MASK;
1066 	data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
1067 	reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
1068 	/* Power and PLL Control */
1069 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1070 	data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1071 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1072 	data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1073 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1074 	/* Loopback register */
1075 	mask = HPIPE_LOOPBACK_SEL_MASK;
1076 	data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
1077 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
1078 	/* rx control 1 */
1079 	mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
1080 	data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
1081 	mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
1082 	data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
1083 	reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1084 	/* DTL Control */
1085 	mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
1086 	data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
1087 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
1088 
1089 	/* Set analog paramters from ETP(HW) - for now use the default datas */
1090 	debug("stage: Analog paramters from ETP(HW)\n");
1091 
1092 	reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
1093 		0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
1094 		HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
1095 
1096 	debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1097 	/* SERDES External Configuration */
1098 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1099 	data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1100 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1101 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1102 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1103 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1104 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1105 
1106 	/* check PLL rx & tx ready */
1107 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1108 	data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1109 		SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1110 	mask = data;
1111 	data = polling_with_timeout(addr, data, mask, 15000);
1112 	if (data != 0) {
1113 		debug("Read from reg = %p - value = 0x%x\n",
1114 		      sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1115 		pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
1116 		      (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1117 		      (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1118 		ret = 0;
1119 	}
1120 
1121 	/* RX init */
1122 	mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1123 	data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1124 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1125 
1126 	/* check that RX init done */
1127 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1128 	data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1129 	mask = data;
1130 	data = polling_with_timeout(addr, data, mask, 100);
1131 	if (data != 0) {
1132 		debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1133 		pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
1134 		ret = 0;
1135 	}
1136 
1137 	debug("stage: RF Reset\n");
1138 	/* RF Reset */
1139 	mask =  SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1140 	data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1141 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1142 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1143 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1144 
1145 	debug_exit();
1146 	return ret;
1147 }
1148 
1149 static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base,
1150 			       void __iomem *comphy_base, u32 speed)
1151 {
1152 	u32 mask, data, ret = 1;
1153 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
1154 	void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
1155 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
1156 	void __iomem *addr;
1157 
1158 	debug_enter();
1159 	debug("stage: RFU configurations - hard reset comphy\n");
1160 	/* RFU configurations - hard reset comphy */
1161 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1162 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1163 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1164 	data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1165 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1166 
1167 	/* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
1168 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1169 	data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1170 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
1171 	data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1172 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
1173 	data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1174 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1175 	data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1176 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1177 	data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1178 	mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
1179 	data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
1180 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1181 
1182 	/* release from hard reset */
1183 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1184 	data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1185 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1186 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1187 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1188 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1189 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1190 
1191 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1192 	data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1193 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1194 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1195 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1196 
1197 
1198 	/* Wait 1ms - until band gap and ref clock ready */
1199 	mdelay(1);
1200 
1201 	/* Start comphy Configuration */
1202 	debug("stage: Comphy configuration\n");
1203 	/* set reference clock */
1204 	mask = HPIPE_MISC_ICP_FORCE_MASK;
1205 	data = (speed == PHY_SPEED_5_15625G) ?
1206 		(0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) :
1207 		(0x1 << HPIPE_MISC_ICP_FORCE_OFFSET);
1208 	mask |= HPIPE_MISC_REFCLK_SEL_MASK;
1209 	data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
1210 	reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
1211 	/* Power and PLL Control */
1212 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1213 	data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1214 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1215 	data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1216 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1217 	/* Loopback register */
1218 	mask = HPIPE_LOOPBACK_SEL_MASK;
1219 	data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
1220 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
1221 	/* rx control 1 */
1222 	mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
1223 	data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
1224 	mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
1225 	data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
1226 	reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1227 	/* DTL Control */
1228 	mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
1229 	data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
1230 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
1231 
1232 	/* Transmitter/Receiver Speed Divider Force */
1233 	if (speed == PHY_SPEED_5_15625G) {
1234 		mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK;
1235 		data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET;
1236 		mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK;
1237 		data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET;
1238 		mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK;
1239 		data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET;
1240 		mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK;
1241 		data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET;
1242 	} else {
1243 		mask = HPIPE_TXDIGCK_DIV_FORCE_MASK;
1244 		data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET;
1245 	}
1246 	reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);
1247 
1248 	/* Set analog paramters from ETP(HW) */
1249 	debug("stage: Analog paramters from ETP(HW)\n");
1250 	/* SERDES External Configuration 2 */
1251 	mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK;
1252 	data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET;
1253 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
1254 	/* 0x7-DFE Resolution control */
1255 	mask = HPIPE_DFE_RES_FORCE_MASK;
1256 	data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
1257 	reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1258 	/* 0xd-G1_Setting_0 */
1259 	if (speed == PHY_SPEED_5_15625G) {
1260 		mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
1261 		data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
1262 	} else {
1263 		mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
1264 		data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
1265 		mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
1266 		data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
1267 	}
1268 	reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
1269 	/* Genration 1 setting 2 (G1_Setting_2) */
1270 	mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK;
1271 	data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET;
1272 	mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK;
1273 	data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET;
1274 	reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
1275 	/* Transmitter Slew Rate Control register (tx_reg1) */
1276 	mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK;
1277 	data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET;
1278 	mask |= HPIPE_TX_REG1_SLC_EN_MASK;
1279 	data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET;
1280 	reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask);
1281 	/* Impedance Calibration Control register (cal_reg1) */
1282 	mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK;
1283 	data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
1284 	mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK;
1285 	data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET;
1286 	reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask);
1287 	/* Generation 1 Setting 5 (g1_setting_5) */
1288 	mask = HPIPE_G1_SETTING_5_G1_ICP_MASK;
1289 	data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
1290 	reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
1291 	/* 0xE-G1_Setting_1 */
1292 	mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
1293 	data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1294 	if (speed == PHY_SPEED_5_15625G) {
1295 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1296 		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1297 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
1298 		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
1299 	} else {
1300 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1301 		data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1302 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
1303 		data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
1304 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
1305 		data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
1306 		mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
1307 		data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
1308 		mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
1309 		data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
1310 	}
1311 	reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1312 
1313 	/* 0xA-DFE_Reg3 */
1314 	mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1315 	data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1316 	mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1317 	data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1318 	reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1319 
1320 	/* 0x111-G1_Setting_4 */
1321 	mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1322 	data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1323 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1324 	/* Genration 1 setting 3 (G1_Setting_3) */
1325 	mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK;
1326 	data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET;
1327 	if (speed == PHY_SPEED_5_15625G) {
1328 		/* Force FFE (Feed Forward Equalization) to 5G */
1329 		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
1330 		data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
1331 		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
1332 		data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
1333 		mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
1334 		data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
1335 	}
1336 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1337 
1338 	/* Connfigure RX training timer */
1339 	mask = HPIPE_RX_TRAIN_TIMER_MASK;
1340 	data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET;
1341 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1342 
1343 	/* Enable TX train peak to peak hold */
1344 	mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
1345 	data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
1346 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1347 
1348 	/* Configure TX preset index */
1349 	mask = HPIPE_TX_PRESET_INDEX_MASK;
1350 	data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET;
1351 	reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask);
1352 
1353 	/* Disable pattern lock lost timeout */
1354 	mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
1355 	data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
1356 	reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1357 
1358 	/* Configure TX training pattern and TX training 16bit auto */
1359 	mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK;
1360 	data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET;
1361 	mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK;
1362 	data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET;
1363 	reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1364 
1365 	/* Configure Training patten number */
1366 	mask = HPIPE_TRAIN_PAT_NUM_MASK;
1367 	data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET;
1368 	reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask);
1369 
1370 	/* Configure differencial manchester encoter to ethernet mode */
1371 	mask = HPIPE_DME_ETHERNET_MODE_MASK;
1372 	data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET;
1373 	reg_set(hpipe_addr + HPIPE_DME_REG, data, mask);
1374 
1375 	/* Configure VDD Continuous Calibration */
1376 	mask = HPIPE_CAL_VDD_CONT_MODE_MASK;
1377 	data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET;
1378 	reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask);
1379 
1380 	/* Trigger sampler enable pulse (by toggleing the bit) */
1381 	mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK;
1382 	data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET;
1383 	mask |= HPIPE_SMAPLER_MASK;
1384 	data |= 0x1 << HPIPE_SMAPLER_OFFSET;
1385 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1386 	mask = HPIPE_SMAPLER_MASK;
1387 	data = 0x0 << HPIPE_SMAPLER_OFFSET;
1388 	reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1389 
1390 	/* Set External RX Regulator Control */
1391 	mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
1392 	data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
1393 	reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1394 
1395 	debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1396 	/* SERDES External Configuration */
1397 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1398 	data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1399 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1400 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1401 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1402 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1403 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1404 
1405 
1406 	/* check PLL rx & tx ready */
1407 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1408 	data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1409 		SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1410 	mask = data;
1411 	data = polling_with_timeout(addr, data, mask, 15000);
1412 	if (data != 0) {
1413 		debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1414 		pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
1415 		      (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1416 		      (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1417 		ret = 0;
1418 	}
1419 
1420 	/* RX init */
1421 	mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1422 	data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1423 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1424 
1425 
1426 	/* check that RX init done */
1427 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1428 	data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1429 	mask = data;
1430 	data = polling_with_timeout(addr, data, mask, 100);
1431 	if (data != 0) {
1432 		debug("Read from reg = %p - value = 0x%x\n",
1433 		      sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1434 		pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
1435 		ret = 0;
1436 	}
1437 
1438 	debug("stage: RF Reset\n");
1439 	/* RF Reset */
1440 	mask =  SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1441 	data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1442 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1443 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1444 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1445 
1446 	debug_exit();
1447 	return ret;
1448 }
1449 
1450 static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base,
1451 				  void __iomem *comphy_base)
1452 {
1453 	u32 mask, data, ret = 1;
1454 	void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
1455 	void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
1456 	void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
1457 	void __iomem *addr;
1458 
1459 	debug_enter();
1460 	debug("stage: RFU configurations - hard reset comphy\n");
1461 	/* RFU configurations - hard reset comphy */
1462 	mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1463 	data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1464 	mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1465 	data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1466 	reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1467 
1468 	if (lane == 2) {
1469 		reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1470 			0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
1471 			COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
1472 	}
1473 	if (lane == 4) {
1474 		reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1475 			0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
1476 			COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
1477 	}
1478 
1479 	/* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
1480 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1481 	data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1482 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
1483 	data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1484 	mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
1485 	data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1486 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1487 	data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1488 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1489 	data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1490 	mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
1491 	data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
1492 	mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
1493 	data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
1494 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1495 
1496 	/* release from hard reset */
1497 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1498 	data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1499 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1500 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1501 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1502 	data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1503 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1504 
1505 	mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1506 	data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1507 	mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1508 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1509 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1510 
1511 	/* Wait 1ms - until band gap and ref clock ready */
1512 	mdelay(1);
1513 
1514 	/* Start comphy Configuration */
1515 	debug("stage: Comphy configuration\n");
1516 	/* set reference clock */
1517 	reg_set(hpipe_addr + HPIPE_MISC_REG,
1518 		0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
1519 		HPIPE_MISC_REFCLK_SEL_MASK);
1520 	/* Power and PLL Control */
1521 	mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1522 	data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1523 	mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1524 	data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1525 	reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1526 	/* Loopback register */
1527 	reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
1528 		0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
1529 	/* rx control 1 */
1530 	mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
1531 	data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
1532 	mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
1533 	data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
1534 	reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1535 	/* DTL Control */
1536 	reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
1537 		0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
1538 		HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
1539 
1540 	/* Set analog paramters from ETP(HW) */
1541 	debug("stage: Analog paramters from ETP(HW)\n");
1542 	/* SERDES External Configuration 2 */
1543 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
1544 		0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
1545 		SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
1546 	/* 0x7-DFE Resolution control */
1547 	reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
1548 		HPIPE_DFE_RES_FORCE_MASK);
1549 	/* 0xd-G1_Setting_0 */
1550 	reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
1551 		0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
1552 		HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
1553 	/* 0xE-G1_Setting_1 */
1554 	mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1555 	data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1556 	mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
1557 	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
1558 	mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
1559 	data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1560 	reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1561 	/* 0xA-DFE_Reg3 */
1562 	mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1563 	data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1564 	mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1565 	data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1566 	reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1567 
1568 	/* 0x111-G1_Setting_4 */
1569 	mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1570 	data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1571 	reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1572 
1573 	debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1574 	/* SERDES External Configuration */
1575 	mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1576 	data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1577 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1578 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1579 	mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1580 	data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1581 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1582 
1583 
1584 	/* check PLL rx & tx ready */
1585 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1586 	data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1587 		SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1588 	mask = data;
1589 	data = polling_with_timeout(addr, data, mask, 15000);
1590 	if (data != 0) {
1591 		debug("Read from reg = %p - value = 0x%x\n",
1592 		      sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1593 		pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
1594 		      (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1595 		      (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1596 		ret = 0;
1597 	}
1598 
1599 	/* RX init */
1600 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
1601 		0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
1602 		SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
1603 
1604 	/* check that RX init done */
1605 	addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1606 	data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1607 	mask = data;
1608 	data = polling_with_timeout(addr, data, mask, 100);
1609 	if (data != 0) {
1610 		debug("Read from reg = %p - value = 0x%x\n",
1611 		      sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1612 		pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
1613 		ret = 0;
1614 	}
1615 
1616 	debug("stage: RF Reset\n");
1617 	/* RF Reset */
1618 	mask =  SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1619 	data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1620 	mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1621 	data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1622 	reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1623 
1624 	debug_exit();
1625 	return ret;
1626 }
1627 
1628 static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
1629 				   void __iomem *usb_cfg_addr,
1630 				   void __iomem *utmi_cfg_addr,
1631 				   u32 utmi_phy_port)
1632 {
1633 	u32 mask, data;
1634 
1635 	debug_enter();
1636 	debug("stage:  UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n",
1637 	      utmi_index);
1638 	/* Power down UTMI PHY */
1639 	reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET,
1640 		UTMI_PHY_CFG_PU_MASK);
1641 
1642 	/*
1643 	 * If UTMI connected to USB Device, configure mux prior to PHY init
1644 	 * (Device can be connected to UTMI0 or to UTMI1)
1645 	 */
1646 	if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) {
1647 		debug("stage:  UTMI %d - Enable Device mode and configure UTMI mux\n",
1648 		      utmi_index);
1649 		/* USB3 Device UTMI enable */
1650 		mask = UTMI_USB_CFG_DEVICE_EN_MASK;
1651 		data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
1652 		/* USB3 Device UTMI MUX */
1653 		mask |= UTMI_USB_CFG_DEVICE_MUX_MASK;
1654 		data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET;
1655 		reg_set(usb_cfg_addr,  data, mask);
1656 	}
1657 
1658 	/* Set Test suspendm mode */
1659 	mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK;
1660 	data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET;
1661 	/* Enable Test UTMI select */
1662 	mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK;
1663 	data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET;
1664 	reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask);
1665 
1666 	/* Wait for UTMI power down */
1667 	mdelay(1);
1668 
1669 	debug_exit();
1670 	return;
1671 }
1672 
1673 static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
1674 				   void __iomem *usb_cfg_addr,
1675 				   void __iomem *utmi_cfg_addr,
1676 				   u32 utmi_phy_port)
1677 {
1678 	u32 mask, data;
1679 
1680 	debug_exit();
1681 	debug("stage: Configure UTMI PHY %d registers\n", utmi_index);
1682 	/* Reference Clock Divider Select */
1683 	mask = UTMI_PLL_CTRL_REFDIV_MASK;
1684 	data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET;
1685 	/* Feedback Clock Divider Select - 90 for 25Mhz*/
1686 	mask |= UTMI_PLL_CTRL_FBDIV_MASK;
1687 	data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET;
1688 	/* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
1689 	mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
1690 	data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
1691 	reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask);
1692 
1693 	/* Impedance Calibration Threshold Setting */
1694 	reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
1695 		0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
1696 		UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
1697 
1698 	/* Set LS TX driver strength coarse control */
1699 	mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
1700 	data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
1701 	/* Set LS TX driver fine adjustment */
1702 	mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
1703 	data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
1704 	reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
1705 
1706 	/* Enable SQ */
1707 	mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
1708 	data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
1709 	/* Enable analog squelch detect */
1710 	mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
1711 	data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
1712 	reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
1713 
1714 	/* Set External squelch calibration number */
1715 	mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK;
1716 	data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET;
1717 	/* Enable the External squelch calibration */
1718 	mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK;
1719 	data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET;
1720 	reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask);
1721 
1722 	/* Set Control VDAT Reference Voltage - 0.325V */
1723 	mask = UTMI_CHGDTC_CTRL_VDAT_MASK;
1724 	data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET;
1725 	/* Set Control VSRC Reference Voltage - 0.6V */
1726 	mask |= UTMI_CHGDTC_CTRL_VSRC_MASK;
1727 	data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET;
1728 	reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask);
1729 
1730 	debug_exit();
1731 	return;
1732 }
1733 
1734 static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
1735 				void __iomem *usb_cfg_addr,
1736 				void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
1737 {
1738 	u32 data, mask, ret = 1;
1739 	void __iomem *addr;
1740 
1741 	debug_enter();
1742 	debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n",
1743 	      utmi_index);
1744 	/* Power UP UTMI PHY */
1745 	reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET,
1746 		UTMI_PHY_CFG_PU_MASK);
1747 	/* Disable Test UTMI select */
1748 	reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG,
1749 		0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET,
1750 		UTMI_CTRL_STATUS0_TEST_SEL_MASK);
1751 
1752 	debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
1753 	addr = utmi_base_addr + UTMI_CALIB_CTRL_REG;
1754 	data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
1755 	mask = data;
1756 	data = polling_with_timeout(addr, data, mask, 100);
1757 	if (data != 0) {
1758 		pr_err("Impedance calibration is not done\n");
1759 		debug("Read from reg = %p - value = 0x%x\n", addr, data);
1760 		ret = 0;
1761 	}
1762 
1763 	data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK;
1764 	mask = data;
1765 	data = polling_with_timeout(addr, data, mask, 100);
1766 	if (data != 0) {
1767 		pr_err("PLL calibration is not done\n");
1768 		debug("Read from reg = %p - value = 0x%x\n", addr, data);
1769 		ret = 0;
1770 	}
1771 
1772 	addr = utmi_base_addr + UTMI_PLL_CTRL_REG;
1773 	data = UTMI_PLL_CTRL_PLL_RDY_MASK;
1774 	mask = data;
1775 	data = polling_with_timeout(addr, data, mask, 100);
1776 	if (data != 0) {
1777 		pr_err("PLL is not ready\n");
1778 		debug("Read from reg = %p - value = 0x%x\n", addr, data);
1779 		ret = 0;
1780 	}
1781 
1782 	if (ret)
1783 		debug("Passed\n");
1784 	else
1785 		debug("\n");
1786 
1787 	debug_exit();
1788 	return ret;
1789 }
1790 
1791 /*
1792  * comphy_utmi_phy_init initialize the UTMI PHY
1793  * the init split in 3 parts:
1794  * 1. Power down transceiver and PLL
1795  * 2. UTMI PHY configure
1796  * 3. Powe up transceiver and PLL
1797  * Note: - Power down/up should be once for both UTMI PHYs
1798  *       - comphy_dedicated_phys_init call this function if at least there is
1799  *         one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
1800  *         legal
1801  */
1802 static void comphy_utmi_phy_init(u32 utmi_phy_count,
1803 				 struct utmi_phy_data *cp110_utmi_data)
1804 {
1805 	u32 i;
1806 
1807 	debug_enter();
1808 	/* UTMI Power down */
1809 	for (i = 0; i < utmi_phy_count; i++) {
1810 		comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr,
1811 				       cp110_utmi_data[i].usb_cfg_addr,
1812 				       cp110_utmi_data[i].utmi_cfg_addr,
1813 				       cp110_utmi_data[i].utmi_phy_port);
1814 	}
1815 	/* PLL Power down */
1816 	debug("stage: UTMI PHY power down PLL\n");
1817 	for (i = 0; i < utmi_phy_count; i++) {
1818 		reg_set(cp110_utmi_data[i].usb_cfg_addr,
1819 			0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
1820 	}
1821 	/* UTMI configure */
1822 	for (i = 0; i < utmi_phy_count; i++) {
1823 		comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr,
1824 				       cp110_utmi_data[i].usb_cfg_addr,
1825 				       cp110_utmi_data[i].utmi_cfg_addr,
1826 				       cp110_utmi_data[i].utmi_phy_port);
1827 	}
1828 	/* UTMI Power up */
1829 	for (i = 0; i < utmi_phy_count; i++) {
1830 		if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr,
1831 					  cp110_utmi_data[i].usb_cfg_addr,
1832 					  cp110_utmi_data[i].utmi_cfg_addr,
1833 					  cp110_utmi_data[i].utmi_phy_port)) {
1834 			pr_err("Failed to initialize UTMI PHY %d\n", i);
1835 			continue;
1836 		}
1837 		printf("UTMI PHY %d initialized to ", i);
1838 		if (cp110_utmi_data[i].utmi_phy_port ==
1839 		    UTMI_PHY_TO_USB3_DEVICE0)
1840 			printf("USB Device\n");
1841 		else
1842 			printf("USB Host%d\n",
1843 			       cp110_utmi_data[i].utmi_phy_port);
1844 	}
1845 	/* PLL Power up */
1846 	debug("stage: UTMI PHY power up PLL\n");
1847 	for (i = 0; i < utmi_phy_count; i++) {
1848 		reg_set(cp110_utmi_data[i].usb_cfg_addr,
1849 			0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
1850 	}
1851 
1852 	debug_exit();
1853 	return;
1854 }
1855 
1856 /*
1857  * comphy_dedicated_phys_init initialize the dedicated PHYs
1858  * - not muxed SerDes lanes e.g. UTMI PHY
1859  */
1860 void comphy_dedicated_phys_init(void)
1861 {
1862 	struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
1863 	int node;
1864 	int i;
1865 
1866 	debug_enter();
1867 	debug("Initialize USB UTMI PHYs\n");
1868 
1869 	/* Find the UTMI phy node in device tree and go over them */
1870 	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
1871 					     "marvell,mvebu-utmi-2.6.0");
1872 
1873 	i = 0;
1874 	while (node > 0) {
1875 		/* get base address of UTMI phy */
1876 		cp110_utmi_data[i].utmi_base_addr =
1877 			(void __iomem *)fdtdec_get_addr_size_auto_noparent(
1878 				gd->fdt_blob, node, "reg", 0, NULL, true);
1879 		if (cp110_utmi_data[i].utmi_base_addr == NULL) {
1880 			pr_err("UTMI PHY base address is invalid\n");
1881 			i++;
1882 			continue;
1883 		}
1884 
1885 		/* get usb config address */
1886 		cp110_utmi_data[i].usb_cfg_addr =
1887 			(void __iomem *)fdtdec_get_addr_size_auto_noparent(
1888 				gd->fdt_blob, node, "reg", 1, NULL, true);
1889 		if (cp110_utmi_data[i].usb_cfg_addr == NULL) {
1890 			pr_err("UTMI PHY base address is invalid\n");
1891 			i++;
1892 			continue;
1893 		}
1894 
1895 		/* get UTMI config address */
1896 		cp110_utmi_data[i].utmi_cfg_addr =
1897 			(void __iomem *)fdtdec_get_addr_size_auto_noparent(
1898 				gd->fdt_blob, node, "reg", 2, NULL, true);
1899 		if (cp110_utmi_data[i].utmi_cfg_addr == NULL) {
1900 			pr_err("UTMI PHY base address is invalid\n");
1901 			i++;
1902 			continue;
1903 		}
1904 
1905 		/*
1906 		 * get the port number (to check if the utmi connected to
1907 		 * host/device)
1908 		 */
1909 		cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int(
1910 			gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
1911 		if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) {
1912 			pr_err("UTMI PHY port type is invalid\n");
1913 			i++;
1914 			continue;
1915 		}
1916 
1917 		node = fdt_node_offset_by_compatible(
1918 			gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0");
1919 		i++;
1920 	}
1921 
1922 	if (i > 0)
1923 		comphy_utmi_phy_init(i, cp110_utmi_data);
1924 
1925 	debug_exit();
1926 }
1927 
1928 static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
1929 				  struct comphy_map *serdes_map)
1930 {
1931 	void __iomem *comphy_base_addr;
1932 	struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS];
1933 	struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS];
1934 	u32 lane, comphy_max_count;
1935 
1936 	comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
1937 	comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
1938 
1939 	/*
1940 	 * Copy the SerDes map configuration for PIPE map and PHY map
1941 	 * the comphy_mux_init modify the type of the lane if the type
1942 	 * is not valid because we have 2 selectores run the
1943 	 * comphy_mux_init twice and after that update the original
1944 	 * serdes_map
1945 	 */
1946 	for (lane = 0; lane < comphy_max_count; lane++) {
1947 		comphy_map_pipe_data[lane].type = serdes_map[lane].type;
1948 		comphy_map_pipe_data[lane].speed = serdes_map[lane].speed;
1949 		comphy_map_phy_data[lane].type = serdes_map[lane].type;
1950 		comphy_map_phy_data[lane].speed = serdes_map[lane].speed;
1951 	}
1952 	ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data;
1953 	comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data,
1954 			comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET);
1955 
1956 	ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data;
1957 	comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data,
1958 			comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
1959 	/* Fix the type after check the PHY and PIPE configuration */
1960 	for (lane = 0; lane < comphy_max_count; lane++) {
1961 		if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
1962 		    (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
1963 			serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
1964 	}
1965 }
1966 
1967 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
1968 		      struct comphy_map *serdes_map)
1969 {
1970 	struct comphy_map *ptr_comphy_map;
1971 	void __iomem *comphy_base_addr, *hpipe_base_addr;
1972 	u32 comphy_max_count, lane, ret = 0;
1973 	u32 pcie_width = 0;
1974 
1975 	debug_enter();
1976 
1977 	comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
1978 	comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
1979 	hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
1980 
1981 	/* Config Comphy mux configuration */
1982 	comphy_mux_cp110_init(ptr_chip_cfg, serdes_map);
1983 
1984 	/* Check if the first 4 lanes configured as By-4 */
1985 	for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
1986 	     lane++, ptr_comphy_map++) {
1987 		if (ptr_comphy_map->type != PHY_TYPE_PEX0)
1988 			break;
1989 		pcie_width++;
1990 	}
1991 
1992 	for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count;
1993 	     lane++, ptr_comphy_map++) {
1994 		debug("Initialize serdes number %d\n", lane);
1995 		debug("Serdes type = 0x%x\n", ptr_comphy_map->type);
1996 		if (lane == 4) {
1997 			/*
1998 			 * PCIe lanes above the first 4 lanes, can be only
1999 			 * by1
2000 			 */
2001 			pcie_width = 1;
2002 		}
2003 		switch (ptr_comphy_map->type) {
2004 		case PHY_TYPE_UNCONNECTED:
2005 		case PHY_TYPE_IGNORE:
2006 			continue;
2007 			break;
2008 		case PHY_TYPE_PEX0:
2009 		case PHY_TYPE_PEX1:
2010 		case PHY_TYPE_PEX2:
2011 		case PHY_TYPE_PEX3:
2012 			ret = comphy_pcie_power_up(
2013 				lane, pcie_width, ptr_comphy_map->clk_src,
2014 				serdes_map->end_point,
2015 				hpipe_base_addr, comphy_base_addr);
2016 			break;
2017 		case PHY_TYPE_SATA0:
2018 		case PHY_TYPE_SATA1:
2019 		case PHY_TYPE_SATA2:
2020 		case PHY_TYPE_SATA3:
2021 			ret = comphy_sata_power_up(
2022 				lane, hpipe_base_addr, comphy_base_addr,
2023 				ptr_chip_cfg->cp_index,
2024 				serdes_map[lane].invert);
2025 			break;
2026 		case PHY_TYPE_USB3_HOST0:
2027 		case PHY_TYPE_USB3_HOST1:
2028 		case PHY_TYPE_USB3_DEVICE:
2029 			ret = comphy_usb3_power_up(lane, hpipe_base_addr,
2030 						   comphy_base_addr);
2031 			break;
2032 		case PHY_TYPE_SGMII0:
2033 		case PHY_TYPE_SGMII1:
2034 		case PHY_TYPE_SGMII2:
2035 		case PHY_TYPE_SGMII3:
2036 			if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
2037 				debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
2038 				      lane);
2039 				ptr_comphy_map->speed = PHY_SPEED_1_25G;
2040 			}
2041 			ret = comphy_sgmii_power_up(
2042 				lane, ptr_comphy_map->speed, hpipe_base_addr,
2043 				comphy_base_addr);
2044 			break;
2045 		case PHY_TYPE_SFI:
2046 			ret = comphy_sfi_power_up(lane, hpipe_base_addr,
2047 						  comphy_base_addr,
2048 						  ptr_comphy_map->speed);
2049 			break;
2050 		case PHY_TYPE_RXAUI0:
2051 		case PHY_TYPE_RXAUI1:
2052 			ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
2053 						     comphy_base_addr);
2054 			break;
2055 		default:
2056 			debug("Unknown SerDes type, skip initialize SerDes %d\n",
2057 			      lane);
2058 			break;
2059 		}
2060 		if (ret == 0) {
2061 			/*
2062 			 * If interface wans't initialized, set the lane to
2063 			 * PHY_TYPE_UNCONNECTED state.
2064 			 */
2065 			ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
2066 			pr_err("PLL is not locked - Failed to initialize lane %d\n",
2067 			      lane);
2068 		}
2069 	}
2070 
2071 	debug_exit();
2072 	return 0;
2073 }
2074