1 /* 2 * Xilinx AXI Bridge for PCI Express Driver 3 * 4 * Copyright (C) 2016 Imagination Technologies 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <pci.h> 12 13 #include <asm/io.h> 14 15 /** 16 * struct xilinx_pcie - Xilinx PCIe controller state 17 * @cfg_base: The base address of memory mapped configuration space 18 */ 19 struct xilinx_pcie { 20 void *cfg_base; 21 }; 22 23 /* Register definitions */ 24 #define XILINX_PCIE_REG_PSCR 0x144 25 #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) 26 27 /** 28 * pcie_xilinx_link_up() - Check whether the PCIe link is up 29 * @pcie: Pointer to the PCI controller state 30 * 31 * Checks whether the PCIe link for the given device is up or down. 32 * 33 * Return: true if the link is up, else false 34 */ 35 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie) 36 { 37 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR); 38 39 return pscr & XILINX_PCIE_REG_PSCR_LNKUP; 40 } 41 42 /** 43 * pcie_xilinx_config_address() - Calculate the address of a config access 44 * @pcie: Pointer to the PCI controller state 45 * @bdf: Identifies the PCIe device to access 46 * @offset: The offset into the device's configuration space 47 * @paddress: Pointer to the pointer to write the calculates address to 48 * 49 * Calculates the address that should be accessed to perform a PCIe 50 * configuration space access for a given device identified by the PCIe 51 * controller device @pcie and the bus, device & function numbers in @bdf. If 52 * access to the device is not valid then the function will return an error 53 * code. Otherwise the address to access will be written to the pointer pointed 54 * to by @paddress. 55 * 56 * Return: 0 on success, else -ENODEV 57 */ 58 static int pcie_xilinx_config_address(struct xilinx_pcie *pcie, pci_dev_t bdf, 59 uint offset, void **paddress) 60 { 61 unsigned int bus = PCI_BUS(bdf); 62 unsigned int dev = PCI_DEV(bdf); 63 unsigned int func = PCI_FUNC(bdf); 64 void *addr; 65 66 if ((bus > 0) && !pcie_xilinx_link_up(pcie)) 67 return -ENODEV; 68 69 /* 70 * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are 71 * limited to a single device each. 72 */ 73 if ((bus < 2) && (dev > 0)) 74 return -ENODEV; 75 76 addr = pcie->cfg_base; 77 addr += bus << 20; 78 addr += dev << 15; 79 addr += func << 12; 80 addr += offset; 81 *paddress = addr; 82 83 return 0; 84 } 85 86 /** 87 * pcie_xilinx_read_config() - Read from configuration space 88 * @bus: Pointer to the PCI bus 89 * @bdf: Identifies the PCIe device to access 90 * @offset: The offset into the device's configuration space 91 * @valuep: A pointer at which to store the read value 92 * @size: Indicates the size of access to perform 93 * 94 * Read a value of size @size from offset @offset within the configuration 95 * space of the device identified by the bus, device & function numbers in @bdf 96 * on the PCI bus @bus. 97 * 98 * Return: 0 on success, else -ENODEV or -EINVAL 99 */ 100 static int pcie_xilinx_read_config(struct udevice *bus, pci_dev_t bdf, 101 uint offset, ulong *valuep, 102 enum pci_size_t size) 103 { 104 struct xilinx_pcie *pcie = dev_get_priv(bus); 105 void *address; 106 int err; 107 108 err = pcie_xilinx_config_address(pcie, bdf, offset, &address); 109 if (err < 0) { 110 *valuep = pci_get_ff(size); 111 return 0; 112 } 113 114 switch (size) { 115 case PCI_SIZE_8: 116 *valuep = __raw_readb(address); 117 return 0; 118 case PCI_SIZE_16: 119 *valuep = __raw_readw(address); 120 return 0; 121 case PCI_SIZE_32: 122 *valuep = __raw_readl(address); 123 return 0; 124 default: 125 return -EINVAL; 126 } 127 } 128 129 /** 130 * pcie_xilinx_write_config() - Write to configuration space 131 * @bus: Pointer to the PCI bus 132 * @bdf: Identifies the PCIe device to access 133 * @offset: The offset into the device's configuration space 134 * @value: The value to write 135 * @size: Indicates the size of access to perform 136 * 137 * Write the value @value of size @size from offset @offset within the 138 * configuration space of the device identified by the bus, device & function 139 * numbers in @bdf on the PCI bus @bus. 140 * 141 * Return: 0 on success, else -ENODEV or -EINVAL 142 */ 143 static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf, 144 uint offset, ulong value, 145 enum pci_size_t size) 146 { 147 struct xilinx_pcie *pcie = dev_get_priv(bus); 148 void *address; 149 int err; 150 151 err = pcie_xilinx_config_address(pcie, bdf, offset, &address); 152 if (err < 0) 153 return 0; 154 155 switch (size) { 156 case PCI_SIZE_8: 157 __raw_writeb(value, address); 158 return 0; 159 case PCI_SIZE_16: 160 __raw_writew(value, address); 161 return 0; 162 case PCI_SIZE_32: 163 __raw_writel(value, address); 164 return 0; 165 default: 166 return -EINVAL; 167 } 168 } 169 170 /** 171 * pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state 172 * @dev: A pointer to the device being operated on 173 * 174 * Translate relevant data from the device tree pertaining to device @dev into 175 * state that the driver will later make use of. This state is stored in the 176 * device's private data structure. 177 * 178 * Return: 0 on success, else -EINVAL 179 */ 180 static int pcie_xilinx_ofdata_to_platdata(struct udevice *dev) 181 { 182 struct xilinx_pcie *pcie = dev_get_priv(dev); 183 struct fdt_resource reg_res; 184 DECLARE_GLOBAL_DATA_PTR; 185 int err; 186 187 err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", 188 0, ®_res); 189 if (err < 0) { 190 error("\"reg\" resource not found\n"); 191 return err; 192 } 193 194 pcie->cfg_base = map_physmem(reg_res.start, 195 fdt_resource_size(®_res), 196 MAP_NOCACHE); 197 198 return 0; 199 } 200 201 static const struct dm_pci_ops pcie_xilinx_ops = { 202 .read_config = pcie_xilinx_read_config, 203 .write_config = pcie_xilinx_write_config, 204 }; 205 206 static const struct udevice_id pcie_xilinx_ids[] = { 207 { .compatible = "xlnx,axi-pcie-host-1.00.a" }, 208 { } 209 }; 210 211 U_BOOT_DRIVER(pcie_xilinx) = { 212 .name = "pcie_xilinx", 213 .id = UCLASS_PCI, 214 .of_match = pcie_xilinx_ids, 215 .ops = &pcie_xilinx_ops, 216 .ofdata_to_platdata = pcie_xilinx_ofdata_to_platdata, 217 .priv_auto_alloc_size = sizeof(struct xilinx_pcie), 218 }; 219