1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2017 NXP
4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
5  * Layerscape PCIe driver
6  */
7 
8 #include <common.h>
9 #include <pci.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/io.h>
12 #include <errno.h>
13 #ifdef CONFIG_OF_BOARD_SETUP
14 #include <linux/libfdt.h>
15 #include <fdt_support.h>
16 #ifdef CONFIG_ARM
17 #include <asm/arch/clock.h>
18 #endif
19 #include "pcie_layerscape.h"
20 
21 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
22 /*
23  * Return next available LUT index.
24  */
25 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
26 {
27 	if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
28 		return pcie->next_lut_index++;
29 	else
30 		return -ENOSPC;  /* LUT is full */
31 }
32 
33 /* returns the next available streamid for pcie, -errno if failed */
34 static int ls_pcie_next_streamid(void)
35 {
36 	static int next_stream_id = FSL_PEX_STREAM_ID_START;
37 
38 	if (next_stream_id > FSL_PEX_STREAM_ID_END)
39 		return -EINVAL;
40 
41 	return next_stream_id++;
42 }
43 
44 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
45 		       unsigned int offset)
46 {
47 	if (pcie->big_endian)
48 		out_be32(pcie->lut + offset, value);
49 	else
50 		out_le32(pcie->lut + offset, value);
51 }
52 
53 /*
54  * Program a single LUT entry
55  */
56 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
57 				    u32 streamid)
58 {
59 	/* leave mask as all zeroes, want to match all bits */
60 	lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
61 	lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
62 }
63 
64 /*
65  * An msi-map is a property to be added to the pci controller
66  * node.  It is a table, where each entry consists of 4 fields
67  * e.g.:
68  *
69  *      msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
70  *                 [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
71  */
72 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
73 				       u32 devid, u32 streamid)
74 {
75 	u32 *prop;
76 	u32 phandle;
77 	int nodeoffset;
78 	uint svr;
79 	char *compat = NULL;
80 
81 	/* find pci controller node */
82 	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
83 						   pcie->dbi_res.start);
84 	if (nodeoffset < 0) {
85 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
86 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
87 		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
88 		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
89 		    svr == SVR_LS2081A || svr == SVR_LS2041A)
90 			compat = "fsl,ls2088a-pcie";
91 		else
92 			compat = CONFIG_FSL_PCIE_COMPAT;
93 		if (compat)
94 			nodeoffset = fdt_node_offset_by_compat_reg(blob,
95 					compat, pcie->dbi_res.start);
96 #endif
97 		if (nodeoffset < 0)
98 			return;
99 	}
100 
101 	/* get phandle to MSI controller */
102 	prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
103 	if (prop == NULL) {
104 		debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
105 		      __func__, pcie->idx);
106 		return;
107 	}
108 	phandle = fdt32_to_cpu(*prop);
109 
110 	/* set one msi-map row */
111 	fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
112 	fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
113 	fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
114 	fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
115 }
116 
117 /*
118  * An iommu-map is a property to be added to the pci controller
119  * node.  It is a table, where each entry consists of 4 fields
120  * e.g.:
121  *
122  *      iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
123  *                 [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
124  */
125 static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
126 				       u32 devid, u32 streamid)
127 {
128 	u32 *prop;
129 	u32 iommu_map[4];
130 	int nodeoffset;
131 	int lenp;
132 	uint svr;
133 	char *compat = NULL;
134 
135 	/* find pci controller node */
136 	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
137 						   pcie->dbi_res.start);
138 	if (nodeoffset < 0) {
139 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
140 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
141 		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
142 		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
143 		    svr == SVR_LS2081A || svr == SVR_LS2041A)
144 			compat = "fsl,ls2088a-pcie";
145 		else
146 			compat = CONFIG_FSL_PCIE_COMPAT;
147 
148 		if (compat)
149 			nodeoffset = fdt_node_offset_by_compat_reg(blob,
150 						compat, pcie->dbi_res.start);
151 #endif
152 		if (nodeoffset < 0)
153 			return;
154 	}
155 
156 	/* get phandle to iommu controller */
157 	prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
158 	if (prop == NULL) {
159 		debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
160 		      __func__, pcie->idx);
161 		return;
162 	}
163 
164 	/* set iommu-map row */
165 	iommu_map[0] = cpu_to_fdt32(devid);
166 	iommu_map[1] = *++prop;
167 	iommu_map[2] = cpu_to_fdt32(streamid);
168 	iommu_map[3] = cpu_to_fdt32(1);
169 
170 	if (devid == 0) {
171 		fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
172 				    iommu_map, 16);
173 	} else {
174 		fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
175 	}
176 }
177 
178 static void fdt_fixup_pcie(void *blob)
179 {
180 	struct udevice *dev, *bus;
181 	struct ls_pcie *pcie;
182 	int streamid;
183 	int index;
184 	pci_dev_t bdf;
185 
186 	/* Scan all known buses */
187 	for (pci_find_first_device(&dev);
188 	     dev;
189 	     pci_find_next_device(&dev)) {
190 		for (bus = dev; device_is_on_pci_bus(bus);)
191 			bus = bus->parent;
192 		pcie = dev_get_priv(bus);
193 
194 		streamid = ls_pcie_next_streamid();
195 		if (streamid < 0) {
196 			debug("ERROR: no stream ids free\n");
197 			continue;
198 		}
199 
200 		index = ls_pcie_next_lut_index(pcie);
201 		if (index < 0) {
202 			debug("ERROR: no LUT indexes free\n");
203 			continue;
204 		}
205 
206 		/* the DT fixup must be relative to the hose first_busno */
207 		bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
208 		/* map PCI b.d.f to streamID in LUT */
209 		ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
210 					streamid);
211 		/* update msi-map in device tree */
212 		fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
213 					   streamid);
214 		/* update iommu-map in device tree */
215 		fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
216 					     streamid);
217 	}
218 }
219 #endif
220 
221 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
222 {
223 	int off;
224 	uint svr;
225 	char *compat = NULL;
226 
227 	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
228 					    pcie->dbi_res.start);
229 	if (off < 0) {
230 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
231 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
232 		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
233 		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
234 		    svr == SVR_LS2081A || svr == SVR_LS2041A)
235 			compat = "fsl,ls2088a-pcie";
236 		else
237 			compat = CONFIG_FSL_PCIE_COMPAT;
238 		if (compat)
239 			off = fdt_node_offset_by_compat_reg(blob,
240 					compat, pcie->dbi_res.start);
241 #endif
242 		if (off < 0)
243 			return;
244 	}
245 
246 	if (pcie->enabled)
247 		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
248 	else
249 		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
250 }
251 
252 /* Fixup Kernel DT for PCIe */
253 void ft_pci_setup(void *blob, bd_t *bd)
254 {
255 	struct ls_pcie *pcie;
256 
257 	list_for_each_entry(pcie, &ls_pcie_list, list)
258 		ft_pcie_ls_setup(blob, pcie);
259 
260 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
261 	fdt_fixup_pcie(blob);
262 #endif
263 }
264 
265 #else /* !CONFIG_OF_BOARD_SETUP */
266 void ft_pci_setup(void *blob, bd_t *bd)
267 {
268 }
269 #endif
270