1 /* 2 * Copyright 2017 NXP 3 * Copyright 2014-2015 Freescale Semiconductor, Inc. 4 * Layerscape PCIe driver 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <pci.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/io.h> 13 #include <errno.h> 14 #ifdef CONFIG_OF_BOARD_SETUP 15 #include <libfdt.h> 16 #include <fdt_support.h> 17 #include "pcie_layerscape.h" 18 19 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) 20 /* 21 * Return next available LUT index. 22 */ 23 static int ls_pcie_next_lut_index(struct ls_pcie *pcie) 24 { 25 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) 26 return pcie->next_lut_index++; 27 else 28 return -ENOSPC; /* LUT is full */ 29 } 30 31 /* returns the next available streamid for pcie, -errno if failed */ 32 static int ls_pcie_next_streamid(void) 33 { 34 static int next_stream_id = FSL_PEX_STREAM_ID_START; 35 36 if (next_stream_id > FSL_PEX_STREAM_ID_END) 37 return -EINVAL; 38 39 return next_stream_id++; 40 } 41 42 static void lut_writel(struct ls_pcie *pcie, unsigned int value, 43 unsigned int offset) 44 { 45 if (pcie->big_endian) 46 out_be32(pcie->lut + offset, value); 47 else 48 out_le32(pcie->lut + offset, value); 49 } 50 51 /* 52 * Program a single LUT entry 53 */ 54 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, 55 u32 streamid) 56 { 57 /* leave mask as all zeroes, want to match all bits */ 58 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index)); 59 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index)); 60 } 61 62 /* 63 * An msi-map is a property to be added to the pci controller 64 * node. It is a table, where each entry consists of 4 fields 65 * e.g.: 66 * 67 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count] 68 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>; 69 */ 70 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, 71 u32 devid, u32 streamid) 72 { 73 u32 *prop; 74 u32 phandle; 75 int nodeoffset; 76 uint svr; 77 char *compat = NULL; 78 79 /* find pci controller node */ 80 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", 81 pcie->dbi_res.start); 82 if (nodeoffset < 0) { 83 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ 84 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; 85 if (svr == SVR_LS2088A || svr == SVR_LS2084A || 86 svr == SVR_LS2048A || svr == SVR_LS2044A || 87 svr == SVR_LS2081A || svr == SVR_LS2041A) 88 compat = "fsl,ls2088a-pcie"; 89 else 90 compat = CONFIG_FSL_PCIE_COMPAT; 91 if (compat) 92 nodeoffset = fdt_node_offset_by_compat_reg(blob, 93 compat, pcie->dbi_res.start); 94 #endif 95 if (nodeoffset < 0) 96 return; 97 } 98 99 /* get phandle to MSI controller */ 100 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0); 101 if (prop == NULL) { 102 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n", 103 __func__, pcie->idx); 104 return; 105 } 106 phandle = fdt32_to_cpu(*prop); 107 108 /* set one msi-map row */ 109 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid); 110 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle); 111 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid); 112 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); 113 } 114 115 /* 116 * An iommu-map is a property to be added to the pci controller 117 * node. It is a table, where each entry consists of 4 fields 118 * e.g.: 119 * 120 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count] 121 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>; 122 */ 123 static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie, 124 u32 devid, u32 streamid) 125 { 126 u32 *prop; 127 u32 iommu_map[4]; 128 int nodeoffset; 129 int lenp; 130 131 /* find pci controller node */ 132 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", 133 pcie->dbi_res.start); 134 if (nodeoffset < 0) { 135 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ 136 nodeoffset = fdt_node_offset_by_compat_reg(blob, 137 CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start); 138 if (nodeoffset < 0) 139 return; 140 #else 141 return; 142 #endif 143 } 144 145 /* get phandle to iommu controller */ 146 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp); 147 if (prop == NULL) { 148 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n", 149 __func__, pcie->idx); 150 return; 151 } 152 153 /* set iommu-map row */ 154 iommu_map[0] = cpu_to_fdt32(devid); 155 iommu_map[1] = *++prop; 156 iommu_map[2] = cpu_to_fdt32(streamid); 157 iommu_map[3] = cpu_to_fdt32(1); 158 159 if (devid == 0) { 160 fdt_setprop_inplace(blob, nodeoffset, "iommu-map", 161 iommu_map, 16); 162 } else { 163 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16); 164 } 165 } 166 167 static void fdt_fixup_pcie(void *blob) 168 { 169 struct udevice *dev, *bus; 170 struct ls_pcie *pcie; 171 int streamid; 172 int index; 173 pci_dev_t bdf; 174 175 /* Scan all known buses */ 176 for (pci_find_first_device(&dev); 177 dev; 178 pci_find_next_device(&dev)) { 179 for (bus = dev; device_is_on_pci_bus(bus);) 180 bus = bus->parent; 181 pcie = dev_get_priv(bus); 182 183 streamid = ls_pcie_next_streamid(); 184 if (streamid < 0) { 185 debug("ERROR: no stream ids free\n"); 186 continue; 187 } 188 189 index = ls_pcie_next_lut_index(pcie); 190 if (index < 0) { 191 debug("ERROR: no LUT indexes free\n"); 192 continue; 193 } 194 195 /* the DT fixup must be relative to the hose first_busno */ 196 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0); 197 /* map PCI b.d.f to streamID in LUT */ 198 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8, 199 streamid); 200 /* update msi-map in device tree */ 201 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, 202 streamid); 203 /* update iommu-map in device tree */ 204 fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8, 205 streamid); 206 } 207 } 208 #endif 209 210 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) 211 { 212 int off; 213 uint svr; 214 char *compat = NULL; 215 216 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", 217 pcie->dbi_res.start); 218 if (off < 0) { 219 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ 220 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; 221 if (svr == SVR_LS2088A || svr == SVR_LS2084A || 222 svr == SVR_LS2048A || svr == SVR_LS2044A || 223 svr == SVR_LS2081A || svr == SVR_LS2041A) 224 compat = "fsl,ls2088a-pcie"; 225 else 226 compat = CONFIG_FSL_PCIE_COMPAT; 227 if (compat) 228 off = fdt_node_offset_by_compat_reg(blob, 229 compat, pcie->dbi_res.start); 230 #endif 231 if (off < 0) 232 return; 233 } 234 235 if (pcie->enabled) 236 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0); 237 else 238 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); 239 } 240 241 /* Fixup Kernel DT for PCIe */ 242 void ft_pci_setup(void *blob, bd_t *bd) 243 { 244 struct ls_pcie *pcie; 245 246 list_for_each_entry(pcie, &ls_pcie_list, list) 247 ft_pcie_ls_setup(blob, pcie); 248 249 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) 250 fdt_fixup_pcie(blob); 251 #endif 252 } 253 254 #else /* !CONFIG_OF_BOARD_SETUP */ 255 void ft_pci_setup(void *blob, bd_t *bd) 256 { 257 } 258 #endif 259