1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * Layerscape PCIe driver 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <pci.h> 10 #include <asm/arch/fsl_serdes.h> 11 #include <asm/io.h> 12 #include <errno.h> 13 #ifdef CONFIG_OF_BOARD_SETUP 14 #include <libfdt.h> 15 #include <fdt_support.h> 16 #include "pcie_layerscape.h" 17 18 #ifdef CONFIG_FSL_LSCH3 19 /* 20 * Return next available LUT index. 21 */ 22 static int ls_pcie_next_lut_index(struct ls_pcie *pcie) 23 { 24 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) 25 return pcie->next_lut_index++; 26 else 27 return -ENOSPC; /* LUT is full */ 28 } 29 30 /* returns the next available streamid for pcie, -errno if failed */ 31 static int ls_pcie_next_streamid(void) 32 { 33 static int next_stream_id = FSL_PEX_STREAM_ID_START; 34 35 if (next_stream_id > FSL_PEX_STREAM_ID_END) 36 return -EINVAL; 37 38 return next_stream_id++; 39 } 40 41 static void lut_writel(struct ls_pcie *pcie, unsigned int value, 42 unsigned int offset) 43 { 44 if (pcie->big_endian) 45 out_be32(pcie->lut + offset, value); 46 else 47 out_le32(pcie->lut + offset, value); 48 } 49 50 /* 51 * Program a single LUT entry 52 */ 53 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, 54 u32 streamid) 55 { 56 /* leave mask as all zeroes, want to match all bits */ 57 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index)); 58 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index)); 59 } 60 61 /* 62 * An msi-map is a property to be added to the pci controller 63 * node. It is a table, where each entry consists of 4 fields 64 * e.g.: 65 * 66 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count] 67 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>; 68 */ 69 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, 70 u32 devid, u32 streamid) 71 { 72 u32 *prop; 73 u32 phandle; 74 int nodeoffset; 75 76 /* find pci controller node */ 77 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", 78 pcie->dbi_res.start); 79 if (nodeoffset < 0) { 80 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ 81 nodeoffset = fdt_node_offset_by_compat_reg(blob, 82 CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start); 83 if (nodeoffset < 0) 84 return; 85 #else 86 return; 87 #endif 88 } 89 90 /* get phandle to MSI controller */ 91 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0); 92 if (prop == NULL) { 93 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n", 94 __func__, pcie->idx); 95 return; 96 } 97 phandle = fdt32_to_cpu(*prop); 98 99 /* set one msi-map row */ 100 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid); 101 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle); 102 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid); 103 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); 104 } 105 106 static void fdt_fixup_pcie(void *blob) 107 { 108 struct udevice *dev, *bus; 109 struct ls_pcie *pcie; 110 int streamid; 111 int index; 112 pci_dev_t bdf; 113 114 /* Scan all known buses */ 115 for (pci_find_first_device(&dev); 116 dev; 117 pci_find_next_device(&dev)) { 118 for (bus = dev; device_is_on_pci_bus(bus);) 119 bus = bus->parent; 120 pcie = dev_get_priv(bus); 121 122 streamid = ls_pcie_next_streamid(); 123 if (streamid < 0) { 124 debug("ERROR: no stream ids free\n"); 125 continue; 126 } 127 128 index = ls_pcie_next_lut_index(pcie); 129 if (index < 0) { 130 debug("ERROR: no LUT indexes free\n"); 131 continue; 132 } 133 134 /* the DT fixup must be relative to the hose first_busno */ 135 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0); 136 /* map PCI b.d.f to streamID in LUT */ 137 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8, 138 streamid); 139 /* update msi-map in device tree */ 140 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, 141 streamid); 142 } 143 } 144 #endif 145 146 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) 147 { 148 int off; 149 150 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", 151 pcie->dbi_res.start); 152 if (off < 0) { 153 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ 154 off = fdt_node_offset_by_compat_reg(blob, 155 CONFIG_FSL_PCIE_COMPAT, 156 pcie->dbi_res.start); 157 if (off < 0) 158 return; 159 #else 160 return; 161 #endif 162 } 163 164 if (pcie->enabled) 165 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0); 166 else 167 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); 168 } 169 170 /* Fixup Kernel DT for PCIe */ 171 void ft_pci_setup(void *blob, bd_t *bd) 172 { 173 struct ls_pcie *pcie; 174 175 list_for_each_entry(pcie, &ls_pcie_list, list) 176 ft_pcie_ls_setup(blob, pcie); 177 178 #ifdef CONFIG_FSL_LSCH3 179 fdt_fixup_pcie(blob); 180 #endif 181 } 182 183 #else /* !CONFIG_OF_BOARD_SETUP */ 184 void ft_pci_setup(void *blob, bd_t *bd) 185 { 186 } 187 #endif 188