1 /* 2 * Copyright 2017 NXP 3 * Copyright 2014-2015 Freescale Semiconductor, Inc. 4 * Layerscape PCIe driver 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/arch/fsl_serdes.h> 11 #include <pci.h> 12 #include <asm/io.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <dm.h> 16 #include "pcie_layerscape.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 LIST_HEAD(ls_pcie_list); 21 22 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) 23 { 24 return in_le32(pcie->dbi + offset); 25 } 26 27 static void dbi_writel(struct ls_pcie *pcie, unsigned int value, 28 unsigned int offset) 29 { 30 out_le32(pcie->dbi + offset, value); 31 } 32 33 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) 34 { 35 if (pcie->big_endian) 36 return in_be32(pcie->ctrl + offset); 37 else 38 return in_le32(pcie->ctrl + offset); 39 } 40 41 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value, 42 unsigned int offset) 43 { 44 if (pcie->big_endian) 45 out_be32(pcie->ctrl + offset, value); 46 else 47 out_le32(pcie->ctrl + offset, value); 48 } 49 50 static int ls_pcie_ltssm(struct ls_pcie *pcie) 51 { 52 u32 state; 53 uint svr; 54 55 svr = get_svr(); 56 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) { 57 state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx)); 58 state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; 59 } else { 60 state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK; 61 } 62 63 return state; 64 } 65 66 static int ls_pcie_link_up(struct ls_pcie *pcie) 67 { 68 int ltssm; 69 70 ltssm = ls_pcie_ltssm(pcie); 71 if (ltssm < LTSSM_PCIE_L0) 72 return 0; 73 74 return 1; 75 } 76 77 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev) 78 { 79 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, 80 PCIE_ATU_VIEWPORT); 81 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); 82 } 83 84 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev) 85 { 86 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, 87 PCIE_ATU_VIEWPORT); 88 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); 89 } 90 91 static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type, 92 u64 phys, u64 bus_addr, pci_size_t size) 93 { 94 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT); 95 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE); 96 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE); 97 dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT); 98 dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET); 99 dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET); 100 dbi_writel(pcie, type, PCIE_ATU_CR1); 101 dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 102 } 103 104 /* Use bar match mode and MEM type as default */ 105 static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, 106 int bar, u64 phys) 107 { 108 dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT); 109 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET); 110 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET); 111 dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); 112 dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | 113 PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2); 114 } 115 116 static void ls_pcie_dump_atu(struct ls_pcie *pcie) 117 { 118 int i; 119 120 for (i = 0; i < PCIE_ATU_REGION_NUM; i++) { 121 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i, 122 PCIE_ATU_VIEWPORT); 123 debug("iATU%d:\n", i); 124 debug("\tLOWER PHYS 0x%08x\n", 125 dbi_readl(pcie, PCIE_ATU_LOWER_BASE)); 126 debug("\tUPPER PHYS 0x%08x\n", 127 dbi_readl(pcie, PCIE_ATU_UPPER_BASE)); 128 debug("\tLOWER BUS 0x%08x\n", 129 dbi_readl(pcie, PCIE_ATU_LOWER_TARGET)); 130 debug("\tUPPER BUS 0x%08x\n", 131 dbi_readl(pcie, PCIE_ATU_UPPER_TARGET)); 132 debug("\tLIMIT 0x%08x\n", 133 readl(pcie->dbi + PCIE_ATU_LIMIT)); 134 debug("\tCR1 0x%08x\n", 135 dbi_readl(pcie, PCIE_ATU_CR1)); 136 debug("\tCR2 0x%08x\n", 137 dbi_readl(pcie, PCIE_ATU_CR2)); 138 } 139 } 140 141 static void ls_pcie_setup_atu(struct ls_pcie *pcie) 142 { 143 struct pci_region *io, *mem, *pref; 144 unsigned long long offset = 0; 145 int idx = 0; 146 uint svr; 147 148 svr = get_svr(); 149 if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) { 150 offset = LS1021_PCIE_SPACE_OFFSET + 151 LS1021_PCIE_SPACE_SIZE * pcie->idx; 152 } 153 154 /* ATU 0 : OUTBOUND : CFG0 */ 155 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, 156 PCIE_ATU_TYPE_CFG0, 157 pcie->cfg_res.start + offset, 158 0, 159 fdt_resource_size(&pcie->cfg_res) / 2); 160 /* ATU 1 : OUTBOUND : CFG1 */ 161 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, 162 PCIE_ATU_TYPE_CFG1, 163 pcie->cfg_res.start + offset + 164 fdt_resource_size(&pcie->cfg_res) / 2, 165 0, 166 fdt_resource_size(&pcie->cfg_res) / 2); 167 168 pci_get_regions(pcie->bus, &io, &mem, &pref); 169 idx = PCIE_ATU_REGION_INDEX1 + 1; 170 171 /* Fix the pcie memory map for LS2088A series SoCs */ 172 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; 173 if (svr == SVR_LS2088A || svr == SVR_LS2084A || 174 svr == SVR_LS2048A || svr == SVR_LS2044A || 175 svr == SVR_LS2081A || svr == SVR_LS2041A) { 176 if (io) 177 io->phys_start = (io->phys_start & 178 (PCIE_PHYS_SIZE - 1)) + 179 LS2088A_PCIE1_PHYS_ADDR + 180 LS2088A_PCIE_PHYS_SIZE * pcie->idx; 181 if (mem) 182 mem->phys_start = (mem->phys_start & 183 (PCIE_PHYS_SIZE - 1)) + 184 LS2088A_PCIE1_PHYS_ADDR + 185 LS2088A_PCIE_PHYS_SIZE * pcie->idx; 186 if (pref) 187 pref->phys_start = (pref->phys_start & 188 (PCIE_PHYS_SIZE - 1)) + 189 LS2088A_PCIE1_PHYS_ADDR + 190 LS2088A_PCIE_PHYS_SIZE * pcie->idx; 191 } 192 193 if (io) 194 /* ATU : OUTBOUND : IO */ 195 ls_pcie_atu_outbound_set(pcie, idx++, 196 PCIE_ATU_TYPE_IO, 197 io->phys_start + offset, 198 io->bus_start, 199 io->size); 200 201 if (mem) 202 /* ATU : OUTBOUND : MEM */ 203 ls_pcie_atu_outbound_set(pcie, idx++, 204 PCIE_ATU_TYPE_MEM, 205 mem->phys_start + offset, 206 mem->bus_start, 207 mem->size); 208 209 if (pref) 210 /* ATU : OUTBOUND : pref */ 211 ls_pcie_atu_outbound_set(pcie, idx++, 212 PCIE_ATU_TYPE_MEM, 213 pref->phys_start + offset, 214 pref->bus_start, 215 pref->size); 216 217 ls_pcie_dump_atu(pcie); 218 } 219 220 /* Return 0 if the address is valid, -errno if not valid */ 221 static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf) 222 { 223 struct udevice *bus = pcie->bus; 224 225 if (!pcie->enabled) 226 return -ENXIO; 227 228 if (PCI_BUS(bdf) < bus->seq) 229 return -EINVAL; 230 231 if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie))) 232 return -EINVAL; 233 234 if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0)) 235 return -EINVAL; 236 237 return 0; 238 } 239 240 void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf, 241 int offset) 242 { 243 struct udevice *bus = pcie->bus; 244 u32 busdev; 245 246 if (PCI_BUS(bdf) == bus->seq) 247 return pcie->dbi + offset; 248 249 busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) | 250 PCIE_ATU_DEV(PCI_DEV(bdf)) | 251 PCIE_ATU_FUNC(PCI_FUNC(bdf)); 252 253 if (PCI_BUS(bdf) == bus->seq + 1) { 254 ls_pcie_cfg0_set_busdev(pcie, busdev); 255 return pcie->cfg0 + offset; 256 } else { 257 ls_pcie_cfg1_set_busdev(pcie, busdev); 258 return pcie->cfg1 + offset; 259 } 260 } 261 262 static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf, 263 uint offset, ulong *valuep, 264 enum pci_size_t size) 265 { 266 struct ls_pcie *pcie = dev_get_priv(bus); 267 void *address; 268 269 if (ls_pcie_addr_valid(pcie, bdf)) { 270 *valuep = pci_get_ff(size); 271 return 0; 272 } 273 274 address = ls_pcie_conf_address(pcie, bdf, offset); 275 276 switch (size) { 277 case PCI_SIZE_8: 278 *valuep = readb(address); 279 return 0; 280 case PCI_SIZE_16: 281 *valuep = readw(address); 282 return 0; 283 case PCI_SIZE_32: 284 *valuep = readl(address); 285 return 0; 286 default: 287 return -EINVAL; 288 } 289 } 290 291 static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf, 292 uint offset, ulong value, 293 enum pci_size_t size) 294 { 295 struct ls_pcie *pcie = dev_get_priv(bus); 296 void *address; 297 298 if (ls_pcie_addr_valid(pcie, bdf)) 299 return 0; 300 301 address = ls_pcie_conf_address(pcie, bdf, offset); 302 303 switch (size) { 304 case PCI_SIZE_8: 305 writeb(value, address); 306 return 0; 307 case PCI_SIZE_16: 308 writew(value, address); 309 return 0; 310 case PCI_SIZE_32: 311 writel(value, address); 312 return 0; 313 default: 314 return -EINVAL; 315 } 316 } 317 318 /* Clear multi-function bit */ 319 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) 320 { 321 writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE); 322 } 323 324 /* Fix class value */ 325 static void ls_pcie_fix_class(struct ls_pcie *pcie) 326 { 327 writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); 328 } 329 330 /* Drop MSG TLP except for Vendor MSG */ 331 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) 332 { 333 u32 val; 334 335 val = dbi_readl(pcie, PCIE_STRFMR1); 336 val &= 0xDFFFFFFF; 337 dbi_writel(pcie, val, PCIE_STRFMR1); 338 } 339 340 /* Disable all bars in RC mode */ 341 static void ls_pcie_disable_bars(struct ls_pcie *pcie) 342 { 343 u32 sriov; 344 345 sriov = in_le32(pcie->dbi + PCIE_SRIOV); 346 347 /* 348 * TODO: For PCIe controller with SRIOV, the method to disable bars 349 * is different and more complex, so will add later. 350 */ 351 if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) 352 return; 353 354 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0); 355 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1); 356 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1); 357 } 358 359 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie) 360 { 361 ls_pcie_setup_atu(pcie); 362 363 dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN); 364 ls_pcie_fix_class(pcie); 365 ls_pcie_clear_multifunction(pcie); 366 ls_pcie_drop_msg_tlp(pcie); 367 dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN); 368 369 ls_pcie_disable_bars(pcie); 370 } 371 372 static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie) 373 { 374 u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE; 375 376 /* ATU 0 : INBOUND : map BAR0 */ 377 ls_pcie_atu_inbound_set(pcie, 0, 0, phys); 378 /* ATU 1 : INBOUND : map BAR1 */ 379 phys += PCIE_BAR1_SIZE; 380 ls_pcie_atu_inbound_set(pcie, 1, 1, phys); 381 /* ATU 2 : INBOUND : map BAR2 */ 382 phys += PCIE_BAR2_SIZE; 383 ls_pcie_atu_inbound_set(pcie, 2, 2, phys); 384 /* ATU 3 : INBOUND : map BAR4 */ 385 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE; 386 ls_pcie_atu_inbound_set(pcie, 3, 4, phys); 387 388 /* ATU 0 : OUTBOUND : map MEM */ 389 ls_pcie_atu_outbound_set(pcie, 0, 390 PCIE_ATU_TYPE_MEM, 391 pcie->cfg_res.start, 392 0, 393 CONFIG_SYS_PCI_MEMORY_SIZE); 394 } 395 396 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ 397 static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) 398 { 399 /* The least inbound window is 4KiB */ 400 if (size < 4 * 1024) 401 return; 402 403 switch (bar) { 404 case 0: 405 writel(size - 1, bar_base + PCI_BASE_ADDRESS_0); 406 break; 407 case 1: 408 writel(size - 1, bar_base + PCI_BASE_ADDRESS_1); 409 break; 410 case 2: 411 writel(size - 1, bar_base + PCI_BASE_ADDRESS_2); 412 writel(0, bar_base + PCI_BASE_ADDRESS_3); 413 break; 414 case 4: 415 writel(size - 1, bar_base + PCI_BASE_ADDRESS_4); 416 writel(0, bar_base + PCI_BASE_ADDRESS_5); 417 break; 418 default: 419 break; 420 } 421 } 422 423 static void ls_pcie_ep_setup_bars(void *bar_base) 424 { 425 /* BAR0 - 32bit - 4K configuration */ 426 ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); 427 /* BAR1 - 32bit - 8K MSIX*/ 428 ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); 429 /* BAR2 - 64bit - 4K MEM desciptor */ 430 ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); 431 /* BAR4 - 64bit - 1M MEM*/ 432 ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); 433 } 434 435 static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) 436 { 437 ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG); 438 } 439 440 static void ls_pcie_setup_ep(struct ls_pcie *pcie) 441 { 442 u32 sriov; 443 444 sriov = readl(pcie->dbi + PCIE_SRIOV); 445 if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) { 446 int pf, vf; 447 448 for (pf = 0; pf < PCIE_PF_NUM; pf++) { 449 for (vf = 0; vf <= PCIE_VF_NUM; vf++) { 450 ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf), 451 PCIE_PF_VF_CTRL); 452 453 ls_pcie_ep_setup_bars(pcie->dbi); 454 ls_pcie_ep_setup_atu(pcie); 455 } 456 } 457 /* Disable CFG2 */ 458 ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); 459 } else { 460 ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); 461 ls_pcie_ep_setup_atu(pcie); 462 } 463 464 ls_pcie_ep_enable_cfg(pcie); 465 } 466 467 static int ls_pcie_probe(struct udevice *dev) 468 { 469 struct ls_pcie *pcie = dev_get_priv(dev); 470 const void *fdt = gd->fdt_blob; 471 int node = dev_of_offset(dev); 472 u8 header_type; 473 u16 link_sta; 474 bool ep_mode; 475 uint svr; 476 int ret; 477 478 pcie->bus = dev; 479 480 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", 481 "dbi", &pcie->dbi_res); 482 if (ret) { 483 printf("ls-pcie: resource \"dbi\" not found\n"); 484 return ret; 485 } 486 487 pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE; 488 489 list_add(&pcie->list, &ls_pcie_list); 490 491 pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); 492 if (!pcie->enabled) { 493 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); 494 return 0; 495 } 496 497 pcie->dbi = map_physmem(pcie->dbi_res.start, 498 fdt_resource_size(&pcie->dbi_res), 499 MAP_NOCACHE); 500 501 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", 502 "lut", &pcie->lut_res); 503 if (!ret) 504 pcie->lut = map_physmem(pcie->lut_res.start, 505 fdt_resource_size(&pcie->lut_res), 506 MAP_NOCACHE); 507 508 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", 509 "ctrl", &pcie->ctrl_res); 510 if (!ret) 511 pcie->ctrl = map_physmem(pcie->ctrl_res.start, 512 fdt_resource_size(&pcie->ctrl_res), 513 MAP_NOCACHE); 514 if (!pcie->ctrl) 515 pcie->ctrl = pcie->lut; 516 517 if (!pcie->ctrl) { 518 printf("%s: NOT find CTRL\n", dev->name); 519 return -1; 520 } 521 522 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", 523 "config", &pcie->cfg_res); 524 if (ret) { 525 printf("%s: resource \"config\" not found\n", dev->name); 526 return ret; 527 } 528 529 /* 530 * Fix the pcie memory map address and PF control registers address 531 * for LS2088A series SoCs 532 */ 533 svr = get_svr(); 534 svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; 535 if (svr == SVR_LS2088A || svr == SVR_LS2084A || 536 svr == SVR_LS2048A || svr == SVR_LS2044A || 537 svr == SVR_LS2081A || svr == SVR_LS2041A) { 538 pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + 539 LS2088A_PCIE_PHYS_SIZE * pcie->idx; 540 pcie->ctrl = pcie->lut + 0x40000; 541 } 542 543 pcie->cfg0 = map_physmem(pcie->cfg_res.start, 544 fdt_resource_size(&pcie->cfg_res), 545 MAP_NOCACHE); 546 pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2; 547 548 pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian"); 549 550 debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n", 551 dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut, 552 (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0, 553 pcie->big_endian); 554 555 header_type = readb(pcie->dbi + PCI_HEADER_TYPE); 556 ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; 557 printf("PCIe%u: %s %s", pcie->idx, dev->name, 558 ep_mode ? "Endpoint" : "Root Complex"); 559 560 if (ep_mode) 561 ls_pcie_setup_ep(pcie); 562 else 563 ls_pcie_setup_ctrl(pcie); 564 565 if (!ls_pcie_link_up(pcie)) { 566 /* Let the user know there's no PCIe link */ 567 printf(": no link\n"); 568 return 0; 569 } 570 571 /* Print the negotiated PCIe link width */ 572 link_sta = readw(pcie->dbi + PCIE_LINK_STA); 573 printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4, 574 link_sta & PCIE_LINK_SPEED_MASK); 575 576 return 0; 577 } 578 579 static const struct dm_pci_ops ls_pcie_ops = { 580 .read_config = ls_pcie_read_config, 581 .write_config = ls_pcie_write_config, 582 }; 583 584 static const struct udevice_id ls_pcie_ids[] = { 585 { .compatible = "fsl,ls-pcie" }, 586 { } 587 }; 588 589 U_BOOT_DRIVER(pci_layerscape) = { 590 .name = "pci_layerscape", 591 .id = UCLASS_PCI, 592 .of_match = ls_pcie_ids, 593 .ops = &ls_pcie_ops, 594 .probe = ls_pcie_probe, 595 .priv_auto_alloc_size = sizeof(struct ls_pcie), 596 }; 597