1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * Layerscape PCIe driver 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/fsl_serdes.h> 10 #include <pci.h> 11 #include <asm/io.h> 12 #include <errno.h> 13 #include <malloc.h> 14 15 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 16 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE 17 #endif 18 19 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 20 #define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE 21 #endif 22 23 #ifndef CONFIG_SYS_PCI_MEMORY_SIZE 24 #define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */ 25 #endif 26 27 /* iATU registers */ 28 #define PCIE_ATU_VIEWPORT 0x900 29 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) 30 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) 31 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 32 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 33 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) 34 #define PCIE_ATU_REGION_INDEX3 (0x3 << 0) 35 #define PCIE_ATU_CR1 0x904 36 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 37 #define PCIE_ATU_TYPE_IO (0x2 << 0) 38 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 39 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 40 #define PCIE_ATU_CR2 0x908 41 #define PCIE_ATU_ENABLE (0x1 << 31) 42 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 43 #define PCIE_ATU_LOWER_BASE 0x90C 44 #define PCIE_ATU_UPPER_BASE 0x910 45 #define PCIE_ATU_LIMIT 0x914 46 #define PCIE_ATU_LOWER_TARGET 0x918 47 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 48 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 49 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 50 #define PCIE_ATU_UPPER_TARGET 0x91C 51 52 /* LUT registers */ 53 #define PCIE_LUT_BASE 0x80000 54 #define PCIE_LUT_DBG 0x7FC 55 56 #define PCIE_DBI_RO_WR_EN 0x8bc 57 58 #define PCIE_LINK_CAP 0x7c 59 #define PCIE_LINK_SPEED_MASK 0xf 60 #define PCIE_LINK_STA 0x82 61 62 #define LTSSM_STATE_MASK 0x3f 63 #define LTSSM_PCIE_L0 0x11 /* L0 state */ 64 65 #define PCIE_DBI_SIZE 0x100000 /* 1M */ 66 67 struct ls_pcie { 68 int idx; 69 void __iomem *dbi; 70 void __iomem *va_cfg0; 71 void __iomem *va_cfg1; 72 struct pci_controller hose; 73 }; 74 75 struct ls_pcie_info { 76 unsigned long regs; 77 int pci_num; 78 u64 cfg0_phys; 79 u64 cfg0_size; 80 u64 cfg1_phys; 81 u64 cfg1_size; 82 u64 mem_bus; 83 u64 mem_phys; 84 u64 mem_size; 85 u64 io_bus; 86 u64 io_phys; 87 u64 io_size; 88 }; 89 90 #define SET_LS_PCIE_INFO(x, num) \ 91 { \ 92 x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ 93 x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \ 94 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ 95 x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \ 96 x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \ 97 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ 98 x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \ 99 x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \ 100 x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \ 101 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ 102 x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \ 103 x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \ 104 x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \ 105 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ 106 x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \ 107 x.pci_num = num; \ 108 } 109 110 #ifdef CONFIG_LS102XA 111 #include <asm/arch/immap_ls102xa.h> 112 113 /* PEX1/2 Misc Ports Status Register */ 114 #define LTSSM_STATE_SHIFT 20 115 116 static int ls_pcie_link_state(struct ls_pcie *pcie) 117 { 118 u32 state; 119 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 120 121 state = in_be32(&scfg->pexmscportsr[pcie->idx]); 122 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; 123 if (state < LTSSM_PCIE_L0) { 124 debug("....PCIe link error. LTSSM=0x%02x.\n", state); 125 return 0; 126 } 127 128 return 1; 129 } 130 #else 131 static int ls_pcie_link_state(struct ls_pcie *pcie) 132 { 133 u32 state; 134 135 state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & 136 LTSSM_STATE_MASK; 137 if (state < LTSSM_PCIE_L0) { 138 debug("....PCIe link error. LTSSM=0x%02x.\n", state); 139 return 0; 140 } 141 142 return 1; 143 } 144 #endif 145 146 static int ls_pcie_link_up(struct ls_pcie *pcie) 147 { 148 int state; 149 u32 cap; 150 151 state = ls_pcie_link_state(pcie); 152 if (state) 153 return state; 154 155 /* Try to download speed to gen1 */ 156 cap = readl(pcie->dbi + PCIE_LINK_CAP); 157 writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP); 158 /* 159 * Notice: the following delay has critical impact on link training 160 * if too short (<30ms) the link doesn't get up. 161 */ 162 mdelay(100); 163 state = ls_pcie_link_state(pcie); 164 if (state) 165 return state; 166 167 writel(cap, pcie->dbi + PCIE_LINK_CAP); 168 169 return 0; 170 } 171 172 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev) 173 { 174 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, 175 pcie->dbi + PCIE_ATU_VIEWPORT); 176 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET); 177 } 178 179 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev) 180 { 181 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, 182 pcie->dbi + PCIE_ATU_VIEWPORT); 183 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET); 184 } 185 186 static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type, 187 u64 phys, u64 bus_addr, pci_size_t size) 188 { 189 writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT); 190 writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE); 191 writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE); 192 writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT); 193 writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET); 194 writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET); 195 writel(type, pcie->dbi + PCIE_ATU_CR1); 196 writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2); 197 } 198 199 static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info) 200 { 201 #ifdef DEBUG 202 int i; 203 #endif 204 205 /* ATU 0 : OUTBOUND : CFG0 */ 206 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, 207 PCIE_ATU_TYPE_CFG0, 208 info->cfg0_phys, 209 0, 210 info->cfg0_size); 211 /* ATU 1 : OUTBOUND : CFG1 */ 212 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, 213 PCIE_ATU_TYPE_CFG1, 214 info->cfg1_phys, 215 0, 216 info->cfg1_size); 217 /* ATU 2 : OUTBOUND : MEM */ 218 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2, 219 PCIE_ATU_TYPE_MEM, 220 info->mem_phys, 221 info->mem_bus, 222 info->mem_size); 223 /* ATU 3 : OUTBOUND : IO */ 224 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3, 225 PCIE_ATU_TYPE_IO, 226 info->io_phys, 227 info->io_bus, 228 info->io_size); 229 230 #ifdef DEBUG 231 for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) { 232 writel(PCIE_ATU_REGION_OUTBOUND | i, 233 pcie->dbi + PCIE_ATU_VIEWPORT); 234 debug("iATU%d:\n", i); 235 debug("\tLOWER PHYS 0x%08x\n", 236 readl(pcie->dbi + PCIE_ATU_LOWER_BASE)); 237 debug("\tUPPER PHYS 0x%08x\n", 238 readl(pcie->dbi + PCIE_ATU_UPPER_BASE)); 239 debug("\tLOWER BUS 0x%08x\n", 240 readl(pcie->dbi + PCIE_ATU_LOWER_TARGET)); 241 debug("\tUPPER BUS 0x%08x\n", 242 readl(pcie->dbi + PCIE_ATU_UPPER_TARGET)); 243 debug("\tLIMIT 0x%08x\n", 244 readl(pcie->dbi + PCIE_ATU_LIMIT)); 245 debug("\tCR1 0x%08x\n", 246 readl(pcie->dbi + PCIE_ATU_CR1)); 247 debug("\tCR2 0x%08x\n", 248 readl(pcie->dbi + PCIE_ATU_CR2)); 249 } 250 #endif 251 } 252 253 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 254 { 255 /* Do not skip controller */ 256 return 0; 257 } 258 259 static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d) 260 { 261 if (PCI_DEV(d) > 0) 262 return -EINVAL; 263 264 /* Controller does not support multi-function in RC mode */ 265 if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0)) 266 return -EINVAL; 267 268 return 0; 269 } 270 271 static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d, 272 int where, u32 *val) 273 { 274 struct ls_pcie *pcie = hose->priv_data; 275 u32 busdev, *addr; 276 277 if (ls_pcie_addr_valid(hose, d)) { 278 *val = 0xffffffff; 279 return -EINVAL; 280 } 281 282 if (PCI_BUS(d) == hose->first_busno) { 283 addr = pcie->dbi + (where & ~0x3); 284 } else { 285 busdev = PCIE_ATU_BUS(PCI_BUS(d)) | 286 PCIE_ATU_DEV(PCI_DEV(d)) | 287 PCIE_ATU_FUNC(PCI_FUNC(d)); 288 289 if (PCI_BUS(d) == hose->first_busno + 1) { 290 ls_pcie_cfg0_set_busdev(pcie, busdev); 291 addr = pcie->va_cfg0 + (where & ~0x3); 292 } else { 293 ls_pcie_cfg1_set_busdev(pcie, busdev); 294 addr = pcie->va_cfg1 + (where & ~0x3); 295 } 296 } 297 298 *val = readl(addr); 299 300 return 0; 301 } 302 303 static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d, 304 int where, u32 val) 305 { 306 struct ls_pcie *pcie = hose->priv_data; 307 u32 busdev, *addr; 308 309 if (ls_pcie_addr_valid(hose, d)) 310 return -EINVAL; 311 312 if (PCI_BUS(d) == hose->first_busno) { 313 addr = pcie->dbi + (where & ~0x3); 314 } else { 315 busdev = PCIE_ATU_BUS(PCI_BUS(d)) | 316 PCIE_ATU_DEV(PCI_DEV(d)) | 317 PCIE_ATU_FUNC(PCI_FUNC(d)); 318 319 if (PCI_BUS(d) == hose->first_busno + 1) { 320 ls_pcie_cfg0_set_busdev(pcie, busdev); 321 addr = pcie->va_cfg0 + (where & ~0x3); 322 } else { 323 ls_pcie_cfg1_set_busdev(pcie, busdev); 324 addr = pcie->va_cfg1 + (where & ~0x3); 325 } 326 } 327 328 writel(val, addr); 329 330 return 0; 331 } 332 333 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie, 334 struct ls_pcie_info *info) 335 { 336 struct pci_controller *hose = &pcie->hose; 337 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 338 339 ls_pcie_setup_atu(pcie, info); 340 341 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0); 342 343 /* program correct class for RC */ 344 writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN); 345 pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE, 346 PCI_CLASS_BRIDGE_PCI); 347 #ifndef CONFIG_LS102XA 348 writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN); 349 #endif 350 } 351 352 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) 353 { 354 struct ls_pcie *pcie; 355 struct pci_controller *hose; 356 int num = dev - PCIE1; 357 pci_dev_t pdev = PCI_BDF(busno, 0, 0); 358 int i, linkup, ep_mode; 359 u8 header_type; 360 u16 temp16; 361 362 if (!is_serdes_configured(dev)) { 363 printf("PCIe%d: disabled\n", num + 1); 364 return busno; 365 } 366 367 pcie = malloc(sizeof(*pcie)); 368 if (!pcie) 369 return busno; 370 memset(pcie, 0, sizeof(*pcie)); 371 372 hose = &pcie->hose; 373 hose->priv_data = pcie; 374 hose->first_busno = busno; 375 pcie->idx = num; 376 pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE); 377 pcie->va_cfg0 = map_physmem(info->cfg0_phys, 378 info->cfg0_size, 379 MAP_NOCACHE); 380 pcie->va_cfg1 = map_physmem(info->cfg1_phys, 381 info->cfg1_size, 382 MAP_NOCACHE); 383 384 /* outbound memory */ 385 pci_set_region(&hose->regions[0], 386 (pci_size_t)info->mem_bus, 387 (phys_size_t)info->mem_phys, 388 (pci_size_t)info->mem_size, 389 PCI_REGION_MEM); 390 391 /* outbound io */ 392 pci_set_region(&hose->regions[1], 393 (pci_size_t)info->io_bus, 394 (phys_size_t)info->io_phys, 395 (pci_size_t)info->io_size, 396 PCI_REGION_IO); 397 398 /* System memory space */ 399 pci_set_region(&hose->regions[2], 400 CONFIG_SYS_PCI_MEMORY_BUS, 401 CONFIG_SYS_PCI_MEMORY_PHYS, 402 CONFIG_SYS_PCI_MEMORY_SIZE, 403 PCI_REGION_SYS_MEMORY); 404 405 hose->region_count = 3; 406 407 for (i = 0; i < hose->region_count; i++) 408 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", 409 i, 410 (u64)hose->regions[i].phys_start, 411 (u64)hose->regions[i].bus_start, 412 (u64)hose->regions[i].size, 413 hose->regions[i].flags); 414 415 pci_set_ops(hose, 416 pci_hose_read_config_byte_via_dword, 417 pci_hose_read_config_word_via_dword, 418 ls_pcie_read_config, 419 pci_hose_write_config_byte_via_dword, 420 pci_hose_write_config_word_via_dword, 421 ls_pcie_write_config); 422 423 pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type); 424 ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; 425 printf("PCIe%u: %s ", info->pci_num, 426 ep_mode ? "Endpoint" : "Root Complex"); 427 428 linkup = ls_pcie_link_up(pcie); 429 430 if (!linkup) { 431 /* Let the user know there's no PCIe link */ 432 printf("no link, regs @ 0x%lx\n", info->regs); 433 hose->last_busno = hose->first_busno; 434 return busno; 435 } 436 437 /* Print the negotiated PCIe link width */ 438 pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16); 439 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, 440 (temp16 & 0xf), info->regs); 441 442 if (ep_mode) 443 return busno; 444 445 ls_pcie_setup_ctrl(pcie, info); 446 447 pci_register_hose(hose); 448 449 hose->last_busno = pci_hose_scan(hose); 450 451 printf("PCIe%x: Bus %02x - %02x\n", 452 info->pci_num, hose->first_busno, hose->last_busno); 453 454 return hose->last_busno + 1; 455 } 456 457 int ls_pcie_init_board(int busno) 458 { 459 struct ls_pcie_info info; 460 461 #ifdef CONFIG_PCIE1 462 SET_LS_PCIE_INFO(info, 1); 463 busno = ls_pcie_init_ctrl(busno, PCIE1, &info); 464 #endif 465 466 #ifdef CONFIG_PCIE2 467 SET_LS_PCIE_INFO(info, 2); 468 busno = ls_pcie_init_ctrl(busno, PCIE2, &info); 469 #endif 470 471 #ifdef CONFIG_PCIE3 472 SET_LS_PCIE_INFO(info, 3); 473 busno = ls_pcie_init_ctrl(busno, PCIE3, &info); 474 #endif 475 476 #ifdef CONFIG_PCIE4 477 SET_LS_PCIE_INFO(info, 4); 478 busno = ls_pcie_init_ctrl(busno, PCIE4, &info); 479 #endif 480 481 return busno; 482 } 483 484 void pci_init_board(void) 485 { 486 ls_pcie_init_board(0); 487 } 488 489 #ifdef CONFIG_OF_BOARD_SETUP 490 #include <libfdt.h> 491 #include <fdt_support.h> 492 493 static void ft_pcie_ls_setup(void *blob, const char *pci_compat, 494 unsigned long ctrl_addr, enum srds_prtcl dev) 495 { 496 int off; 497 498 off = fdt_node_offset_by_compat_reg(blob, pci_compat, 499 (phys_addr_t)ctrl_addr); 500 if (off < 0) 501 return; 502 503 if (!is_serdes_configured(dev)) 504 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); 505 } 506 507 void ft_pci_setup(void *blob, bd_t *bd) 508 { 509 #ifdef CONFIG_PCIE1 510 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); 511 #endif 512 513 #ifdef CONFIG_PCIE2 514 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); 515 #endif 516 517 #ifdef CONFIG_PCIE3 518 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3); 519 #endif 520 521 #ifdef CONFIG_PCIE4 522 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4); 523 #endif 524 } 525 526 #else 527 void ft_pci_setup(void *blob, bd_t *bd) 528 { 529 } 530 #endif 531