1 /* 2 * Copyright (C) 2015 Marvell International Ltd. 3 * 4 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 5 * 6 * Based on: 7 * - drivers/pci/pcie_imx.c 8 * - drivers/pci/pci_mvebu.c 9 * - drivers/pci/pcie_xilinx.c 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <pci.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* PCI Config space registers */ 23 #define PCIE_CONFIG_BAR0 0x10 24 #define PCIE_LINK_STATUS_REG 0x80 25 #define PCIE_LINK_STATUS_SPEED_OFF 16 26 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 27 #define PCIE_LINK_STATUS_WIDTH_OFF 20 28 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 29 30 /* Resizable bar capability registers */ 31 #define RESIZABLE_BAR_CAP 0x250 32 #define RESIZABLE_BAR_CTL0 0x254 33 #define RESIZABLE_BAR_CTL1 0x258 34 35 /* iATU registers */ 36 #define PCIE_ATU_VIEWPORT 0x900 37 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) 38 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) 39 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 40 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 41 #define PCIE_ATU_CR1 0x904 42 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 43 #define PCIE_ATU_TYPE_IO (0x2 << 0) 44 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 45 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 46 #define PCIE_ATU_CR2 0x908 47 #define PCIE_ATU_ENABLE (0x1 << 31) 48 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 49 #define PCIE_ATU_LOWER_BASE 0x90C 50 #define PCIE_ATU_UPPER_BASE 0x910 51 #define PCIE_ATU_LIMIT 0x914 52 #define PCIE_ATU_LOWER_TARGET 0x918 53 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 54 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 55 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 56 #define PCIE_ATU_UPPER_TARGET 0x91C 57 58 #define PCIE_LINK_CAPABILITY 0x7C 59 #define PCIE_LINK_CTL_2 0xA0 60 #define TARGET_LINK_SPEED_MASK 0xF 61 #define LINK_SPEED_GEN_1 0x1 62 #define LINK_SPEED_GEN_2 0x2 63 #define LINK_SPEED_GEN_3 0x3 64 65 #define PCIE_GEN3_RELATED 0x890 66 #define GEN3_EQU_DISABLE (1 << 16) 67 #define GEN3_ZRXDC_NON_COMP (1 << 0) 68 69 #define PCIE_GEN3_EQU_CTRL 0x8A8 70 #define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5) 71 72 #define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4) 73 74 #define PCIE_LINK_UP_TIMEOUT_MS 100 75 76 #define PCIE_GLOBAL_CONTROL 0x8000 77 #define PCIE_APP_LTSSM_EN (1 << 2) 78 #define PCIE_DEVICE_TYPE_OFFSET (4) 79 #define PCIE_DEVICE_TYPE_MASK (0xF) 80 #define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */ 81 #define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */ 82 #define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */ 83 84 #define PCIE_GLOBAL_STATUS 0x8008 85 #define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1) 86 #define PCIE_GLB_STS_PHY_LINK_UP (1 << 9) 87 88 #define PCIE_ARCACHE_TRC 0x8050 89 #define PCIE_AWCACHE_TRC 0x8054 90 #define ARCACHE_SHAREABLE_CACHEABLE 0x3511 91 #define AWCACHE_SHAREABLE_CACHEABLE 0x5311 92 93 #define LINK_SPEED_GEN_1 0x1 94 #define LINK_SPEED_GEN_2 0x2 95 #define LINK_SPEED_GEN_3 0x3 96 97 /** 98 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state 99 * 100 * @ctrl_base: The base address of the register space 101 * @cfg_base: The base address of the configuration space 102 * @cfg_size: The size of the configuration space which is needed 103 * as it gets written into the PCIE_ATU_LIMIT register 104 * @first_busno: This driver supports multiple PCIe controllers. 105 * first_busno stores the bus number of the PCIe root-port 106 * number which may vary depending on the PCIe setup 107 * (PEX switches etc). 108 */ 109 struct pcie_dw_mvebu { 110 void *ctrl_base; 111 void *cfg_base; 112 fdt_size_t cfg_size; 113 int first_busno; 114 115 /* IO and MEM PCI regions */ 116 struct pci_region io; 117 struct pci_region mem; 118 }; 119 120 static int pcie_dw_get_link_speed(const void *regs_base) 121 { 122 return (readl(regs_base + PCIE_LINK_STATUS_REG) & 123 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 124 } 125 126 static int pcie_dw_get_link_width(const void *regs_base) 127 { 128 return (readl(regs_base + PCIE_LINK_STATUS_REG) & 129 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 130 } 131 132 /** 133 * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses 134 * 135 * @pcie: Pointer to the PCI controller state 136 * @index: ATU region index 137 * @type: ATU accsess type 138 * @cpu_addr: the physical address for the translation entry 139 * @pci_addr: the pcie bus address for the translation entry 140 * @size: the size of the translation entry 141 */ 142 static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index, 143 int type, u64 cpu_addr, u64 pci_addr, 144 u32 size) 145 { 146 writel(PCIE_ATU_REGION_OUTBOUND | index, 147 pcie->ctrl_base + PCIE_ATU_VIEWPORT); 148 writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE); 149 writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE); 150 writel(lower_32_bits(cpu_addr + size - 1), 151 pcie->ctrl_base + PCIE_ATU_LIMIT); 152 writel(lower_32_bits(pci_addr), 153 pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); 154 writel(upper_32_bits(pci_addr), 155 pcie->ctrl_base + PCIE_ATU_UPPER_TARGET); 156 writel(type, pcie->ctrl_base + PCIE_ATU_CR1); 157 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2); 158 } 159 160 /** 161 * set_cfg_address() - Configure the PCIe controller config space access 162 * 163 * @pcie: Pointer to the PCI controller state 164 * @d: PCI device to access 165 * @where: Offset in the configuration space 166 * 167 * Configures the PCIe controller to access the configuration space of 168 * a specific PCIe device and returns the address to use for this 169 * access. 170 * 171 * Return: Address that can be used to access the configation space 172 * of the requested device / offset 173 */ 174 static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie, 175 pci_dev_t d, uint where) 176 { 177 uintptr_t va_address; 178 u32 atu_type; 179 180 /* 181 * Region #0 is used for Outbound CFG space access. 182 * Direction = Outbound 183 * Region Index = 0 184 */ 185 186 if (PCI_BUS(d) == (pcie->first_busno + 1)) 187 /* For local bus, change TLP Type field to 4. */ 188 atu_type = PCIE_ATU_TYPE_CFG0; 189 else 190 /* Otherwise, change TLP Type field to 5. */ 191 atu_type = PCIE_ATU_TYPE_CFG1; 192 193 if (PCI_BUS(d) == pcie->first_busno) { 194 /* Accessing root port configuration space. */ 195 va_address = (uintptr_t)pcie->ctrl_base; 196 } else { 197 d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno); 198 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, 199 atu_type, (u64)pcie->cfg_base, 200 d << 8, pcie->cfg_size); 201 va_address = (uintptr_t)pcie->cfg_base; 202 } 203 204 va_address += where & ~0x3; 205 206 return va_address; 207 } 208 209 /** 210 * pcie_dw_addr_valid() - Check for valid bus address 211 * 212 * @d: The PCI device to access 213 * @first_busno: Bus number of the PCIe controller root complex 214 * 215 * Return 1 (true) if the PCI device can be accessed by this controller. 216 * 217 * Return: 1 on valid, 0 on invalid 218 */ 219 static int pcie_dw_addr_valid(pci_dev_t d, int first_busno) 220 { 221 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 222 return 0; 223 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 224 return 0; 225 226 return 1; 227 } 228 229 /** 230 * pcie_dw_mvebu_read_config() - Read from configuration space 231 * 232 * @bus: Pointer to the PCI bus 233 * @bdf: Identifies the PCIe device to access 234 * @offset: The offset into the device's configuration space 235 * @valuep: A pointer at which to store the read value 236 * @size: Indicates the size of access to perform 237 * 238 * Read a value of size @size from offset @offset within the configuration 239 * space of the device identified by the bus, device & function numbers in @bdf 240 * on the PCI bus @bus. 241 * 242 * Return: 0 on success 243 */ 244 static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf, 245 uint offset, ulong *valuep, 246 enum pci_size_t size) 247 { 248 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); 249 uintptr_t va_address; 250 ulong value; 251 252 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", 253 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 254 255 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { 256 debug("- out of range\n"); 257 *valuep = pci_get_ff(size); 258 return 0; 259 } 260 261 va_address = set_cfg_address(pcie, bdf, offset); 262 263 value = readl(va_address); 264 265 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 266 *valuep = pci_conv_32_to_size(value, offset, size); 267 268 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, 269 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 270 pcie->io.bus_start, pcie->io.size); 271 272 return 0; 273 } 274 275 /** 276 * pcie_dw_mvebu_write_config() - Write to configuration space 277 * 278 * @bus: Pointer to the PCI bus 279 * @bdf: Identifies the PCIe device to access 280 * @offset: The offset into the device's configuration space 281 * @value: The value to write 282 * @size: Indicates the size of access to perform 283 * 284 * Write the value @value of size @size from offset @offset within the 285 * configuration space of the device identified by the bus, device & function 286 * numbers in @bdf on the PCI bus @bus. 287 * 288 * Return: 0 on success 289 */ 290 static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf, 291 uint offset, ulong value, 292 enum pci_size_t size) 293 { 294 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); 295 uintptr_t va_address; 296 ulong old; 297 298 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", 299 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 300 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 301 302 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { 303 debug("- out of range\n"); 304 return 0; 305 } 306 307 va_address = set_cfg_address(pcie, bdf, offset); 308 309 old = readl(va_address); 310 value = pci_conv_size_to_32(old, value, offset, size); 311 writel(value, va_address); 312 313 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, 314 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 315 pcie->io.bus_start, pcie->io.size); 316 317 return 0; 318 } 319 320 /** 321 * pcie_dw_configure() - Configure link capabilities and speed 322 * 323 * @regs_base: A pointer to the PCIe controller registers 324 * @cap_speed: The capabilities and speed to configure 325 * 326 * Configure the link capabilities and speed in the PCIe root complex. 327 */ 328 static void pcie_dw_configure(const void *regs_base, u32 cap_speed) 329 { 330 /* 331 * TODO (shadi@marvell.com, sr@denx.de): 332 * Need to read the serdes speed from the dts and according to it 333 * configure the PCIe gen 334 */ 335 336 /* Set link to GEN 3 */ 337 clrsetbits_le32(regs_base + PCIE_LINK_CTL_2, 338 TARGET_LINK_SPEED_MASK, cap_speed); 339 clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY, 340 TARGET_LINK_SPEED_MASK, cap_speed); 341 setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE); 342 } 343 344 /** 345 * is_link_up() - Return the link state 346 * 347 * @regs_base: A pointer to the PCIe controller registers 348 * 349 * Return: 1 (true) for active line and 0 (false) for no link 350 */ 351 static int is_link_up(const void *regs_base) 352 { 353 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; 354 u32 reg; 355 356 reg = readl(regs_base + PCIE_GLOBAL_STATUS); 357 if ((reg & mask) == mask) 358 return 1; 359 360 return 0; 361 } 362 363 /** 364 * wait_link_up() - Wait for the link to come up 365 * 366 * @regs_base: A pointer to the PCIe controller registers 367 * 368 * Return: 1 (true) for active line and 0 (false) for no link (timeout) 369 */ 370 static int wait_link_up(const void *regs_base) 371 { 372 unsigned long timeout; 373 374 timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS; 375 while (!is_link_up(regs_base)) { 376 if (get_timer(0) > timeout) 377 return 0; 378 }; 379 380 return 1; 381 } 382 383 /** 384 * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port 385 * 386 * @regs_base: A pointer to the PCIe controller registers 387 * @cap_speed: The capabilities and speed to configure 388 * 389 * Configure the PCIe controller root complex depending on the 390 * requested link capabilities and speed. 391 * 392 * Return: 1 (true) for active line and 0 (false) for no link 393 */ 394 static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed) 395 { 396 if (!is_link_up(regs_base)) { 397 /* Disable LTSSM state machine to enable configuration */ 398 clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL, 399 PCIE_APP_LTSSM_EN); 400 } 401 402 clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL, 403 PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET, 404 PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET); 405 406 /* Set the PCIe master AXI attributes */ 407 writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC); 408 writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC); 409 410 /* DW pre link configurations */ 411 pcie_dw_configure(regs_base, cap_speed); 412 413 if (!is_link_up(regs_base)) { 414 /* Configuration done. Start LTSSM */ 415 setbits_le32(regs_base + PCIE_GLOBAL_CONTROL, 416 PCIE_APP_LTSSM_EN); 417 } 418 419 /* Check that link was established */ 420 if (!wait_link_up(regs_base)) 421 return 0; 422 423 /* 424 * Link can be established in Gen 1. still need to wait 425 * till MAC nagaotiation is completed 426 */ 427 udelay(100); 428 429 return 1; 430 } 431 432 /** 433 * pcie_dw_set_host_bars() - Configure the host BARs 434 * 435 * @regs_base: A pointer to the PCIe controller registers 436 * 437 * Configure the host BARs of the PCIe controller root port so that 438 * PCI(e) devices may access the system memory. 439 */ 440 static void pcie_dw_set_host_bars(const void *regs_base) 441 { 442 u32 size = gd->ram_size; 443 u64 max_size; 444 u32 reg; 445 u32 bar0; 446 447 /* Verify the maximal BAR size */ 448 reg = readl(regs_base + RESIZABLE_BAR_CAP); 449 max_size = 1ULL << (5 + (reg + (1 << 4))); 450 451 if (size > max_size) { 452 size = max_size; 453 printf("Warning: PCIe BARs can't map all DRAM space\n"); 454 } 455 456 /* Set the BAR base and size towards DDR */ 457 bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf; 458 bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32; 459 writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); 460 461 reg = ((size >> 20) - 1) << 12; 462 writel(size, regs_base + RESIZABLE_BAR_CTL0); 463 } 464 465 /** 466 * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link 467 * 468 * @dev: A pointer to the device being operated on 469 * 470 * Probe for an active link on the PCIe bus and configure the controller 471 * to enable this port. 472 * 473 * Return: 0 on success, else -ENODEV 474 */ 475 static int pcie_dw_mvebu_probe(struct udevice *dev) 476 { 477 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); 478 struct udevice *ctlr = pci_get_controller(dev); 479 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 480 #ifdef CONFIG_DM_GPIO 481 struct gpio_desc reset_gpio; 482 483 gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio, 484 GPIOD_IS_OUT); 485 /* 486 * Issue reset to add-in card trough the dedicated GPIO. 487 * Some boards are connecting the card reset pin to common system 488 * reset wire and others are using separate GPIO port. 489 * In the last case we have to release a reset of the addon card 490 * using this GPIO. 491 */ 492 if (dm_gpio_is_valid(&reset_gpio)) { 493 dm_gpio_set_value(&reset_gpio, 1); 494 mdelay(200); 495 } 496 #else 497 debug("PCIE Reset on GPIO support is missing\n"); 498 #endif /* CONFIG_DM_GPIO */ 499 500 pcie->first_busno = dev->seq; 501 502 /* Don't register host if link is down */ 503 if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) { 504 printf("PCIE-%d: Link down\n", dev->seq); 505 } else { 506 printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq, 507 pcie_dw_get_link_speed(pcie->ctrl_base), 508 pcie_dw_get_link_width(pcie->ctrl_base), 509 hose->first_busno); 510 } 511 512 /* Store the IO and MEM windows settings for future use by the ATU */ 513 pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */ 514 pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */ 515 pcie->io.size = hose->regions[0].size; /* IO size */ 516 517 pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */ 518 pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */ 519 pcie->mem.size = hose->regions[1].size; /* MEM size */ 520 521 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1, 522 PCIE_ATU_TYPE_MEM, pcie->mem.phys_start, 523 pcie->mem.bus_start, pcie->mem.size); 524 525 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ 526 clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION, 527 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16); 528 529 pcie_dw_set_host_bars(pcie->ctrl_base); 530 531 return 0; 532 } 533 534 /** 535 * pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state 536 * 537 * @dev: A pointer to the device being operated on 538 * 539 * Translate relevant data from the device tree pertaining to device @dev into 540 * state that the driver will later make use of. This state is stored in the 541 * device's private data structure. 542 * 543 * Return: 0 on success, else -EINVAL 544 */ 545 static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev) 546 { 547 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); 548 549 /* Get the controller base address */ 550 pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0); 551 if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE) 552 return -EINVAL; 553 554 /* Get the config space base address and size */ 555 pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, 556 &pcie->cfg_size); 557 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) 558 return -EINVAL; 559 560 return 0; 561 } 562 563 static const struct dm_pci_ops pcie_dw_mvebu_ops = { 564 .read_config = pcie_dw_mvebu_read_config, 565 .write_config = pcie_dw_mvebu_write_config, 566 }; 567 568 static const struct udevice_id pcie_dw_mvebu_ids[] = { 569 { .compatible = "marvell,armada8k-pcie" }, 570 { } 571 }; 572 573 U_BOOT_DRIVER(pcie_dw_mvebu) = { 574 .name = "pcie_dw_mvebu", 575 .id = UCLASS_PCI, 576 .of_match = pcie_dw_mvebu_ids, 577 .ops = &pcie_dw_mvebu_ops, 578 .ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata, 579 .probe = pcie_dw_mvebu_probe, 580 .priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu), 581 }; 582