1 /* 2 * Copyright (c) 2010, CompuLab, Ltd. 3 * Author: Mike Rapoport <mike@compulab.co.il> 4 * 5 * Based on NVIDIA PCIe driver 6 * Copyright (c) 2008-2009, NVIDIA Corporation. 7 * 8 * Copyright (c) 2013-2014, NVIDIA Corporation. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #define DEBUG 14 #define pr_fmt(fmt) "tegra-pcie: " fmt 15 16 #include <common.h> 17 #include <errno.h> 18 #include <fdtdec.h> 19 #include <malloc.h> 20 #include <pci.h> 21 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 25 #include <asm/arch/clock.h> 26 #include <asm/arch/powergate.h> 27 #include <asm/arch-tegra/xusb-padctl.h> 28 29 #include <linux/list.h> 30 31 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define AFI_AXI_BAR0_SZ 0x00 36 #define AFI_AXI_BAR1_SZ 0x04 37 #define AFI_AXI_BAR2_SZ 0x08 38 #define AFI_AXI_BAR3_SZ 0x0c 39 #define AFI_AXI_BAR4_SZ 0x10 40 #define AFI_AXI_BAR5_SZ 0x14 41 42 #define AFI_AXI_BAR0_START 0x18 43 #define AFI_AXI_BAR1_START 0x1c 44 #define AFI_AXI_BAR2_START 0x20 45 #define AFI_AXI_BAR3_START 0x24 46 #define AFI_AXI_BAR4_START 0x28 47 #define AFI_AXI_BAR5_START 0x2c 48 49 #define AFI_FPCI_BAR0 0x30 50 #define AFI_FPCI_BAR1 0x34 51 #define AFI_FPCI_BAR2 0x38 52 #define AFI_FPCI_BAR3 0x3c 53 #define AFI_FPCI_BAR4 0x40 54 #define AFI_FPCI_BAR5 0x44 55 56 #define AFI_CACHE_BAR0_SZ 0x48 57 #define AFI_CACHE_BAR0_ST 0x4c 58 #define AFI_CACHE_BAR1_SZ 0x50 59 #define AFI_CACHE_BAR1_ST 0x54 60 61 #define AFI_MSI_BAR_SZ 0x60 62 #define AFI_MSI_FPCI_BAR_ST 0x64 63 #define AFI_MSI_AXI_BAR_ST 0x68 64 65 #define AFI_CONFIGURATION 0xac 66 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 67 68 #define AFI_FPCI_ERROR_MASKS 0xb0 69 70 #define AFI_INTR_MASK 0xb4 71 #define AFI_INTR_MASK_INT_MASK (1 << 0) 72 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 73 74 #define AFI_SM_INTR_ENABLE 0xc4 75 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 76 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 77 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 78 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 79 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 80 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 81 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 82 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 83 84 #define AFI_AFI_INTR_ENABLE 0xc8 85 #define AFI_INTR_EN_INI_SLVERR (1 << 0) 86 #define AFI_INTR_EN_INI_DECERR (1 << 1) 87 #define AFI_INTR_EN_TGT_SLVERR (1 << 2) 88 #define AFI_INTR_EN_TGT_DECERR (1 << 3) 89 #define AFI_INTR_EN_TGT_WRERR (1 << 4) 90 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) 91 #define AFI_INTR_EN_AXI_DECERR (1 << 6) 92 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) 93 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) 94 95 #define AFI_PCIE_CONFIG 0x0f8 96 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 97 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe 98 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 99 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) 100 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) 101 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) 102 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) 103 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) 104 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) 105 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) 106 107 #define AFI_FUSE 0x104 108 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 109 110 #define AFI_PEX0_CTRL 0x110 111 #define AFI_PEX1_CTRL 0x118 112 #define AFI_PEX2_CTRL 0x128 113 #define AFI_PEX_CTRL_RST (1 << 0) 114 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 115 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 116 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 117 118 #define AFI_PLLE_CONTROL 0x160 119 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 120 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 121 122 #define AFI_PEXBIAS_CTRL_0 0x168 123 124 #define PADS_CTL_SEL 0x0000009C 125 126 #define PADS_CTL 0x000000A0 127 #define PADS_CTL_IDDQ_1L (1 << 0) 128 #define PADS_CTL_TX_DATA_EN_1L (1 << 6) 129 #define PADS_CTL_RX_DATA_EN_1L (1 << 10) 130 131 #define PADS_PLL_CTL_TEGRA20 0x000000B8 132 #define PADS_PLL_CTL_TEGRA30 0x000000B4 133 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) 134 #define PADS_PLL_CTL_LOCKDET (0x1 << 8) 135 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) 136 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) 137 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) 138 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) 139 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) 140 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) 141 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) 142 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) 143 144 #define PADS_REFCLK_CFG0 0x000000C8 145 #define PADS_REFCLK_CFG1 0x000000CC 146 147 /* 148 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit 149 * entries, one entry per PCIe port. These field definitions and desired 150 * values aren't in the TRM, but do come from NVIDIA. 151 */ 152 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ 153 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 154 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ 155 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ 156 157 /* Default value provided by HW engineering is 0xfa5c */ 158 #define PADS_REFCLK_CFG_VALUE \ 159 ( \ 160 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ 161 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ 162 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ 163 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ 164 ) 165 166 #define RP_VEND_XP 0x00000F00 167 #define RP_VEND_XP_DL_UP (1 << 30) 168 169 #define RP_VEND_CTL2 0x00000FA8 170 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) 171 172 #define RP_PRIV_MISC 0x00000FE0 173 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 174 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 175 176 #define RP_LINK_CONTROL_STATUS 0x00000090 177 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 178 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 179 180 struct tegra_pcie; 181 182 struct tegra_pcie_port { 183 struct tegra_pcie *pcie; 184 185 struct fdt_resource regs; 186 unsigned int num_lanes; 187 unsigned int index; 188 189 struct list_head list; 190 }; 191 192 struct tegra_pcie_soc { 193 unsigned int num_ports; 194 unsigned long pads_pll_ctl; 195 unsigned long tx_ref_sel; 196 bool has_pex_clkreq_en; 197 bool has_pex_bias_ctrl; 198 bool has_cml_clk; 199 bool has_gen2; 200 bool force_pca_enable; 201 }; 202 203 struct tegra_pcie { 204 struct pci_controller hose; 205 206 struct fdt_resource pads; 207 struct fdt_resource afi; 208 struct fdt_resource cs; 209 210 struct fdt_resource prefetch; 211 struct fdt_resource mem; 212 struct fdt_resource io; 213 214 struct list_head ports; 215 unsigned long xbar; 216 217 const struct tegra_pcie_soc *soc; 218 struct tegra_xusb_phy *phy; 219 }; 220 221 static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose) 222 { 223 return container_of(hose, struct tegra_pcie, hose); 224 } 225 226 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, 227 unsigned long offset) 228 { 229 writel(value, pcie->afi.start + offset); 230 } 231 232 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) 233 { 234 return readl(pcie->afi.start + offset); 235 } 236 237 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, 238 unsigned long offset) 239 { 240 writel(value, pcie->pads.start + offset); 241 } 242 243 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) 244 { 245 return readl(pcie->pads.start + offset); 246 } 247 248 static unsigned long rp_readl(struct tegra_pcie_port *port, 249 unsigned long offset) 250 { 251 return readl(port->regs.start + offset); 252 } 253 254 static void rp_writel(struct tegra_pcie_port *port, unsigned long value, 255 unsigned long offset) 256 { 257 writel(value, port->regs.start + offset); 258 } 259 260 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) 261 { 262 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | 263 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | 264 (where & 0xfc); 265 } 266 267 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, 268 int where, unsigned long *address) 269 { 270 unsigned int bus = PCI_BUS(bdf); 271 272 if (bus == 0) { 273 unsigned int dev = PCI_DEV(bdf); 274 struct tegra_pcie_port *port; 275 276 list_for_each_entry(port, &pcie->ports, list) { 277 if (port->index + 1 == dev) { 278 *address = port->regs.start + (where & ~3); 279 return 0; 280 } 281 } 282 } else { 283 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); 284 return 0; 285 } 286 287 return -1; 288 } 289 290 static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf, 291 int where, u32 *value) 292 { 293 struct tegra_pcie *pcie = to_tegra_pcie(hose); 294 unsigned long address; 295 int err; 296 297 err = tegra_pcie_conf_address(pcie, bdf, where, &address); 298 if (err < 0) { 299 *value = 0xffffffff; 300 return 1; 301 } 302 303 *value = readl(address); 304 305 /* fixup root port class */ 306 if (PCI_BUS(bdf) == 0) { 307 if (where == PCI_CLASS_REVISION) { 308 *value &= ~0x00ff0000; 309 *value |= PCI_CLASS_BRIDGE_PCI << 16; 310 } 311 } 312 313 return 0; 314 } 315 316 static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf, 317 int where, u32 value) 318 { 319 struct tegra_pcie *pcie = to_tegra_pcie(hose); 320 unsigned long address; 321 int err; 322 323 err = tegra_pcie_conf_address(pcie, bdf, where, &address); 324 if (err < 0) 325 return 1; 326 327 writel(value, address); 328 329 return 0; 330 } 331 332 static int tegra_pcie_port_parse_dt(const void *fdt, int node, 333 struct tegra_pcie_port *port) 334 { 335 const u32 *addr; 336 int len; 337 338 addr = fdt_getprop(fdt, node, "assigned-addresses", &len); 339 if (!addr) { 340 error("property \"assigned-addresses\" not found"); 341 return -FDT_ERR_NOTFOUND; 342 } 343 344 port->regs.start = fdt32_to_cpu(addr[2]); 345 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); 346 347 return 0; 348 } 349 350 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, 351 unsigned long *xbar) 352 { 353 enum fdt_compat_id id = fdtdec_lookup(fdt, node); 354 355 switch (id) { 356 case COMPAT_NVIDIA_TEGRA20_PCIE: 357 switch (lanes) { 358 case 0x00000004: 359 debug("single-mode configuration\n"); 360 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; 361 return 0; 362 363 case 0x00000202: 364 debug("dual-mode configuration\n"); 365 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; 366 return 0; 367 } 368 break; 369 370 case COMPAT_NVIDIA_TEGRA30_PCIE: 371 switch (lanes) { 372 case 0x00000204: 373 debug("4x1, 2x1 configuration\n"); 374 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; 375 return 0; 376 377 case 0x00020202: 378 debug("2x3 configuration\n"); 379 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; 380 return 0; 381 382 case 0x00010104: 383 debug("4x1, 1x2 configuration\n"); 384 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; 385 return 0; 386 } 387 break; 388 389 case COMPAT_NVIDIA_TEGRA124_PCIE: 390 case COMPAT_NVIDIA_TEGRA210_PCIE: 391 switch (lanes) { 392 case 0x0000104: 393 debug("4x1, 1x1 configuration\n"); 394 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; 395 return 0; 396 397 case 0x0000102: 398 debug("2x1, 1x1 configuration\n"); 399 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; 400 return 0; 401 } 402 break; 403 404 default: 405 break; 406 } 407 408 return -FDT_ERR_NOTFOUND; 409 } 410 411 static int tegra_pcie_parse_dt_ranges(const void *fdt, int node, 412 struct tegra_pcie *pcie) 413 { 414 int parent, na_parent, na_pcie, ns_pcie; 415 const u32 *ptr, *end; 416 int len; 417 418 parent = fdt_parent_offset(fdt, node); 419 if (parent < 0) { 420 error("Can't find PCI parent node\n"); 421 return -FDT_ERR_NOTFOUND; 422 } 423 424 na_parent = fdt_address_cells(fdt, parent); 425 if (na_parent < 1) { 426 error("bad #address-cells for PCIE parent\n"); 427 return -FDT_ERR_NOTFOUND; 428 } 429 430 na_pcie = fdt_address_cells(fdt, node); 431 if (na_pcie < 1) { 432 error("bad #address-cells for PCIE\n"); 433 return -FDT_ERR_NOTFOUND; 434 } 435 436 ns_pcie = fdt_size_cells(fdt, node); 437 if (ns_pcie < 1) { 438 error("bad #size-cells for PCIE\n"); 439 return -FDT_ERR_NOTFOUND; 440 } 441 442 ptr = fdt_getprop(fdt, node, "ranges", &len); 443 if (!ptr) { 444 error("missing \"ranges\" property"); 445 return -FDT_ERR_NOTFOUND; 446 } 447 448 end = ptr + len / 4; 449 450 while (ptr < end) { 451 struct fdt_resource *res = NULL; 452 u32 space = fdt32_to_cpu(*ptr); 453 454 switch ((space >> 24) & 0x3) { 455 case 0x01: 456 res = &pcie->io; 457 break; 458 459 case 0x02: /* 32 bit */ 460 case 0x03: /* 64 bit */ 461 if (space & (1 << 30)) 462 res = &pcie->prefetch; 463 else 464 res = &pcie->mem; 465 466 break; 467 } 468 469 if (res) { 470 int start_low = na_pcie + (na_parent - 1); 471 int size_low = na_pcie + na_parent + (ns_pcie - 1); 472 res->start = fdt32_to_cpu(ptr[start_low]); 473 res->end = res->start + fdt32_to_cpu(ptr[size_low]); 474 } 475 476 ptr += na_pcie + na_parent + ns_pcie; 477 } 478 479 debug("PCI regions:\n"); 480 debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end); 481 debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start, 482 &pcie->mem.end); 483 debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start, 484 &pcie->prefetch.end); 485 486 return 0; 487 } 488 489 static int tegra_pcie_parse_port_info(const void *fdt, int node, 490 unsigned int *index, 491 unsigned int *lanes) 492 { 493 struct fdt_pci_addr addr; 494 int err; 495 496 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0); 497 if (err < 0) { 498 error("failed to parse \"nvidia,num-lanes\" property"); 499 return err; 500 } 501 502 *lanes = err; 503 504 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr); 505 if (err < 0) { 506 error("failed to parse \"reg\" property"); 507 return err; 508 } 509 510 *index = PCI_DEV(addr.phys_hi) - 1; 511 512 return 0; 513 } 514 515 static int tegra_pcie_parse_dt(const void *fdt, int node, 516 struct tegra_pcie *pcie) 517 { 518 int err, subnode; 519 u32 lanes = 0; 520 521 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads", 522 &pcie->pads); 523 if (err < 0) { 524 error("resource \"pads\" not found"); 525 return err; 526 } 527 528 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi", 529 &pcie->afi); 530 if (err < 0) { 531 error("resource \"afi\" not found"); 532 return err; 533 } 534 535 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs", 536 &pcie->cs); 537 if (err < 0) { 538 error("resource \"cs\" not found"); 539 return err; 540 } 541 542 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); 543 if (pcie->phy) { 544 err = tegra_xusb_phy_prepare(pcie->phy); 545 if (err < 0) { 546 error("failed to prepare PHY: %d", err); 547 return err; 548 } 549 } 550 551 err = tegra_pcie_parse_dt_ranges(fdt, node, pcie); 552 if (err < 0) { 553 error("failed to parse \"ranges\" property"); 554 return err; 555 } 556 557 fdt_for_each_subnode(fdt, subnode, node) { 558 unsigned int index = 0, num_lanes = 0; 559 struct tegra_pcie_port *port; 560 561 err = tegra_pcie_parse_port_info(fdt, subnode, &index, 562 &num_lanes); 563 if (err < 0) { 564 error("failed to obtain root port info"); 565 continue; 566 } 567 568 lanes |= num_lanes << (index << 3); 569 570 if (!fdtdec_get_is_enabled(fdt, subnode)) 571 continue; 572 573 port = malloc(sizeof(*port)); 574 if (!port) 575 continue; 576 577 memset(port, 0, sizeof(*port)); 578 port->num_lanes = num_lanes; 579 port->index = index; 580 581 err = tegra_pcie_port_parse_dt(fdt, subnode, port); 582 if (err < 0) { 583 free(port); 584 continue; 585 } 586 587 list_add_tail(&port->list, &pcie->ports); 588 port->pcie = pcie; 589 } 590 591 err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar); 592 if (err < 0) { 593 error("invalid lane configuration"); 594 return err; 595 } 596 597 return 0; 598 } 599 600 int __weak tegra_pcie_board_init(void) 601 { 602 return 0; 603 } 604 605 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 606 { 607 const struct tegra_pcie_soc *soc = pcie->soc; 608 unsigned long value; 609 int err; 610 611 /* reset PCIEXCLK logic, AFI controller and PCIe controller */ 612 reset_set_enable(PERIPH_ID_PCIEXCLK, 1); 613 reset_set_enable(PERIPH_ID_AFI, 1); 614 reset_set_enable(PERIPH_ID_PCIE, 1); 615 616 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 617 if (err < 0) { 618 error("failed to power off PCIe partition: %d", err); 619 return err; 620 } 621 622 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, 623 PERIPH_ID_PCIE); 624 if (err < 0) { 625 error("failed to power up PCIe partition: %d", err); 626 return err; 627 } 628 629 /* take AFI controller out of reset */ 630 reset_set_enable(PERIPH_ID_AFI, 0); 631 632 /* enable AFI clock */ 633 clock_enable(PERIPH_ID_AFI); 634 635 if (soc->has_cml_clk) { 636 /* enable CML clock */ 637 value = readl(NV_PA_CLK_RST_BASE + 0x48c); 638 value |= (1 << 0); 639 value &= ~(1 << 1); 640 writel(value, NV_PA_CLK_RST_BASE + 0x48c); 641 } 642 643 err = tegra_plle_enable(); 644 if (err < 0) { 645 error("failed to enable PLLE: %d\n", err); 646 return err; 647 } 648 649 return 0; 650 } 651 652 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) 653 { 654 const struct tegra_pcie_soc *soc = pcie->soc; 655 unsigned long start = get_timer(0); 656 u32 value; 657 658 while (get_timer(start) < timeout) { 659 value = pads_readl(pcie, soc->pads_pll_ctl); 660 if (value & PADS_PLL_CTL_LOCKDET) 661 return 0; 662 } 663 664 return -ETIMEDOUT; 665 } 666 667 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 668 { 669 const struct tegra_pcie_soc *soc = pcie->soc; 670 u32 value; 671 int err; 672 673 /* initialize internal PHY, enable up to 16 PCIe lanes */ 674 pads_writel(pcie, 0, PADS_CTL_SEL); 675 676 /* override IDDQ to 1 on all 4 lanes */ 677 value = pads_readl(pcie, PADS_CTL); 678 value |= PADS_CTL_IDDQ_1L; 679 pads_writel(pcie, value, PADS_CTL); 680 681 /* 682 * Set up PHY PLL inputs select PLLE output as refclock, set TX 683 * ref sel to div10 (not div5). 684 */ 685 value = pads_readl(pcie, soc->pads_pll_ctl); 686 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); 687 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; 688 pads_writel(pcie, value, soc->pads_pll_ctl); 689 690 /* reset PLL */ 691 value = pads_readl(pcie, soc->pads_pll_ctl); 692 value &= ~PADS_PLL_CTL_RST_B4SM; 693 pads_writel(pcie, value, soc->pads_pll_ctl); 694 695 udelay(20); 696 697 /* take PLL out of reset */ 698 value = pads_readl(pcie, soc->pads_pll_ctl); 699 value |= PADS_PLL_CTL_RST_B4SM; 700 pads_writel(pcie, value, soc->pads_pll_ctl); 701 702 /* configure the reference clock driver */ 703 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); 704 pads_writel(pcie, value, PADS_REFCLK_CFG0); 705 706 if (soc->num_ports > 2) 707 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); 708 709 /* wait for the PLL to lock */ 710 err = tegra_pcie_pll_wait(pcie, 500); 711 if (err < 0) { 712 error("PLL failed to lock: %d", err); 713 return err; 714 } 715 716 /* turn off IDDQ override */ 717 value = pads_readl(pcie, PADS_CTL); 718 value &= ~PADS_CTL_IDDQ_1L; 719 pads_writel(pcie, value, PADS_CTL); 720 721 /* enable TX/RX data */ 722 value = pads_readl(pcie, PADS_CTL); 723 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; 724 pads_writel(pcie, value, PADS_CTL); 725 726 return 0; 727 } 728 729 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) 730 { 731 const struct tegra_pcie_soc *soc = pcie->soc; 732 struct tegra_pcie_port *port; 733 u32 value; 734 int err; 735 736 if (pcie->phy) { 737 value = afi_readl(pcie, AFI_PLLE_CONTROL); 738 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 739 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 740 afi_writel(pcie, value, AFI_PLLE_CONTROL); 741 } 742 743 if (soc->has_pex_bias_ctrl) 744 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); 745 746 value = afi_readl(pcie, AFI_PCIE_CONFIG); 747 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 748 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; 749 750 list_for_each_entry(port, &pcie->ports, list) 751 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); 752 753 afi_writel(pcie, value, AFI_PCIE_CONFIG); 754 755 value = afi_readl(pcie, AFI_FUSE); 756 757 if (soc->has_gen2) 758 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 759 else 760 value |= AFI_FUSE_PCIE_T0_GEN2_DIS; 761 762 afi_writel(pcie, value, AFI_FUSE); 763 764 if (pcie->phy) 765 err = tegra_xusb_phy_enable(pcie->phy); 766 else 767 err = tegra_pcie_phy_enable(pcie); 768 769 if (err < 0) { 770 error("failed to power on PHY: %d\n", err); 771 return err; 772 } 773 774 /* take the PCIEXCLK logic out of reset */ 775 reset_set_enable(PERIPH_ID_PCIEXCLK, 0); 776 777 /* finally enable PCIe */ 778 value = afi_readl(pcie, AFI_CONFIGURATION); 779 value |= AFI_CONFIGURATION_EN_FPCI; 780 afi_writel(pcie, value, AFI_CONFIGURATION); 781 782 /* disable all interrupts */ 783 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); 784 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); 785 afi_writel(pcie, 0, AFI_INTR_MASK); 786 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); 787 788 return 0; 789 } 790 791 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) 792 { 793 unsigned long fpci, axi, size; 794 795 /* BAR 0: type 1 extended configuration space */ 796 fpci = 0xfe100000; 797 size = fdt_resource_size(&pcie->cs); 798 axi = pcie->cs.start; 799 800 afi_writel(pcie, axi, AFI_AXI_BAR0_START); 801 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); 802 afi_writel(pcie, fpci, AFI_FPCI_BAR0); 803 804 /* BAR 1: downstream I/O */ 805 fpci = 0xfdfc0000; 806 size = fdt_resource_size(&pcie->io); 807 axi = pcie->io.start; 808 809 afi_writel(pcie, axi, AFI_AXI_BAR1_START); 810 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); 811 afi_writel(pcie, fpci, AFI_FPCI_BAR1); 812 813 /* BAR 2: prefetchable memory */ 814 fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; 815 size = fdt_resource_size(&pcie->prefetch); 816 axi = pcie->prefetch.start; 817 818 afi_writel(pcie, axi, AFI_AXI_BAR2_START); 819 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); 820 afi_writel(pcie, fpci, AFI_FPCI_BAR2); 821 822 /* BAR 3: non-prefetchable memory */ 823 fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; 824 size = fdt_resource_size(&pcie->mem); 825 axi = pcie->mem.start; 826 827 afi_writel(pcie, axi, AFI_AXI_BAR3_START); 828 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); 829 afi_writel(pcie, fpci, AFI_FPCI_BAR3); 830 831 /* NULL out the remaining BARs as they are not used */ 832 afi_writel(pcie, 0, AFI_AXI_BAR4_START); 833 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); 834 afi_writel(pcie, 0, AFI_FPCI_BAR4); 835 836 afi_writel(pcie, 0, AFI_AXI_BAR5_START); 837 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); 838 afi_writel(pcie, 0, AFI_FPCI_BAR5); 839 840 /* map all upstream transactions as uncached */ 841 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); 842 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); 843 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); 844 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); 845 846 /* MSI translations are setup only when needed */ 847 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); 848 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 849 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); 850 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 851 } 852 853 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) 854 { 855 unsigned long ret = 0; 856 857 switch (port->index) { 858 case 0: 859 ret = AFI_PEX0_CTRL; 860 break; 861 862 case 1: 863 ret = AFI_PEX1_CTRL; 864 break; 865 866 case 2: 867 ret = AFI_PEX2_CTRL; 868 break; 869 } 870 871 return ret; 872 } 873 874 static void tegra_pcie_port_reset(struct tegra_pcie_port *port) 875 { 876 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 877 unsigned long value; 878 879 /* pulse reset signel */ 880 value = afi_readl(port->pcie, ctrl); 881 value &= ~AFI_PEX_CTRL_RST; 882 afi_writel(port->pcie, value, ctrl); 883 884 udelay(2000); 885 886 value = afi_readl(port->pcie, ctrl); 887 value |= AFI_PEX_CTRL_RST; 888 afi_writel(port->pcie, value, ctrl); 889 } 890 891 static void tegra_pcie_port_enable(struct tegra_pcie_port *port) 892 { 893 const struct tegra_pcie_soc *soc = port->pcie->soc; 894 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 895 unsigned long value; 896 897 /* enable reference clock */ 898 value = afi_readl(port->pcie, ctrl); 899 value |= AFI_PEX_CTRL_REFCLK_EN; 900 901 if (port->pcie->soc->has_pex_clkreq_en) 902 value |= AFI_PEX_CTRL_CLKREQ_EN; 903 904 value |= AFI_PEX_CTRL_OVERRIDE_EN; 905 906 afi_writel(port->pcie, value, ctrl); 907 908 tegra_pcie_port_reset(port); 909 910 if (soc->force_pca_enable) { 911 value = rp_readl(port, RP_VEND_CTL2); 912 value |= RP_VEND_CTL2_PCA_ENABLE; 913 rp_writel(port, value, RP_VEND_CTL2); 914 } 915 } 916 917 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) 918 { 919 unsigned int retries = 3; 920 unsigned long value; 921 922 value = rp_readl(port, RP_PRIV_MISC); 923 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 924 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 925 rp_writel(port, value, RP_PRIV_MISC); 926 927 do { 928 unsigned int timeout = 200; 929 930 do { 931 value = rp_readl(port, RP_VEND_XP); 932 if (value & RP_VEND_XP_DL_UP) 933 break; 934 935 udelay(2000); 936 } while (--timeout); 937 938 if (!timeout) { 939 debug("link %u down, retrying\n", port->index); 940 goto retry; 941 } 942 943 timeout = 200; 944 945 do { 946 value = rp_readl(port, RP_LINK_CONTROL_STATUS); 947 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 948 return true; 949 950 udelay(2000); 951 } while (--timeout); 952 953 retry: 954 tegra_pcie_port_reset(port); 955 } while (--retries); 956 957 return false; 958 } 959 960 static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 961 { 962 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 963 unsigned long value; 964 965 /* assert port reset */ 966 value = afi_readl(port->pcie, ctrl); 967 value &= ~AFI_PEX_CTRL_RST; 968 afi_writel(port->pcie, value, ctrl); 969 970 /* disable reference clock */ 971 value = afi_readl(port->pcie, ctrl); 972 value &= ~AFI_PEX_CTRL_REFCLK_EN; 973 afi_writel(port->pcie, value, ctrl); 974 } 975 976 static void tegra_pcie_port_free(struct tegra_pcie_port *port) 977 { 978 list_del(&port->list); 979 free(port); 980 } 981 982 static int tegra_pcie_enable(struct tegra_pcie *pcie) 983 { 984 struct tegra_pcie_port *port, *tmp; 985 986 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 987 debug("probing port %u, using %u lanes\n", port->index, 988 port->num_lanes); 989 990 tegra_pcie_port_enable(port); 991 992 if (tegra_pcie_port_check_link(port)) 993 continue; 994 995 debug("link %u down, ignoring\n", port->index); 996 997 tegra_pcie_port_disable(port); 998 tegra_pcie_port_free(port); 999 } 1000 1001 return 0; 1002 } 1003 1004 static const struct tegra_pcie_soc tegra20_pcie_soc = { 1005 .num_ports = 2, 1006 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, 1007 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, 1008 .has_pex_clkreq_en = false, 1009 .has_pex_bias_ctrl = false, 1010 .has_cml_clk = false, 1011 .has_gen2 = false, 1012 .force_pca_enable = false, 1013 }; 1014 1015 static const struct tegra_pcie_soc tegra30_pcie_soc = { 1016 .num_ports = 3, 1017 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1018 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1019 .has_pex_clkreq_en = true, 1020 .has_pex_bias_ctrl = true, 1021 .has_cml_clk = true, 1022 .has_gen2 = false, 1023 .force_pca_enable = false, 1024 }; 1025 1026 static const struct tegra_pcie_soc tegra124_pcie_soc = { 1027 .num_ports = 2, 1028 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1029 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1030 .has_pex_clkreq_en = true, 1031 .has_pex_bias_ctrl = true, 1032 .has_cml_clk = true, 1033 .has_gen2 = true, 1034 .force_pca_enable = false, 1035 }; 1036 1037 static const struct tegra_pcie_soc tegra210_pcie_soc = { 1038 .num_ports = 2, 1039 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1040 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1041 .has_pex_clkreq_en = true, 1042 .has_pex_bias_ctrl = true, 1043 .has_cml_clk = true, 1044 .has_gen2 = true, 1045 .force_pca_enable = true, 1046 }; 1047 1048 static int process_nodes(const void *fdt, int nodes[], unsigned int count) 1049 { 1050 unsigned int i; 1051 uint64_t dram_end; 1052 uint32_t pci_dram_size; 1053 1054 /* Clip PCI-accessible DRAM to 32-bits */ 1055 dram_end = ((uint64_t)NV_PA_SDRAM_BASE) + gd->ram_size; 1056 if (dram_end > 0x100000000) 1057 dram_end = 0x100000000; 1058 pci_dram_size = dram_end - NV_PA_SDRAM_BASE; 1059 1060 for (i = 0; i < count; i++) { 1061 const struct tegra_pcie_soc *soc; 1062 struct tegra_pcie *pcie; 1063 enum fdt_compat_id id; 1064 int err; 1065 1066 if (!fdtdec_get_is_enabled(fdt, nodes[i])) 1067 continue; 1068 1069 id = fdtdec_lookup(fdt, nodes[i]); 1070 switch (id) { 1071 case COMPAT_NVIDIA_TEGRA20_PCIE: 1072 soc = &tegra20_pcie_soc; 1073 break; 1074 1075 case COMPAT_NVIDIA_TEGRA30_PCIE: 1076 soc = &tegra30_pcie_soc; 1077 break; 1078 1079 case COMPAT_NVIDIA_TEGRA124_PCIE: 1080 soc = &tegra124_pcie_soc; 1081 break; 1082 1083 case COMPAT_NVIDIA_TEGRA210_PCIE: 1084 soc = &tegra210_pcie_soc; 1085 break; 1086 1087 default: 1088 error("unsupported compatible: %s", 1089 fdtdec_get_compatible(id)); 1090 continue; 1091 } 1092 1093 pcie = malloc(sizeof(*pcie)); 1094 if (!pcie) { 1095 error("failed to allocate controller"); 1096 continue; 1097 } 1098 1099 memset(pcie, 0, sizeof(*pcie)); 1100 pcie->soc = soc; 1101 1102 INIT_LIST_HEAD(&pcie->ports); 1103 1104 err = tegra_pcie_parse_dt(fdt, nodes[i], pcie); 1105 if (err < 0) { 1106 free(pcie); 1107 continue; 1108 } 1109 1110 err = tegra_pcie_power_on(pcie); 1111 if (err < 0) { 1112 error("failed to power on"); 1113 continue; 1114 } 1115 1116 err = tegra_pcie_enable_controller(pcie); 1117 if (err < 0) { 1118 error("failed to enable controller"); 1119 continue; 1120 } 1121 1122 tegra_pcie_setup_translations(pcie); 1123 1124 err = tegra_pcie_enable(pcie); 1125 if (err < 0) { 1126 error("failed to enable PCIe"); 1127 continue; 1128 } 1129 1130 pcie->hose.first_busno = 0; 1131 pcie->hose.current_busno = 0; 1132 pcie->hose.last_busno = 0; 1133 1134 pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE, 1135 NV_PA_SDRAM_BASE, pci_dram_size, 1136 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 1137 1138 pci_set_region(&pcie->hose.regions[1], pcie->io.start, 1139 pcie->io.start, fdt_resource_size(&pcie->io), 1140 PCI_REGION_IO); 1141 1142 pci_set_region(&pcie->hose.regions[2], pcie->mem.start, 1143 pcie->mem.start, fdt_resource_size(&pcie->mem), 1144 PCI_REGION_MEM); 1145 1146 pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start, 1147 pcie->prefetch.start, 1148 fdt_resource_size(&pcie->prefetch), 1149 PCI_REGION_MEM | PCI_REGION_PREFETCH); 1150 1151 pcie->hose.region_count = 4; 1152 1153 pci_set_ops(&pcie->hose, 1154 pci_hose_read_config_byte_via_dword, 1155 pci_hose_read_config_word_via_dword, 1156 tegra_pcie_read_conf, 1157 pci_hose_write_config_byte_via_dword, 1158 pci_hose_write_config_word_via_dword, 1159 tegra_pcie_write_conf); 1160 1161 pci_register_hose(&pcie->hose); 1162 1163 #ifdef CONFIG_PCI_SCAN_SHOW 1164 printf("PCI: Enumerating devices...\n"); 1165 printf("---------------------------------------\n"); 1166 printf(" Device ID Description\n"); 1167 printf(" ------ -- -----------\n"); 1168 #endif 1169 1170 pcie->hose.last_busno = pci_hose_scan(&pcie->hose); 1171 } 1172 1173 return 0; 1174 } 1175 1176 void pci_init_board(void) 1177 { 1178 const void *fdt = gd->fdt_blob; 1179 int count, nodes[1]; 1180 1181 tegra_pcie_board_init(); 1182 1183 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1184 COMPAT_NVIDIA_TEGRA210_PCIE, 1185 nodes, ARRAY_SIZE(nodes)); 1186 if (process_nodes(fdt, nodes, count)) 1187 return; 1188 1189 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1190 COMPAT_NVIDIA_TEGRA124_PCIE, 1191 nodes, ARRAY_SIZE(nodes)); 1192 if (process_nodes(fdt, nodes, count)) 1193 return; 1194 1195 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1196 COMPAT_NVIDIA_TEGRA30_PCIE, 1197 nodes, ARRAY_SIZE(nodes)); 1198 if (process_nodes(fdt, nodes, count)) 1199 return; 1200 1201 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1202 COMPAT_NVIDIA_TEGRA20_PCIE, 1203 nodes, ARRAY_SIZE(nodes)); 1204 if (process_nodes(fdt, nodes, count)) 1205 return; 1206 } 1207 1208 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 1209 { 1210 if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0) 1211 return 1; 1212 1213 return 0; 1214 } 1215