1 /* 2 * Copyright (c) 2010, CompuLab, Ltd. 3 * Author: Mike Rapoport <mike@compulab.co.il> 4 * 5 * Based on NVIDIA PCIe driver 6 * Copyright (c) 2008-2009, NVIDIA Corporation. 7 * 8 * Copyright (c) 2013-2014, NVIDIA Corporation. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #define pr_fmt(fmt) "tegra-pcie: " fmt 14 15 #include <common.h> 16 #include <dm.h> 17 #include <errno.h> 18 #include <fdtdec.h> 19 #include <malloc.h> 20 #include <pci.h> 21 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 25 #include <asm/arch/clock.h> 26 #include <asm/arch/powergate.h> 27 #include <asm/arch-tegra/xusb-padctl.h> 28 29 #include <linux/list.h> 30 31 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define AFI_AXI_BAR0_SZ 0x00 36 #define AFI_AXI_BAR1_SZ 0x04 37 #define AFI_AXI_BAR2_SZ 0x08 38 #define AFI_AXI_BAR3_SZ 0x0c 39 #define AFI_AXI_BAR4_SZ 0x10 40 #define AFI_AXI_BAR5_SZ 0x14 41 42 #define AFI_AXI_BAR0_START 0x18 43 #define AFI_AXI_BAR1_START 0x1c 44 #define AFI_AXI_BAR2_START 0x20 45 #define AFI_AXI_BAR3_START 0x24 46 #define AFI_AXI_BAR4_START 0x28 47 #define AFI_AXI_BAR5_START 0x2c 48 49 #define AFI_FPCI_BAR0 0x30 50 #define AFI_FPCI_BAR1 0x34 51 #define AFI_FPCI_BAR2 0x38 52 #define AFI_FPCI_BAR3 0x3c 53 #define AFI_FPCI_BAR4 0x40 54 #define AFI_FPCI_BAR5 0x44 55 56 #define AFI_CACHE_BAR0_SZ 0x48 57 #define AFI_CACHE_BAR0_ST 0x4c 58 #define AFI_CACHE_BAR1_SZ 0x50 59 #define AFI_CACHE_BAR1_ST 0x54 60 61 #define AFI_MSI_BAR_SZ 0x60 62 #define AFI_MSI_FPCI_BAR_ST 0x64 63 #define AFI_MSI_AXI_BAR_ST 0x68 64 65 #define AFI_CONFIGURATION 0xac 66 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 67 68 #define AFI_FPCI_ERROR_MASKS 0xb0 69 70 #define AFI_INTR_MASK 0xb4 71 #define AFI_INTR_MASK_INT_MASK (1 << 0) 72 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 73 74 #define AFI_SM_INTR_ENABLE 0xc4 75 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 76 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 77 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 78 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 79 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 80 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 81 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 82 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 83 84 #define AFI_AFI_INTR_ENABLE 0xc8 85 #define AFI_INTR_EN_INI_SLVERR (1 << 0) 86 #define AFI_INTR_EN_INI_DECERR (1 << 1) 87 #define AFI_INTR_EN_TGT_SLVERR (1 << 2) 88 #define AFI_INTR_EN_TGT_DECERR (1 << 3) 89 #define AFI_INTR_EN_TGT_WRERR (1 << 4) 90 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) 91 #define AFI_INTR_EN_AXI_DECERR (1 << 6) 92 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) 93 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) 94 95 #define AFI_PCIE_CONFIG 0x0f8 96 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 97 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe 98 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 99 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) 100 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) 101 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) 102 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) 103 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) 104 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) 105 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) 106 107 #define AFI_FUSE 0x104 108 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 109 110 #define AFI_PEX0_CTRL 0x110 111 #define AFI_PEX1_CTRL 0x118 112 #define AFI_PEX2_CTRL 0x128 113 #define AFI_PEX_CTRL_RST (1 << 0) 114 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 115 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 116 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 117 118 #define AFI_PLLE_CONTROL 0x160 119 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 120 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 121 122 #define AFI_PEXBIAS_CTRL_0 0x168 123 124 #define PADS_CTL_SEL 0x0000009C 125 126 #define PADS_CTL 0x000000A0 127 #define PADS_CTL_IDDQ_1L (1 << 0) 128 #define PADS_CTL_TX_DATA_EN_1L (1 << 6) 129 #define PADS_CTL_RX_DATA_EN_1L (1 << 10) 130 131 #define PADS_PLL_CTL_TEGRA20 0x000000B8 132 #define PADS_PLL_CTL_TEGRA30 0x000000B4 133 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) 134 #define PADS_PLL_CTL_LOCKDET (0x1 << 8) 135 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) 136 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) 137 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) 138 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) 139 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) 140 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) 141 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) 142 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) 143 144 #define PADS_REFCLK_CFG0 0x000000C8 145 #define PADS_REFCLK_CFG1 0x000000CC 146 147 /* 148 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit 149 * entries, one entry per PCIe port. These field definitions and desired 150 * values aren't in the TRM, but do come from NVIDIA. 151 */ 152 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ 153 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 154 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ 155 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ 156 157 /* Default value provided by HW engineering is 0xfa5c */ 158 #define PADS_REFCLK_CFG_VALUE \ 159 ( \ 160 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ 161 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ 162 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ 163 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ 164 ) 165 166 #define RP_VEND_XP 0x00000F00 167 #define RP_VEND_XP_DL_UP (1 << 30) 168 169 #define RP_VEND_CTL2 0x00000FA8 170 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) 171 172 #define RP_PRIV_MISC 0x00000FE0 173 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 174 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 175 176 #define RP_LINK_CONTROL_STATUS 0x00000090 177 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 178 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 179 180 enum tegra_pci_id { 181 TEGRA20_PCIE, 182 TEGRA30_PCIE, 183 TEGRA124_PCIE, 184 TEGRA210_PCIE, 185 }; 186 187 struct tegra_pcie_port { 188 struct tegra_pcie *pcie; 189 190 struct fdt_resource regs; 191 unsigned int num_lanes; 192 unsigned int index; 193 194 struct list_head list; 195 }; 196 197 struct tegra_pcie_soc { 198 unsigned int num_ports; 199 unsigned long pads_pll_ctl; 200 unsigned long tx_ref_sel; 201 bool has_pex_clkreq_en; 202 bool has_pex_bias_ctrl; 203 bool has_cml_clk; 204 bool has_gen2; 205 bool force_pca_enable; 206 }; 207 208 struct tegra_pcie { 209 struct pci_controller hose; 210 211 struct fdt_resource pads; 212 struct fdt_resource afi; 213 struct fdt_resource cs; 214 215 struct list_head ports; 216 unsigned long xbar; 217 218 const struct tegra_pcie_soc *soc; 219 struct tegra_xusb_phy *phy; 220 }; 221 222 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, 223 unsigned long offset) 224 { 225 writel(value, pcie->afi.start + offset); 226 } 227 228 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) 229 { 230 return readl(pcie->afi.start + offset); 231 } 232 233 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, 234 unsigned long offset) 235 { 236 writel(value, pcie->pads.start + offset); 237 } 238 239 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) 240 { 241 return readl(pcie->pads.start + offset); 242 } 243 244 static unsigned long rp_readl(struct tegra_pcie_port *port, 245 unsigned long offset) 246 { 247 return readl(port->regs.start + offset); 248 } 249 250 static void rp_writel(struct tegra_pcie_port *port, unsigned long value, 251 unsigned long offset) 252 { 253 writel(value, port->regs.start + offset); 254 } 255 256 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) 257 { 258 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | 259 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | 260 (where & 0xfc); 261 } 262 263 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, 264 int where, unsigned long *address) 265 { 266 unsigned int bus = PCI_BUS(bdf); 267 268 if (bus == 0) { 269 unsigned int dev = PCI_DEV(bdf); 270 struct tegra_pcie_port *port; 271 272 list_for_each_entry(port, &pcie->ports, list) { 273 if (port->index + 1 == dev) { 274 *address = port->regs.start + (where & ~3); 275 return 0; 276 } 277 } 278 } else { 279 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); 280 return 0; 281 } 282 283 return -EFAULT; 284 } 285 286 static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf, 287 uint offset, ulong *valuep, 288 enum pci_size_t size) 289 { 290 struct tegra_pcie *pcie = dev_get_priv(bus); 291 unsigned long address, value; 292 int err; 293 294 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); 295 if (err < 0) { 296 value = 0xffffffff; 297 goto done; 298 } 299 300 value = readl(address); 301 302 /* fixup root port class */ 303 if (PCI_BUS(bdf) == 0) { 304 if (offset == PCI_CLASS_REVISION) { 305 value &= ~0x00ff0000; 306 value |= PCI_CLASS_BRIDGE_PCI << 16; 307 } 308 } 309 310 done: 311 *valuep = pci_conv_32_to_size(value, offset, size); 312 313 return 0; 314 } 315 316 static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf, 317 uint offset, ulong value, 318 enum pci_size_t size) 319 { 320 struct tegra_pcie *pcie = dev_get_priv(bus); 321 unsigned long address; 322 ulong old; 323 int err; 324 325 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); 326 if (err < 0) 327 return 0; 328 329 old = readl(address); 330 value = pci_conv_size_to_32(old, value, offset, size); 331 writel(value, address); 332 333 return 0; 334 } 335 336 static int tegra_pcie_port_parse_dt(const void *fdt, int node, 337 struct tegra_pcie_port *port) 338 { 339 const u32 *addr; 340 int len; 341 342 addr = fdt_getprop(fdt, node, "assigned-addresses", &len); 343 if (!addr) { 344 error("property \"assigned-addresses\" not found"); 345 return -FDT_ERR_NOTFOUND; 346 } 347 348 port->regs.start = fdt32_to_cpu(addr[2]); 349 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); 350 351 return 0; 352 } 353 354 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, 355 enum tegra_pci_id id, unsigned long *xbar) 356 { 357 switch (id) { 358 case TEGRA20_PCIE: 359 switch (lanes) { 360 case 0x00000004: 361 debug("single-mode configuration\n"); 362 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; 363 return 0; 364 365 case 0x00000202: 366 debug("dual-mode configuration\n"); 367 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; 368 return 0; 369 } 370 break; 371 case TEGRA30_PCIE: 372 switch (lanes) { 373 case 0x00000204: 374 debug("4x1, 2x1 configuration\n"); 375 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; 376 return 0; 377 378 case 0x00020202: 379 debug("2x3 configuration\n"); 380 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; 381 return 0; 382 383 case 0x00010104: 384 debug("4x1, 1x2 configuration\n"); 385 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; 386 return 0; 387 } 388 break; 389 case TEGRA124_PCIE: 390 case TEGRA210_PCIE: 391 switch (lanes) { 392 case 0x0000104: 393 debug("4x1, 1x1 configuration\n"); 394 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; 395 return 0; 396 397 case 0x0000102: 398 debug("2x1, 1x1 configuration\n"); 399 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; 400 return 0; 401 } 402 break; 403 default: 404 break; 405 } 406 407 return -FDT_ERR_NOTFOUND; 408 } 409 410 static int tegra_pcie_parse_port_info(const void *fdt, int node, 411 unsigned int *index, 412 unsigned int *lanes) 413 { 414 struct fdt_pci_addr addr; 415 int err; 416 417 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0); 418 if (err < 0) { 419 error("failed to parse \"nvidia,num-lanes\" property"); 420 return err; 421 } 422 423 *lanes = err; 424 425 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr); 426 if (err < 0) { 427 error("failed to parse \"reg\" property"); 428 return err; 429 } 430 431 *index = PCI_DEV(addr.phys_hi) - 1; 432 433 return 0; 434 } 435 436 int __weak tegra_pcie_board_init(void) 437 { 438 return 0; 439 } 440 441 static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, 442 struct tegra_pcie *pcie) 443 { 444 int err, subnode; 445 u32 lanes = 0; 446 447 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads", 448 &pcie->pads); 449 if (err < 0) { 450 error("resource \"pads\" not found"); 451 return err; 452 } 453 454 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi", 455 &pcie->afi); 456 if (err < 0) { 457 error("resource \"afi\" not found"); 458 return err; 459 } 460 461 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs", 462 &pcie->cs); 463 if (err < 0) { 464 error("resource \"cs\" not found"); 465 return err; 466 } 467 468 tegra_pcie_board_init(); 469 470 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); 471 if (pcie->phy) { 472 err = tegra_xusb_phy_prepare(pcie->phy); 473 if (err < 0) { 474 error("failed to prepare PHY: %d", err); 475 return err; 476 } 477 } 478 479 fdt_for_each_subnode(fdt, subnode, node) { 480 unsigned int index = 0, num_lanes = 0; 481 struct tegra_pcie_port *port; 482 483 err = tegra_pcie_parse_port_info(fdt, subnode, &index, 484 &num_lanes); 485 if (err < 0) { 486 error("failed to obtain root port info"); 487 continue; 488 } 489 490 lanes |= num_lanes << (index << 3); 491 492 if (!fdtdec_get_is_enabled(fdt, subnode)) 493 continue; 494 495 port = malloc(sizeof(*port)); 496 if (!port) 497 continue; 498 499 memset(port, 0, sizeof(*port)); 500 port->num_lanes = num_lanes; 501 port->index = index; 502 503 err = tegra_pcie_port_parse_dt(fdt, subnode, port); 504 if (err < 0) { 505 free(port); 506 continue; 507 } 508 509 list_add_tail(&port->list, &pcie->ports); 510 port->pcie = pcie; 511 } 512 513 err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar); 514 if (err < 0) { 515 error("invalid lane configuration"); 516 return err; 517 } 518 519 return 0; 520 } 521 522 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 523 { 524 const struct tegra_pcie_soc *soc = pcie->soc; 525 unsigned long value; 526 int err; 527 528 /* reset PCIEXCLK logic, AFI controller and PCIe controller */ 529 reset_set_enable(PERIPH_ID_PCIEXCLK, 1); 530 reset_set_enable(PERIPH_ID_AFI, 1); 531 reset_set_enable(PERIPH_ID_PCIE, 1); 532 533 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 534 if (err < 0) { 535 error("failed to power off PCIe partition: %d", err); 536 return err; 537 } 538 539 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, 540 PERIPH_ID_PCIE); 541 if (err < 0) { 542 error("failed to power up PCIe partition: %d", err); 543 return err; 544 } 545 546 /* take AFI controller out of reset */ 547 reset_set_enable(PERIPH_ID_AFI, 0); 548 549 /* enable AFI clock */ 550 clock_enable(PERIPH_ID_AFI); 551 552 if (soc->has_cml_clk) { 553 /* enable CML clock */ 554 value = readl(NV_PA_CLK_RST_BASE + 0x48c); 555 value |= (1 << 0); 556 value &= ~(1 << 1); 557 writel(value, NV_PA_CLK_RST_BASE + 0x48c); 558 } 559 560 err = tegra_plle_enable(); 561 if (err < 0) { 562 error("failed to enable PLLE: %d\n", err); 563 return err; 564 } 565 566 return 0; 567 } 568 569 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) 570 { 571 const struct tegra_pcie_soc *soc = pcie->soc; 572 unsigned long start = get_timer(0); 573 u32 value; 574 575 while (get_timer(start) < timeout) { 576 value = pads_readl(pcie, soc->pads_pll_ctl); 577 if (value & PADS_PLL_CTL_LOCKDET) 578 return 0; 579 } 580 581 return -ETIMEDOUT; 582 } 583 584 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 585 { 586 const struct tegra_pcie_soc *soc = pcie->soc; 587 u32 value; 588 int err; 589 590 /* initialize internal PHY, enable up to 16 PCIe lanes */ 591 pads_writel(pcie, 0, PADS_CTL_SEL); 592 593 /* override IDDQ to 1 on all 4 lanes */ 594 value = pads_readl(pcie, PADS_CTL); 595 value |= PADS_CTL_IDDQ_1L; 596 pads_writel(pcie, value, PADS_CTL); 597 598 /* 599 * Set up PHY PLL inputs select PLLE output as refclock, set TX 600 * ref sel to div10 (not div5). 601 */ 602 value = pads_readl(pcie, soc->pads_pll_ctl); 603 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); 604 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; 605 pads_writel(pcie, value, soc->pads_pll_ctl); 606 607 /* reset PLL */ 608 value = pads_readl(pcie, soc->pads_pll_ctl); 609 value &= ~PADS_PLL_CTL_RST_B4SM; 610 pads_writel(pcie, value, soc->pads_pll_ctl); 611 612 udelay(20); 613 614 /* take PLL out of reset */ 615 value = pads_readl(pcie, soc->pads_pll_ctl); 616 value |= PADS_PLL_CTL_RST_B4SM; 617 pads_writel(pcie, value, soc->pads_pll_ctl); 618 619 /* configure the reference clock driver */ 620 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); 621 pads_writel(pcie, value, PADS_REFCLK_CFG0); 622 623 if (soc->num_ports > 2) 624 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); 625 626 /* wait for the PLL to lock */ 627 err = tegra_pcie_pll_wait(pcie, 500); 628 if (err < 0) { 629 error("PLL failed to lock: %d", err); 630 return err; 631 } 632 633 /* turn off IDDQ override */ 634 value = pads_readl(pcie, PADS_CTL); 635 value &= ~PADS_CTL_IDDQ_1L; 636 pads_writel(pcie, value, PADS_CTL); 637 638 /* enable TX/RX data */ 639 value = pads_readl(pcie, PADS_CTL); 640 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; 641 pads_writel(pcie, value, PADS_CTL); 642 643 return 0; 644 } 645 646 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) 647 { 648 const struct tegra_pcie_soc *soc = pcie->soc; 649 struct tegra_pcie_port *port; 650 u32 value; 651 int err; 652 653 if (pcie->phy) { 654 value = afi_readl(pcie, AFI_PLLE_CONTROL); 655 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 656 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 657 afi_writel(pcie, value, AFI_PLLE_CONTROL); 658 } 659 660 if (soc->has_pex_bias_ctrl) 661 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); 662 663 value = afi_readl(pcie, AFI_PCIE_CONFIG); 664 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 665 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; 666 667 list_for_each_entry(port, &pcie->ports, list) 668 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); 669 670 afi_writel(pcie, value, AFI_PCIE_CONFIG); 671 672 value = afi_readl(pcie, AFI_FUSE); 673 674 if (soc->has_gen2) 675 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 676 else 677 value |= AFI_FUSE_PCIE_T0_GEN2_DIS; 678 679 afi_writel(pcie, value, AFI_FUSE); 680 681 if (pcie->phy) 682 err = tegra_xusb_phy_enable(pcie->phy); 683 else 684 err = tegra_pcie_phy_enable(pcie); 685 686 if (err < 0) { 687 error("failed to power on PHY: %d\n", err); 688 return err; 689 } 690 691 /* take the PCIEXCLK logic out of reset */ 692 reset_set_enable(PERIPH_ID_PCIEXCLK, 0); 693 694 /* finally enable PCIe */ 695 value = afi_readl(pcie, AFI_CONFIGURATION); 696 value |= AFI_CONFIGURATION_EN_FPCI; 697 afi_writel(pcie, value, AFI_CONFIGURATION); 698 699 /* disable all interrupts */ 700 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); 701 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); 702 afi_writel(pcie, 0, AFI_INTR_MASK); 703 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); 704 705 return 0; 706 } 707 708 static int tegra_pcie_setup_translations(struct udevice *bus) 709 { 710 struct tegra_pcie *pcie = dev_get_priv(bus); 711 unsigned long fpci, axi, size; 712 struct pci_region *io, *mem, *pref; 713 int count; 714 715 /* BAR 0: type 1 extended configuration space */ 716 fpci = 0xfe100000; 717 size = fdt_resource_size(&pcie->cs); 718 axi = pcie->cs.start; 719 720 afi_writel(pcie, axi, AFI_AXI_BAR0_START); 721 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); 722 afi_writel(pcie, fpci, AFI_FPCI_BAR0); 723 724 count = pci_get_regions(bus, &io, &mem, &pref); 725 if (count != 3) 726 return -EINVAL; 727 728 /* BAR 1: downstream I/O */ 729 fpci = 0xfdfc0000; 730 size = io->size; 731 axi = io->phys_start; 732 733 afi_writel(pcie, axi, AFI_AXI_BAR1_START); 734 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); 735 afi_writel(pcie, fpci, AFI_FPCI_BAR1); 736 737 /* BAR 2: prefetchable memory */ 738 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; 739 size = pref->size; 740 axi = pref->phys_start; 741 742 afi_writel(pcie, axi, AFI_AXI_BAR2_START); 743 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); 744 afi_writel(pcie, fpci, AFI_FPCI_BAR2); 745 746 /* BAR 3: non-prefetchable memory */ 747 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; 748 size = mem->size; 749 axi = mem->phys_start; 750 751 afi_writel(pcie, axi, AFI_AXI_BAR3_START); 752 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); 753 afi_writel(pcie, fpci, AFI_FPCI_BAR3); 754 755 /* NULL out the remaining BARs as they are not used */ 756 afi_writel(pcie, 0, AFI_AXI_BAR4_START); 757 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); 758 afi_writel(pcie, 0, AFI_FPCI_BAR4); 759 760 afi_writel(pcie, 0, AFI_AXI_BAR5_START); 761 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); 762 afi_writel(pcie, 0, AFI_FPCI_BAR5); 763 764 /* map all upstream transactions as uncached */ 765 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); 766 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); 767 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); 768 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); 769 770 /* MSI translations are setup only when needed */ 771 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); 772 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 773 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); 774 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 775 776 return 0; 777 } 778 779 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) 780 { 781 unsigned long ret = 0; 782 783 switch (port->index) { 784 case 0: 785 ret = AFI_PEX0_CTRL; 786 break; 787 788 case 1: 789 ret = AFI_PEX1_CTRL; 790 break; 791 792 case 2: 793 ret = AFI_PEX2_CTRL; 794 break; 795 } 796 797 return ret; 798 } 799 800 static void tegra_pcie_port_reset(struct tegra_pcie_port *port) 801 { 802 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 803 unsigned long value; 804 805 /* pulse reset signel */ 806 value = afi_readl(port->pcie, ctrl); 807 value &= ~AFI_PEX_CTRL_RST; 808 afi_writel(port->pcie, value, ctrl); 809 810 udelay(2000); 811 812 value = afi_readl(port->pcie, ctrl); 813 value |= AFI_PEX_CTRL_RST; 814 afi_writel(port->pcie, value, ctrl); 815 } 816 817 static void tegra_pcie_port_enable(struct tegra_pcie_port *port) 818 { 819 const struct tegra_pcie_soc *soc = port->pcie->soc; 820 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 821 unsigned long value; 822 823 /* enable reference clock */ 824 value = afi_readl(port->pcie, ctrl); 825 value |= AFI_PEX_CTRL_REFCLK_EN; 826 827 if (port->pcie->soc->has_pex_clkreq_en) 828 value |= AFI_PEX_CTRL_CLKREQ_EN; 829 830 value |= AFI_PEX_CTRL_OVERRIDE_EN; 831 832 afi_writel(port->pcie, value, ctrl); 833 834 tegra_pcie_port_reset(port); 835 836 if (soc->force_pca_enable) { 837 value = rp_readl(port, RP_VEND_CTL2); 838 value |= RP_VEND_CTL2_PCA_ENABLE; 839 rp_writel(port, value, RP_VEND_CTL2); 840 } 841 } 842 843 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) 844 { 845 unsigned int retries = 3; 846 unsigned long value; 847 848 value = rp_readl(port, RP_PRIV_MISC); 849 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 850 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 851 rp_writel(port, value, RP_PRIV_MISC); 852 853 do { 854 unsigned int timeout = 200; 855 856 do { 857 value = rp_readl(port, RP_VEND_XP); 858 if (value & RP_VEND_XP_DL_UP) 859 break; 860 861 udelay(2000); 862 } while (--timeout); 863 864 if (!timeout) { 865 debug("link %u down, retrying\n", port->index); 866 goto retry; 867 } 868 869 timeout = 200; 870 871 do { 872 value = rp_readl(port, RP_LINK_CONTROL_STATUS); 873 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 874 return true; 875 876 udelay(2000); 877 } while (--timeout); 878 879 retry: 880 tegra_pcie_port_reset(port); 881 } while (--retries); 882 883 return false; 884 } 885 886 static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 887 { 888 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 889 unsigned long value; 890 891 /* assert port reset */ 892 value = afi_readl(port->pcie, ctrl); 893 value &= ~AFI_PEX_CTRL_RST; 894 afi_writel(port->pcie, value, ctrl); 895 896 /* disable reference clock */ 897 value = afi_readl(port->pcie, ctrl); 898 value &= ~AFI_PEX_CTRL_REFCLK_EN; 899 afi_writel(port->pcie, value, ctrl); 900 } 901 902 static void tegra_pcie_port_free(struct tegra_pcie_port *port) 903 { 904 list_del(&port->list); 905 free(port); 906 } 907 908 static int tegra_pcie_enable(struct tegra_pcie *pcie) 909 { 910 struct tegra_pcie_port *port, *tmp; 911 912 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 913 debug("probing port %u, using %u lanes\n", port->index, 914 port->num_lanes); 915 916 tegra_pcie_port_enable(port); 917 918 if (tegra_pcie_port_check_link(port)) 919 continue; 920 921 debug("link %u down, ignoring\n", port->index); 922 923 tegra_pcie_port_disable(port); 924 tegra_pcie_port_free(port); 925 } 926 927 return 0; 928 } 929 930 static const struct tegra_pcie_soc pci_tegra_soc[] = { 931 [TEGRA20_PCIE] = { 932 .num_ports = 2, 933 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, 934 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, 935 .has_pex_clkreq_en = false, 936 .has_pex_bias_ctrl = false, 937 .has_cml_clk = false, 938 .has_gen2 = false, 939 }, 940 [TEGRA30_PCIE] = { 941 .num_ports = 3, 942 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 943 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 944 .has_pex_clkreq_en = true, 945 .has_pex_bias_ctrl = true, 946 .has_cml_clk = true, 947 .has_gen2 = false, 948 }, 949 [TEGRA124_PCIE] = { 950 .num_ports = 2, 951 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 952 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 953 .has_pex_clkreq_en = true, 954 .has_pex_bias_ctrl = true, 955 .has_cml_clk = true, 956 .has_gen2 = true, 957 }, 958 [TEGRA210_PCIE] = { 959 .num_ports = 2, 960 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 961 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 962 .has_pex_clkreq_en = true, 963 .has_pex_bias_ctrl = true, 964 .has_cml_clk = true, 965 .has_gen2 = true, 966 .force_pca_enable = true, 967 } 968 }; 969 970 static int pci_tegra_ofdata_to_platdata(struct udevice *dev) 971 { 972 struct tegra_pcie *pcie = dev_get_priv(dev); 973 enum tegra_pci_id id; 974 975 id = dev_get_driver_data(dev); 976 pcie->soc = &pci_tegra_soc[id]; 977 978 INIT_LIST_HEAD(&pcie->ports); 979 980 if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie)) 981 return -EINVAL; 982 983 return 0; 984 } 985 986 static int pci_tegra_probe(struct udevice *dev) 987 { 988 struct tegra_pcie *pcie = dev_get_priv(dev); 989 int err; 990 991 err = tegra_pcie_power_on(pcie); 992 if (err < 0) { 993 error("failed to power on"); 994 return err; 995 } 996 997 err = tegra_pcie_enable_controller(pcie); 998 if (err < 0) { 999 error("failed to enable controller"); 1000 return err; 1001 } 1002 1003 err = tegra_pcie_setup_translations(dev); 1004 if (err < 0) { 1005 error("failed to decode ranges"); 1006 return err; 1007 } 1008 1009 err = tegra_pcie_enable(pcie); 1010 if (err < 0) { 1011 error("failed to enable PCIe"); 1012 return err; 1013 } 1014 1015 return 0; 1016 } 1017 1018 static const struct dm_pci_ops pci_tegra_ops = { 1019 .read_config = pci_tegra_read_config, 1020 .write_config = pci_tegra_write_config, 1021 }; 1022 1023 static const struct udevice_id pci_tegra_ids[] = { 1024 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE }, 1025 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE }, 1026 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE }, 1027 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE }, 1028 { } 1029 }; 1030 1031 U_BOOT_DRIVER(pci_tegra) = { 1032 .name = "pci_tegra", 1033 .id = UCLASS_PCI, 1034 .of_match = pci_tegra_ids, 1035 .ops = &pci_tegra_ops, 1036 .ofdata_to_platdata = pci_tegra_ofdata_to_platdata, 1037 .probe = pci_tegra_probe, 1038 .priv_auto_alloc_size = sizeof(struct tegra_pcie), 1039 }; 1040 1041 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 1042 { 1043 if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0) 1044 return 1; 1045 1046 return 0; 1047 } 1048