1 /* 2 * Copyright (c) 2010, CompuLab, Ltd. 3 * Author: Mike Rapoport <mike@compulab.co.il> 4 * 5 * Based on NVIDIA PCIe driver 6 * Copyright (c) 2008-2009, NVIDIA Corporation. 7 * 8 * Copyright (c) 2013-2014, NVIDIA Corporation. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #define DEBUG 14 #define pr_fmt(fmt) "tegra-pcie: " fmt 15 16 #include <common.h> 17 #include <errno.h> 18 #include <fdtdec.h> 19 #include <malloc.h> 20 #include <pci.h> 21 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 25 #include <asm/arch/clock.h> 26 #include <asm/arch/powergate.h> 27 #include <asm/arch-tegra/xusb-padctl.h> 28 29 #include <linux/list.h> 30 31 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define AFI_AXI_BAR0_SZ 0x00 36 #define AFI_AXI_BAR1_SZ 0x04 37 #define AFI_AXI_BAR2_SZ 0x08 38 #define AFI_AXI_BAR3_SZ 0x0c 39 #define AFI_AXI_BAR4_SZ 0x10 40 #define AFI_AXI_BAR5_SZ 0x14 41 42 #define AFI_AXI_BAR0_START 0x18 43 #define AFI_AXI_BAR1_START 0x1c 44 #define AFI_AXI_BAR2_START 0x20 45 #define AFI_AXI_BAR3_START 0x24 46 #define AFI_AXI_BAR4_START 0x28 47 #define AFI_AXI_BAR5_START 0x2c 48 49 #define AFI_FPCI_BAR0 0x30 50 #define AFI_FPCI_BAR1 0x34 51 #define AFI_FPCI_BAR2 0x38 52 #define AFI_FPCI_BAR3 0x3c 53 #define AFI_FPCI_BAR4 0x40 54 #define AFI_FPCI_BAR5 0x44 55 56 #define AFI_CACHE_BAR0_SZ 0x48 57 #define AFI_CACHE_BAR0_ST 0x4c 58 #define AFI_CACHE_BAR1_SZ 0x50 59 #define AFI_CACHE_BAR1_ST 0x54 60 61 #define AFI_MSI_BAR_SZ 0x60 62 #define AFI_MSI_FPCI_BAR_ST 0x64 63 #define AFI_MSI_AXI_BAR_ST 0x68 64 65 #define AFI_CONFIGURATION 0xac 66 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 67 68 #define AFI_FPCI_ERROR_MASKS 0xb0 69 70 #define AFI_INTR_MASK 0xb4 71 #define AFI_INTR_MASK_INT_MASK (1 << 0) 72 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 73 74 #define AFI_SM_INTR_ENABLE 0xc4 75 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 76 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 77 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 78 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 79 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 80 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 81 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 82 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 83 84 #define AFI_AFI_INTR_ENABLE 0xc8 85 #define AFI_INTR_EN_INI_SLVERR (1 << 0) 86 #define AFI_INTR_EN_INI_DECERR (1 << 1) 87 #define AFI_INTR_EN_TGT_SLVERR (1 << 2) 88 #define AFI_INTR_EN_TGT_DECERR (1 << 3) 89 #define AFI_INTR_EN_TGT_WRERR (1 << 4) 90 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) 91 #define AFI_INTR_EN_AXI_DECERR (1 << 6) 92 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) 93 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) 94 95 #define AFI_PCIE_CONFIG 0x0f8 96 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 97 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe 98 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 99 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) 100 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) 101 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) 102 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) 103 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) 104 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) 105 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) 106 107 #define AFI_FUSE 0x104 108 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 109 110 #define AFI_PEX0_CTRL 0x110 111 #define AFI_PEX1_CTRL 0x118 112 #define AFI_PEX2_CTRL 0x128 113 #define AFI_PEX_CTRL_RST (1 << 0) 114 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 115 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 116 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 117 118 #define AFI_PLLE_CONTROL 0x160 119 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 120 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 121 122 #define AFI_PEXBIAS_CTRL_0 0x168 123 124 #define PADS_CTL_SEL 0x0000009C 125 126 #define PADS_CTL 0x000000A0 127 #define PADS_CTL_IDDQ_1L (1 << 0) 128 #define PADS_CTL_TX_DATA_EN_1L (1 << 6) 129 #define PADS_CTL_RX_DATA_EN_1L (1 << 10) 130 131 #define PADS_PLL_CTL_TEGRA20 0x000000B8 132 #define PADS_PLL_CTL_TEGRA30 0x000000B4 133 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) 134 #define PADS_PLL_CTL_LOCKDET (0x1 << 8) 135 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) 136 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) 137 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) 138 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) 139 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) 140 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) 141 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) 142 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) 143 144 #define PADS_REFCLK_CFG0 0x000000C8 145 #define PADS_REFCLK_CFG1 0x000000CC 146 147 /* 148 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit 149 * entries, one entry per PCIe port. These field definitions and desired 150 * values aren't in the TRM, but do come from NVIDIA. 151 */ 152 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ 153 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 154 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ 155 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ 156 157 /* Default value provided by HW engineering is 0xfa5c */ 158 #define PADS_REFCLK_CFG_VALUE \ 159 ( \ 160 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ 161 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ 162 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ 163 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ 164 ) 165 166 #define RP_VEND_XP 0x00000F00 167 #define RP_VEND_XP_DL_UP (1 << 30) 168 169 #define RP_PRIV_MISC 0x00000FE0 170 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 171 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 172 173 #define RP_LINK_CONTROL_STATUS 0x00000090 174 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 175 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 176 177 struct tegra_pcie; 178 179 struct tegra_pcie_port { 180 struct tegra_pcie *pcie; 181 182 struct fdt_resource regs; 183 unsigned int num_lanes; 184 unsigned int index; 185 186 struct list_head list; 187 }; 188 189 struct tegra_pcie_soc { 190 unsigned int num_ports; 191 unsigned long pads_pll_ctl; 192 unsigned long tx_ref_sel; 193 bool has_pex_clkreq_en; 194 bool has_pex_bias_ctrl; 195 bool has_cml_clk; 196 bool has_gen2; 197 }; 198 199 struct tegra_pcie { 200 struct pci_controller hose; 201 202 struct fdt_resource pads; 203 struct fdt_resource afi; 204 struct fdt_resource cs; 205 206 struct fdt_resource prefetch; 207 struct fdt_resource mem; 208 struct fdt_resource io; 209 210 struct list_head ports; 211 unsigned long xbar; 212 213 const struct tegra_pcie_soc *soc; 214 struct tegra_xusb_phy *phy; 215 }; 216 217 static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose) 218 { 219 return container_of(hose, struct tegra_pcie, hose); 220 } 221 222 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, 223 unsigned long offset) 224 { 225 writel(value, pcie->afi.start + offset); 226 } 227 228 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) 229 { 230 return readl(pcie->afi.start + offset); 231 } 232 233 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, 234 unsigned long offset) 235 { 236 writel(value, pcie->pads.start + offset); 237 } 238 239 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) 240 { 241 return readl(pcie->pads.start + offset); 242 } 243 244 static unsigned long rp_readl(struct tegra_pcie_port *port, 245 unsigned long offset) 246 { 247 return readl(port->regs.start + offset); 248 } 249 250 static void rp_writel(struct tegra_pcie_port *port, unsigned long value, 251 unsigned long offset) 252 { 253 writel(value, port->regs.start + offset); 254 } 255 256 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) 257 { 258 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | 259 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | 260 (where & 0xfc); 261 } 262 263 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, 264 int where, unsigned long *address) 265 { 266 unsigned int bus = PCI_BUS(bdf); 267 268 if (bus == 0) { 269 unsigned int dev = PCI_DEV(bdf); 270 struct tegra_pcie_port *port; 271 272 list_for_each_entry(port, &pcie->ports, list) { 273 if (port->index + 1 == dev) { 274 *address = port->regs.start + (where & ~3); 275 return 0; 276 } 277 } 278 } else { 279 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); 280 return 0; 281 } 282 283 return -1; 284 } 285 286 static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf, 287 int where, u32 *value) 288 { 289 struct tegra_pcie *pcie = to_tegra_pcie(hose); 290 unsigned long address; 291 int err; 292 293 err = tegra_pcie_conf_address(pcie, bdf, where, &address); 294 if (err < 0) { 295 *value = 0xffffffff; 296 return 1; 297 } 298 299 *value = readl(address); 300 301 /* fixup root port class */ 302 if (PCI_BUS(bdf) == 0) { 303 if (where == PCI_CLASS_REVISION) { 304 *value &= ~0x00ff0000; 305 *value |= PCI_CLASS_BRIDGE_PCI << 16; 306 } 307 } 308 309 return 0; 310 } 311 312 static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf, 313 int where, u32 value) 314 { 315 struct tegra_pcie *pcie = to_tegra_pcie(hose); 316 unsigned long address; 317 int err; 318 319 err = tegra_pcie_conf_address(pcie, bdf, where, &address); 320 if (err < 0) 321 return 1; 322 323 writel(value, address); 324 325 return 0; 326 } 327 328 static int tegra_pcie_port_parse_dt(const void *fdt, int node, 329 struct tegra_pcie_port *port) 330 { 331 const u32 *addr; 332 int len; 333 334 addr = fdt_getprop(fdt, node, "assigned-addresses", &len); 335 if (!addr) { 336 error("property \"assigned-addresses\" not found"); 337 return -FDT_ERR_NOTFOUND; 338 } 339 340 port->regs.start = fdt32_to_cpu(addr[2]); 341 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); 342 343 return 0; 344 } 345 346 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, 347 unsigned long *xbar) 348 { 349 enum fdt_compat_id id = fdtdec_lookup(fdt, node); 350 351 switch (id) { 352 case COMPAT_NVIDIA_TEGRA20_PCIE: 353 switch (lanes) { 354 case 0x00000004: 355 debug("single-mode configuration\n"); 356 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; 357 return 0; 358 359 case 0x00000202: 360 debug("dual-mode configuration\n"); 361 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; 362 return 0; 363 } 364 break; 365 366 case COMPAT_NVIDIA_TEGRA30_PCIE: 367 switch (lanes) { 368 case 0x00000204: 369 debug("4x1, 2x1 configuration\n"); 370 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; 371 return 0; 372 373 case 0x00020202: 374 debug("2x3 configuration\n"); 375 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; 376 return 0; 377 378 case 0x00010104: 379 debug("4x1, 1x2 configuration\n"); 380 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; 381 return 0; 382 } 383 break; 384 385 case COMPAT_NVIDIA_TEGRA124_PCIE: 386 switch (lanes) { 387 case 0x0000104: 388 debug("4x1, 1x1 configuration\n"); 389 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; 390 return 0; 391 392 case 0x0000102: 393 debug("2x1, 1x1 configuration\n"); 394 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; 395 return 0; 396 } 397 break; 398 399 default: 400 break; 401 } 402 403 return -FDT_ERR_NOTFOUND; 404 } 405 406 static int tegra_pcie_parse_dt_ranges(const void *fdt, int node, 407 struct tegra_pcie *pcie) 408 { 409 const u32 *ptr, *end; 410 int len; 411 412 ptr = fdt_getprop(fdt, node, "ranges", &len); 413 if (!ptr) { 414 error("missing \"ranges\" property"); 415 return -FDT_ERR_NOTFOUND; 416 } 417 418 end = ptr + len / 4; 419 420 while (ptr < end) { 421 struct fdt_resource *res = NULL; 422 u32 space = fdt32_to_cpu(*ptr); 423 424 switch ((space >> 24) & 0x3) { 425 case 0x01: 426 res = &pcie->io; 427 break; 428 429 case 0x02: /* 32 bit */ 430 case 0x03: /* 64 bit */ 431 if (space & (1 << 30)) 432 res = &pcie->prefetch; 433 else 434 res = &pcie->mem; 435 436 break; 437 } 438 439 if (res) { 440 res->start = fdt32_to_cpu(ptr[3]); 441 res->end = res->start + fdt32_to_cpu(ptr[5]); 442 } 443 444 ptr += 3 + 1 + 2; 445 } 446 447 debug("PCI regions:\n"); 448 debug(" I/O: %#x-%#x\n", pcie->io.start, pcie->io.end); 449 debug(" non-prefetchable memory: %#x-%#x\n", pcie->mem.start, 450 pcie->mem.end); 451 debug(" prefetchable memory: %#x-%#x\n", pcie->prefetch.start, 452 pcie->prefetch.end); 453 454 return 0; 455 } 456 457 static int tegra_pcie_parse_port_info(const void *fdt, int node, 458 unsigned int *index, 459 unsigned int *lanes) 460 { 461 struct fdt_pci_addr addr; 462 pci_dev_t bdf; 463 int err; 464 465 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0); 466 if (err < 0) { 467 error("failed to parse \"nvidia,num-lanes\" property"); 468 return err; 469 } 470 471 *lanes = err; 472 473 err = fdtdec_get_pci_bdf(fdt, node, &addr, &bdf); 474 if (err < 0) { 475 error("failed to parse \"reg\" property"); 476 return err; 477 } 478 479 *index = PCI_DEV(bdf) - 1; 480 481 return 0; 482 } 483 484 static int tegra_pcie_parse_dt(const void *fdt, int node, 485 struct tegra_pcie *pcie) 486 { 487 int err, subnode; 488 u32 lanes = 0; 489 490 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads", 491 &pcie->pads); 492 if (err < 0) { 493 error("resource \"pads\" not found"); 494 return err; 495 } 496 497 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi", 498 &pcie->afi); 499 if (err < 0) { 500 error("resource \"afi\" not found"); 501 return err; 502 } 503 504 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs", 505 &pcie->cs); 506 if (err < 0) { 507 error("resource \"cs\" not found"); 508 return err; 509 } 510 511 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); 512 if (pcie->phy) { 513 err = tegra_xusb_phy_prepare(pcie->phy); 514 if (err < 0) { 515 error("failed to prepare PHY: %d", err); 516 return err; 517 } 518 } 519 520 err = tegra_pcie_parse_dt_ranges(fdt, node, pcie); 521 if (err < 0) { 522 error("failed to parse \"ranges\" property"); 523 return err; 524 } 525 526 fdt_for_each_subnode(fdt, subnode, node) { 527 unsigned int index = 0, num_lanes = 0; 528 struct tegra_pcie_port *port; 529 530 err = tegra_pcie_parse_port_info(fdt, subnode, &index, 531 &num_lanes); 532 if (err < 0) { 533 error("failed to obtain root port info"); 534 continue; 535 } 536 537 lanes |= num_lanes << (index << 3); 538 539 if (!fdtdec_get_is_enabled(fdt, subnode)) 540 continue; 541 542 port = malloc(sizeof(*port)); 543 if (!port) 544 continue; 545 546 memset(port, 0, sizeof(*port)); 547 port->num_lanes = num_lanes; 548 port->index = index; 549 550 err = tegra_pcie_port_parse_dt(fdt, subnode, port); 551 if (err < 0) { 552 free(port); 553 continue; 554 } 555 556 list_add_tail(&port->list, &pcie->ports); 557 port->pcie = pcie; 558 } 559 560 err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar); 561 if (err < 0) { 562 error("invalid lane configuration"); 563 return err; 564 } 565 566 return 0; 567 } 568 569 int __weak tegra_pcie_board_init(void) 570 { 571 return 0; 572 } 573 574 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 575 { 576 const struct tegra_pcie_soc *soc = pcie->soc; 577 unsigned long value; 578 int err; 579 580 /* reset PCIEXCLK logic, AFI controller and PCIe controller */ 581 reset_set_enable(PERIPH_ID_PCIEXCLK, 1); 582 reset_set_enable(PERIPH_ID_AFI, 1); 583 reset_set_enable(PERIPH_ID_PCIE, 1); 584 585 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 586 if (err < 0) { 587 error("failed to power off PCIe partition: %d", err); 588 return err; 589 } 590 591 tegra_pcie_board_init(); 592 593 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, 594 PERIPH_ID_PCIE); 595 if (err < 0) { 596 error("failed to power up PCIe partition: %d", err); 597 return err; 598 } 599 600 /* take AFI controller out of reset */ 601 reset_set_enable(PERIPH_ID_AFI, 0); 602 603 /* enable AFI clock */ 604 clock_enable(PERIPH_ID_AFI); 605 606 if (soc->has_cml_clk) { 607 /* enable CML clock */ 608 value = readl(NV_PA_CLK_RST_BASE + 0x48c); 609 value |= (1 << 0); 610 value &= ~(1 << 1); 611 writel(value, NV_PA_CLK_RST_BASE + 0x48c); 612 } 613 614 err = tegra_plle_enable(); 615 if (err < 0) { 616 error("failed to enable PLLE: %d\n", err); 617 return err; 618 } 619 620 return 0; 621 } 622 623 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) 624 { 625 const struct tegra_pcie_soc *soc = pcie->soc; 626 unsigned long start = get_timer(0); 627 u32 value; 628 629 while (get_timer(start) < timeout) { 630 value = pads_readl(pcie, soc->pads_pll_ctl); 631 if (value & PADS_PLL_CTL_LOCKDET) 632 return 0; 633 } 634 635 return -ETIMEDOUT; 636 } 637 638 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 639 { 640 const struct tegra_pcie_soc *soc = pcie->soc; 641 u32 value; 642 int err; 643 644 /* initialize internal PHY, enable up to 16 PCIe lanes */ 645 pads_writel(pcie, 0, PADS_CTL_SEL); 646 647 /* override IDDQ to 1 on all 4 lanes */ 648 value = pads_readl(pcie, PADS_CTL); 649 value |= PADS_CTL_IDDQ_1L; 650 pads_writel(pcie, value, PADS_CTL); 651 652 /* 653 * Set up PHY PLL inputs select PLLE output as refclock, set TX 654 * ref sel to div10 (not div5). 655 */ 656 value = pads_readl(pcie, soc->pads_pll_ctl); 657 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); 658 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; 659 pads_writel(pcie, value, soc->pads_pll_ctl); 660 661 /* reset PLL */ 662 value = pads_readl(pcie, soc->pads_pll_ctl); 663 value &= ~PADS_PLL_CTL_RST_B4SM; 664 pads_writel(pcie, value, soc->pads_pll_ctl); 665 666 udelay(20); 667 668 /* take PLL out of reset */ 669 value = pads_readl(pcie, soc->pads_pll_ctl); 670 value |= PADS_PLL_CTL_RST_B4SM; 671 pads_writel(pcie, value, soc->pads_pll_ctl); 672 673 /* configure the reference clock driver */ 674 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); 675 pads_writel(pcie, value, PADS_REFCLK_CFG0); 676 677 if (soc->num_ports > 2) 678 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); 679 680 /* wait for the PLL to lock */ 681 err = tegra_pcie_pll_wait(pcie, 500); 682 if (err < 0) { 683 error("PLL failed to lock: %d", err); 684 return err; 685 } 686 687 /* turn off IDDQ override */ 688 value = pads_readl(pcie, PADS_CTL); 689 value &= ~PADS_CTL_IDDQ_1L; 690 pads_writel(pcie, value, PADS_CTL); 691 692 /* enable TX/RX data */ 693 value = pads_readl(pcie, PADS_CTL); 694 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; 695 pads_writel(pcie, value, PADS_CTL); 696 697 return 0; 698 } 699 700 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) 701 { 702 const struct tegra_pcie_soc *soc = pcie->soc; 703 struct tegra_pcie_port *port; 704 u32 value; 705 int err; 706 707 if (pcie->phy) { 708 value = afi_readl(pcie, AFI_PLLE_CONTROL); 709 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 710 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 711 afi_writel(pcie, value, AFI_PLLE_CONTROL); 712 } 713 714 if (soc->has_pex_bias_ctrl) 715 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); 716 717 value = afi_readl(pcie, AFI_PCIE_CONFIG); 718 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 719 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; 720 721 list_for_each_entry(port, &pcie->ports, list) 722 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); 723 724 afi_writel(pcie, value, AFI_PCIE_CONFIG); 725 726 value = afi_readl(pcie, AFI_FUSE); 727 728 if (soc->has_gen2) 729 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 730 else 731 value |= AFI_FUSE_PCIE_T0_GEN2_DIS; 732 733 afi_writel(pcie, value, AFI_FUSE); 734 735 if (pcie->phy) 736 err = tegra_xusb_phy_enable(pcie->phy); 737 else 738 err = tegra_pcie_phy_enable(pcie); 739 740 if (err < 0) { 741 error("failed to power on PHY: %d\n", err); 742 return err; 743 } 744 745 /* take the PCIEXCLK logic out of reset */ 746 reset_set_enable(PERIPH_ID_PCIEXCLK, 0); 747 748 /* finally enable PCIe */ 749 value = afi_readl(pcie, AFI_CONFIGURATION); 750 value |= AFI_CONFIGURATION_EN_FPCI; 751 afi_writel(pcie, value, AFI_CONFIGURATION); 752 753 /* disable all interrupts */ 754 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); 755 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); 756 afi_writel(pcie, 0, AFI_INTR_MASK); 757 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); 758 759 return 0; 760 } 761 762 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) 763 { 764 unsigned long fpci, axi, size; 765 766 /* BAR 0: type 1 extended configuration space */ 767 fpci = 0xfe100000; 768 size = fdt_resource_size(&pcie->cs); 769 axi = pcie->cs.start; 770 771 afi_writel(pcie, axi, AFI_AXI_BAR0_START); 772 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); 773 afi_writel(pcie, fpci, AFI_FPCI_BAR0); 774 775 /* BAR 1: downstream I/O */ 776 fpci = 0xfdfc0000; 777 size = fdt_resource_size(&pcie->io); 778 axi = pcie->io.start; 779 780 afi_writel(pcie, axi, AFI_AXI_BAR1_START); 781 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); 782 afi_writel(pcie, fpci, AFI_FPCI_BAR1); 783 784 /* BAR 2: prefetchable memory */ 785 fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; 786 size = fdt_resource_size(&pcie->prefetch); 787 axi = pcie->prefetch.start; 788 789 afi_writel(pcie, axi, AFI_AXI_BAR2_START); 790 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); 791 afi_writel(pcie, fpci, AFI_FPCI_BAR2); 792 793 /* BAR 3: non-prefetchable memory */ 794 fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; 795 size = fdt_resource_size(&pcie->mem); 796 axi = pcie->mem.start; 797 798 afi_writel(pcie, axi, AFI_AXI_BAR3_START); 799 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); 800 afi_writel(pcie, fpci, AFI_FPCI_BAR3); 801 802 /* NULL out the remaining BARs as they are not used */ 803 afi_writel(pcie, 0, AFI_AXI_BAR4_START); 804 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); 805 afi_writel(pcie, 0, AFI_FPCI_BAR4); 806 807 afi_writel(pcie, 0, AFI_AXI_BAR5_START); 808 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); 809 afi_writel(pcie, 0, AFI_FPCI_BAR5); 810 811 /* map all upstream transactions as uncached */ 812 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); 813 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); 814 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); 815 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); 816 817 /* MSI translations are setup only when needed */ 818 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); 819 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 820 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); 821 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 822 } 823 824 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) 825 { 826 unsigned long ret = 0; 827 828 switch (port->index) { 829 case 0: 830 ret = AFI_PEX0_CTRL; 831 break; 832 833 case 1: 834 ret = AFI_PEX1_CTRL; 835 break; 836 837 case 2: 838 ret = AFI_PEX2_CTRL; 839 break; 840 } 841 842 return ret; 843 } 844 845 static void tegra_pcie_port_reset(struct tegra_pcie_port *port) 846 { 847 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 848 unsigned long value; 849 850 /* pulse reset signel */ 851 value = afi_readl(port->pcie, ctrl); 852 value &= ~AFI_PEX_CTRL_RST; 853 afi_writel(port->pcie, value, ctrl); 854 855 udelay(2000); 856 857 value = afi_readl(port->pcie, ctrl); 858 value |= AFI_PEX_CTRL_RST; 859 afi_writel(port->pcie, value, ctrl); 860 } 861 862 static void tegra_pcie_port_enable(struct tegra_pcie_port *port) 863 { 864 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 865 unsigned long value; 866 867 /* enable reference clock */ 868 value = afi_readl(port->pcie, ctrl); 869 value |= AFI_PEX_CTRL_REFCLK_EN; 870 871 if (port->pcie->soc->has_pex_clkreq_en) 872 value |= AFI_PEX_CTRL_CLKREQ_EN; 873 874 value |= AFI_PEX_CTRL_OVERRIDE_EN; 875 876 afi_writel(port->pcie, value, ctrl); 877 878 tegra_pcie_port_reset(port); 879 } 880 881 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) 882 { 883 unsigned int retries = 3; 884 unsigned long value; 885 886 value = rp_readl(port, RP_PRIV_MISC); 887 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 888 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 889 rp_writel(port, value, RP_PRIV_MISC); 890 891 do { 892 unsigned int timeout = 200; 893 894 do { 895 value = rp_readl(port, RP_VEND_XP); 896 if (value & RP_VEND_XP_DL_UP) 897 break; 898 899 udelay(2000); 900 } while (--timeout); 901 902 if (!timeout) { 903 debug("link %u down, retrying\n", port->index); 904 goto retry; 905 } 906 907 timeout = 200; 908 909 do { 910 value = rp_readl(port, RP_LINK_CONTROL_STATUS); 911 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 912 return true; 913 914 udelay(2000); 915 } while (--timeout); 916 917 retry: 918 tegra_pcie_port_reset(port); 919 } while (--retries); 920 921 return false; 922 } 923 924 static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 925 { 926 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 927 unsigned long value; 928 929 /* assert port reset */ 930 value = afi_readl(port->pcie, ctrl); 931 value &= ~AFI_PEX_CTRL_RST; 932 afi_writel(port->pcie, value, ctrl); 933 934 /* disable reference clock */ 935 value = afi_readl(port->pcie, ctrl); 936 value &= ~AFI_PEX_CTRL_REFCLK_EN; 937 afi_writel(port->pcie, value, ctrl); 938 } 939 940 static void tegra_pcie_port_free(struct tegra_pcie_port *port) 941 { 942 list_del(&port->list); 943 free(port); 944 } 945 946 static int tegra_pcie_enable(struct tegra_pcie *pcie) 947 { 948 struct tegra_pcie_port *port, *tmp; 949 950 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 951 debug("probing port %u, using %u lanes\n", port->index, 952 port->num_lanes); 953 954 tegra_pcie_port_enable(port); 955 956 if (tegra_pcie_port_check_link(port)) 957 continue; 958 959 debug("link %u down, ignoring\n", port->index); 960 961 tegra_pcie_port_disable(port); 962 tegra_pcie_port_free(port); 963 } 964 965 return 0; 966 } 967 968 static const struct tegra_pcie_soc tegra20_pcie_soc = { 969 .num_ports = 2, 970 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, 971 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, 972 .has_pex_clkreq_en = false, 973 .has_pex_bias_ctrl = false, 974 .has_cml_clk = false, 975 .has_gen2 = false, 976 }; 977 978 static const struct tegra_pcie_soc tegra30_pcie_soc = { 979 .num_ports = 3, 980 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 981 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 982 .has_pex_clkreq_en = true, 983 .has_pex_bias_ctrl = true, 984 .has_cml_clk = true, 985 .has_gen2 = false, 986 }; 987 988 static const struct tegra_pcie_soc tegra124_pcie_soc = { 989 .num_ports = 2, 990 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 991 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 992 .has_pex_clkreq_en = true, 993 .has_pex_bias_ctrl = true, 994 .has_cml_clk = true, 995 .has_gen2 = true, 996 }; 997 998 static int process_nodes(const void *fdt, int nodes[], unsigned int count) 999 { 1000 unsigned int i; 1001 1002 for (i = 0; i < count; i++) { 1003 const struct tegra_pcie_soc *soc; 1004 struct tegra_pcie *pcie; 1005 enum fdt_compat_id id; 1006 int err; 1007 1008 if (!fdtdec_get_is_enabled(fdt, nodes[i])) 1009 continue; 1010 1011 id = fdtdec_lookup(fdt, nodes[i]); 1012 switch (id) { 1013 case COMPAT_NVIDIA_TEGRA20_PCIE: 1014 soc = &tegra20_pcie_soc; 1015 break; 1016 1017 case COMPAT_NVIDIA_TEGRA30_PCIE: 1018 soc = &tegra30_pcie_soc; 1019 break; 1020 1021 case COMPAT_NVIDIA_TEGRA124_PCIE: 1022 soc = &tegra124_pcie_soc; 1023 break; 1024 1025 default: 1026 error("unsupported compatible: %s", 1027 fdtdec_get_compatible(id)); 1028 continue; 1029 } 1030 1031 pcie = malloc(sizeof(*pcie)); 1032 if (!pcie) { 1033 error("failed to allocate controller"); 1034 continue; 1035 } 1036 1037 memset(pcie, 0, sizeof(*pcie)); 1038 pcie->soc = soc; 1039 1040 INIT_LIST_HEAD(&pcie->ports); 1041 1042 err = tegra_pcie_parse_dt(fdt, nodes[i], pcie); 1043 if (err < 0) { 1044 free(pcie); 1045 continue; 1046 } 1047 1048 err = tegra_pcie_power_on(pcie); 1049 if (err < 0) { 1050 error("failed to power on"); 1051 continue; 1052 } 1053 1054 err = tegra_pcie_enable_controller(pcie); 1055 if (err < 0) { 1056 error("failed to enable controller"); 1057 continue; 1058 } 1059 1060 tegra_pcie_setup_translations(pcie); 1061 1062 err = tegra_pcie_enable(pcie); 1063 if (err < 0) { 1064 error("failed to enable PCIe"); 1065 continue; 1066 } 1067 1068 pcie->hose.first_busno = 0; 1069 pcie->hose.current_busno = 0; 1070 pcie->hose.last_busno = 0; 1071 1072 pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE, 1073 NV_PA_SDRAM_BASE, gd->ram_size, 1074 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 1075 1076 pci_set_region(&pcie->hose.regions[1], pcie->io.start, 1077 pcie->io.start, fdt_resource_size(&pcie->io), 1078 PCI_REGION_IO); 1079 1080 pci_set_region(&pcie->hose.regions[2], pcie->mem.start, 1081 pcie->mem.start, fdt_resource_size(&pcie->mem), 1082 PCI_REGION_MEM); 1083 1084 pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start, 1085 pcie->prefetch.start, 1086 fdt_resource_size(&pcie->prefetch), 1087 PCI_REGION_MEM | PCI_REGION_PREFETCH); 1088 1089 pcie->hose.region_count = 4; 1090 1091 pci_set_ops(&pcie->hose, 1092 pci_hose_read_config_byte_via_dword, 1093 pci_hose_read_config_word_via_dword, 1094 tegra_pcie_read_conf, 1095 pci_hose_write_config_byte_via_dword, 1096 pci_hose_write_config_word_via_dword, 1097 tegra_pcie_write_conf); 1098 1099 pci_register_hose(&pcie->hose); 1100 1101 #ifdef CONFIG_PCI_SCAN_SHOW 1102 printf("PCI: Enumerating devices...\n"); 1103 printf("---------------------------------------\n"); 1104 printf(" Device ID Description\n"); 1105 printf(" ------ -- -----------\n"); 1106 #endif 1107 1108 pcie->hose.last_busno = pci_hose_scan(&pcie->hose); 1109 } 1110 1111 return 0; 1112 } 1113 1114 void pci_init_board(void) 1115 { 1116 const void *fdt = gd->fdt_blob; 1117 int count, nodes[1]; 1118 1119 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1120 COMPAT_NVIDIA_TEGRA124_PCIE, 1121 nodes, ARRAY_SIZE(nodes)); 1122 if (process_nodes(fdt, nodes, count)) 1123 return; 1124 1125 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1126 COMPAT_NVIDIA_TEGRA30_PCIE, 1127 nodes, ARRAY_SIZE(nodes)); 1128 if (process_nodes(fdt, nodes, count)) 1129 return; 1130 1131 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1132 COMPAT_NVIDIA_TEGRA20_PCIE, 1133 nodes, ARRAY_SIZE(nodes)); 1134 if (process_nodes(fdt, nodes, count)) 1135 return; 1136 } 1137 1138 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 1139 { 1140 if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0) 1141 return 1; 1142 1143 return 0; 1144 } 1145