1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2010, CompuLab, Ltd. 4 * Author: Mike Rapoport <mike@compulab.co.il> 5 * 6 * Based on NVIDIA PCIe driver 7 * Copyright (c) 2008-2009, NVIDIA Corporation. 8 * 9 * Copyright (c) 2013-2014, NVIDIA Corporation. 10 */ 11 12 #define pr_fmt(fmt) "tegra-pcie: " fmt 13 14 #include <common.h> 15 #include <clk.h> 16 #include <dm.h> 17 #include <errno.h> 18 #include <malloc.h> 19 #include <pci.h> 20 #include <power-domain.h> 21 #include <reset.h> 22 23 #include <asm/io.h> 24 #include <asm/gpio.h> 25 26 #include <linux/ioport.h> 27 #include <linux/list.h> 28 29 #ifndef CONFIG_TEGRA186 30 #include <asm/arch/clock.h> 31 #include <asm/arch/powergate.h> 32 #include <asm/arch-tegra/xusb-padctl.h> 33 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 34 #endif 35 36 /* 37 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that 38 * should not be present. These are needed because newer Tegra SoCs support 39 * only the standard clock/reset APIs, whereas older Tegra SoCs support only 40 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be 41 * fixed to implement the standard APIs, and all drivers converted to solely 42 * use the new standard APIs, with no ifdefs. 43 */ 44 45 #define AFI_AXI_BAR0_SZ 0x00 46 #define AFI_AXI_BAR1_SZ 0x04 47 #define AFI_AXI_BAR2_SZ 0x08 48 #define AFI_AXI_BAR3_SZ 0x0c 49 #define AFI_AXI_BAR4_SZ 0x10 50 #define AFI_AXI_BAR5_SZ 0x14 51 52 #define AFI_AXI_BAR0_START 0x18 53 #define AFI_AXI_BAR1_START 0x1c 54 #define AFI_AXI_BAR2_START 0x20 55 #define AFI_AXI_BAR3_START 0x24 56 #define AFI_AXI_BAR4_START 0x28 57 #define AFI_AXI_BAR5_START 0x2c 58 59 #define AFI_FPCI_BAR0 0x30 60 #define AFI_FPCI_BAR1 0x34 61 #define AFI_FPCI_BAR2 0x38 62 #define AFI_FPCI_BAR3 0x3c 63 #define AFI_FPCI_BAR4 0x40 64 #define AFI_FPCI_BAR5 0x44 65 66 #define AFI_CACHE_BAR0_SZ 0x48 67 #define AFI_CACHE_BAR0_ST 0x4c 68 #define AFI_CACHE_BAR1_SZ 0x50 69 #define AFI_CACHE_BAR1_ST 0x54 70 71 #define AFI_MSI_BAR_SZ 0x60 72 #define AFI_MSI_FPCI_BAR_ST 0x64 73 #define AFI_MSI_AXI_BAR_ST 0x68 74 75 #define AFI_CONFIGURATION 0xac 76 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 77 78 #define AFI_FPCI_ERROR_MASKS 0xb0 79 80 #define AFI_INTR_MASK 0xb4 81 #define AFI_INTR_MASK_INT_MASK (1 << 0) 82 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 83 84 #define AFI_SM_INTR_ENABLE 0xc4 85 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 86 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 87 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 88 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 89 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 90 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 91 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 92 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 93 94 #define AFI_AFI_INTR_ENABLE 0xc8 95 #define AFI_INTR_EN_INI_SLVERR (1 << 0) 96 #define AFI_INTR_EN_INI_DECERR (1 << 1) 97 #define AFI_INTR_EN_TGT_SLVERR (1 << 2) 98 #define AFI_INTR_EN_TGT_DECERR (1 << 3) 99 #define AFI_INTR_EN_TGT_WRERR (1 << 4) 100 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) 101 #define AFI_INTR_EN_AXI_DECERR (1 << 6) 102 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) 103 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) 104 105 #define AFI_PCIE_CONFIG 0x0f8 106 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 107 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe 108 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 109 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) 110 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) 111 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) 112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) 113 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) 114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) 115 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) 116 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20) 117 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20) 118 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20) 119 120 #define AFI_FUSE 0x104 121 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 122 123 #define AFI_PEX0_CTRL 0x110 124 #define AFI_PEX1_CTRL 0x118 125 #define AFI_PEX2_CTRL 0x128 126 #define AFI_PEX2_CTRL_T186 0x19c 127 #define AFI_PEX_CTRL_RST (1 << 0) 128 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 129 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 130 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 131 132 #define AFI_PLLE_CONTROL 0x160 133 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 134 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 135 136 #define AFI_PEXBIAS_CTRL_0 0x168 137 138 #define PADS_CTL_SEL 0x0000009C 139 140 #define PADS_CTL 0x000000A0 141 #define PADS_CTL_IDDQ_1L (1 << 0) 142 #define PADS_CTL_TX_DATA_EN_1L (1 << 6) 143 #define PADS_CTL_RX_DATA_EN_1L (1 << 10) 144 145 #define PADS_PLL_CTL_TEGRA20 0x000000B8 146 #define PADS_PLL_CTL_TEGRA30 0x000000B4 147 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) 148 #define PADS_PLL_CTL_LOCKDET (0x1 << 8) 149 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) 150 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) 151 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) 152 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) 153 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) 154 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) 155 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) 156 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) 157 158 #define PADS_REFCLK_CFG0 0x000000C8 159 #define PADS_REFCLK_CFG1 0x000000CC 160 161 /* 162 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit 163 * entries, one entry per PCIe port. These field definitions and desired 164 * values aren't in the TRM, but do come from NVIDIA. 165 */ 166 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ 167 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 168 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ 169 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ 170 171 #define RP_VEND_XP 0x00000F00 172 #define RP_VEND_XP_DL_UP (1 << 30) 173 174 #define RP_VEND_CTL2 0x00000FA8 175 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) 176 177 #define RP_PRIV_MISC 0x00000FE0 178 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 179 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 180 181 #define RP_LINK_CONTROL_STATUS 0x00000090 182 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 183 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 184 185 enum tegra_pci_id { 186 TEGRA20_PCIE, 187 TEGRA30_PCIE, 188 TEGRA124_PCIE, 189 TEGRA210_PCIE, 190 TEGRA186_PCIE, 191 }; 192 193 struct tegra_pcie_port { 194 struct tegra_pcie *pcie; 195 196 struct fdt_resource regs; 197 unsigned int num_lanes; 198 unsigned int index; 199 200 struct list_head list; 201 }; 202 203 struct tegra_pcie_soc { 204 unsigned int num_ports; 205 unsigned long pads_pll_ctl; 206 unsigned long tx_ref_sel; 207 unsigned long afi_pex2_ctrl; 208 u32 pads_refclk_cfg0; 209 u32 pads_refclk_cfg1; 210 bool has_pex_clkreq_en; 211 bool has_pex_bias_ctrl; 212 bool has_cml_clk; 213 bool has_gen2; 214 bool force_pca_enable; 215 }; 216 217 struct tegra_pcie { 218 struct resource pads; 219 struct resource afi; 220 struct resource cs; 221 222 struct list_head ports; 223 unsigned long xbar; 224 225 const struct tegra_pcie_soc *soc; 226 227 #ifdef CONFIG_TEGRA186 228 struct clk clk_afi; 229 struct clk clk_pex; 230 struct reset_ctl reset_afi; 231 struct reset_ctl reset_pex; 232 struct reset_ctl reset_pcie_x; 233 struct power_domain pwrdom; 234 #else 235 struct tegra_xusb_phy *phy; 236 #endif 237 }; 238 239 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, 240 unsigned long offset) 241 { 242 writel(value, pcie->afi.start + offset); 243 } 244 245 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) 246 { 247 return readl(pcie->afi.start + offset); 248 } 249 250 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, 251 unsigned long offset) 252 { 253 writel(value, pcie->pads.start + offset); 254 } 255 256 #ifndef CONFIG_TEGRA186 257 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) 258 { 259 return readl(pcie->pads.start + offset); 260 } 261 #endif 262 263 static unsigned long rp_readl(struct tegra_pcie_port *port, 264 unsigned long offset) 265 { 266 return readl(port->regs.start + offset); 267 } 268 269 static void rp_writel(struct tegra_pcie_port *port, unsigned long value, 270 unsigned long offset) 271 { 272 writel(value, port->regs.start + offset); 273 } 274 275 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) 276 { 277 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | 278 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | 279 (where & 0xfc); 280 } 281 282 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, 283 int where, unsigned long *address) 284 { 285 unsigned int bus = PCI_BUS(bdf); 286 287 if (bus == 0) { 288 unsigned int dev = PCI_DEV(bdf); 289 struct tegra_pcie_port *port; 290 291 list_for_each_entry(port, &pcie->ports, list) { 292 if (port->index + 1 == dev) { 293 *address = port->regs.start + (where & ~3); 294 return 0; 295 } 296 } 297 return -EFAULT; 298 } else { 299 #ifdef CONFIG_TEGRA20 300 unsigned int dev = PCI_DEV(bdf); 301 if (dev != 0) 302 return -EFAULT; 303 #endif 304 305 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); 306 return 0; 307 } 308 } 309 310 static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf, 311 uint offset, ulong *valuep, 312 enum pci_size_t size) 313 { 314 struct tegra_pcie *pcie = dev_get_priv(bus); 315 unsigned long address, value; 316 int err; 317 318 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); 319 if (err < 0) { 320 value = 0xffffffff; 321 goto done; 322 } 323 324 value = readl(address); 325 326 #ifdef CONFIG_TEGRA20 327 /* fixup root port class */ 328 if (PCI_BUS(bdf) == 0) { 329 if ((offset & ~3) == PCI_CLASS_REVISION) { 330 value &= ~0x00ff0000; 331 value |= PCI_CLASS_BRIDGE_PCI << 16; 332 } 333 } 334 #endif 335 336 done: 337 *valuep = pci_conv_32_to_size(value, offset, size); 338 339 return 0; 340 } 341 342 static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf, 343 uint offset, ulong value, 344 enum pci_size_t size) 345 { 346 struct tegra_pcie *pcie = dev_get_priv(bus); 347 unsigned long address; 348 ulong old; 349 int err; 350 351 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); 352 if (err < 0) 353 return 0; 354 355 old = readl(address); 356 value = pci_conv_size_to_32(old, value, offset, size); 357 writel(value, address); 358 359 return 0; 360 } 361 362 static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port) 363 { 364 const u32 *addr; 365 int len; 366 367 addr = ofnode_get_property(node, "assigned-addresses", &len); 368 if (!addr) { 369 pr_err("property \"assigned-addresses\" not found"); 370 return -FDT_ERR_NOTFOUND; 371 } 372 373 port->regs.start = fdt32_to_cpu(addr[2]); 374 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); 375 376 return 0; 377 } 378 379 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes, 380 enum tegra_pci_id id, unsigned long *xbar) 381 { 382 switch (id) { 383 case TEGRA20_PCIE: 384 switch (lanes) { 385 case 0x00000004: 386 debug("single-mode configuration\n"); 387 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; 388 return 0; 389 390 case 0x00000202: 391 debug("dual-mode configuration\n"); 392 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; 393 return 0; 394 } 395 break; 396 case TEGRA30_PCIE: 397 switch (lanes) { 398 case 0x00000204: 399 debug("4x1, 2x1 configuration\n"); 400 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; 401 return 0; 402 403 case 0x00020202: 404 debug("2x3 configuration\n"); 405 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; 406 return 0; 407 408 case 0x00010104: 409 debug("4x1, 1x2 configuration\n"); 410 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; 411 return 0; 412 } 413 break; 414 case TEGRA124_PCIE: 415 case TEGRA210_PCIE: 416 switch (lanes) { 417 case 0x0000104: 418 debug("4x1, 1x1 configuration\n"); 419 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; 420 return 0; 421 422 case 0x0000102: 423 debug("2x1, 1x1 configuration\n"); 424 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; 425 return 0; 426 } 427 break; 428 case TEGRA186_PCIE: 429 switch (lanes) { 430 case 0x0010004: 431 debug("x4 x1 configuration\n"); 432 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401; 433 return 0; 434 435 case 0x0010102: 436 debug("x2 x1 x1 configuration\n"); 437 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211; 438 return 0; 439 440 case 0x0010101: 441 debug("x1 x1 x1 configuration\n"); 442 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111; 443 return 0; 444 } 445 break; 446 default: 447 break; 448 } 449 450 return -FDT_ERR_NOTFOUND; 451 } 452 453 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) 454 { 455 struct fdt_pci_addr addr; 456 int err; 457 458 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1); 459 if (err < 0) { 460 pr_err("failed to parse \"nvidia,num-lanes\" property"); 461 return err; 462 } 463 464 *lanes = err; 465 466 err = ofnode_read_pci_addr(node, 0, "reg", &addr); 467 if (err < 0) { 468 pr_err("failed to parse \"reg\" property"); 469 return err; 470 } 471 472 *index = PCI_DEV(addr.phys_hi) - 1; 473 474 return 0; 475 } 476 477 int __weak tegra_pcie_board_init(void) 478 { 479 return 0; 480 } 481 482 static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id, 483 struct tegra_pcie *pcie) 484 { 485 ofnode subnode; 486 u32 lanes = 0; 487 int err; 488 489 err = dev_read_resource(dev, 0, &pcie->pads); 490 if (err < 0) { 491 pr_err("resource \"pads\" not found"); 492 return err; 493 } 494 495 err = dev_read_resource(dev, 1, &pcie->afi); 496 if (err < 0) { 497 pr_err("resource \"afi\" not found"); 498 return err; 499 } 500 501 err = dev_read_resource(dev, 2, &pcie->cs); 502 if (err < 0) { 503 pr_err("resource \"cs\" not found"); 504 return err; 505 } 506 507 err = tegra_pcie_board_init(); 508 if (err < 0) { 509 pr_err("tegra_pcie_board_init() failed: err=%d", err); 510 return err; 511 } 512 513 #ifndef CONFIG_TEGRA186 514 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); 515 if (pcie->phy) { 516 err = tegra_xusb_phy_prepare(pcie->phy); 517 if (err < 0) { 518 pr_err("failed to prepare PHY: %d", err); 519 return err; 520 } 521 } 522 #endif 523 524 dev_for_each_subnode(subnode, dev) { 525 unsigned int index = 0, num_lanes = 0; 526 struct tegra_pcie_port *port; 527 528 err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes); 529 if (err < 0) { 530 pr_err("failed to obtain root port info"); 531 continue; 532 } 533 534 lanes |= num_lanes << (index << 3); 535 536 if (!ofnode_is_available(subnode)) 537 continue; 538 539 port = malloc(sizeof(*port)); 540 if (!port) 541 continue; 542 543 memset(port, 0, sizeof(*port)); 544 port->num_lanes = num_lanes; 545 port->index = index; 546 547 err = tegra_pcie_port_parse_dt(subnode, port); 548 if (err < 0) { 549 free(port); 550 continue; 551 } 552 553 list_add_tail(&port->list, &pcie->ports); 554 port->pcie = pcie; 555 } 556 557 err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id, 558 &pcie->xbar); 559 if (err < 0) { 560 pr_err("invalid lane configuration"); 561 return err; 562 } 563 564 return 0; 565 } 566 567 #ifdef CONFIG_TEGRA186 568 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 569 { 570 int ret; 571 572 ret = power_domain_on(&pcie->pwrdom); 573 if (ret) { 574 pr_err("power_domain_on() failed: %d\n", ret); 575 return ret; 576 } 577 578 ret = clk_enable(&pcie->clk_afi); 579 if (ret) { 580 pr_err("clk_enable(afi) failed: %d\n", ret); 581 return ret; 582 } 583 584 ret = clk_enable(&pcie->clk_pex); 585 if (ret) { 586 pr_err("clk_enable(pex) failed: %d\n", ret); 587 return ret; 588 } 589 590 ret = reset_deassert(&pcie->reset_afi); 591 if (ret) { 592 pr_err("reset_deassert(afi) failed: %d\n", ret); 593 return ret; 594 } 595 596 ret = reset_deassert(&pcie->reset_pex); 597 if (ret) { 598 pr_err("reset_deassert(pex) failed: %d\n", ret); 599 return ret; 600 } 601 602 return 0; 603 } 604 #else 605 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 606 { 607 const struct tegra_pcie_soc *soc = pcie->soc; 608 unsigned long value; 609 int err; 610 611 /* reset PCIEXCLK logic, AFI controller and PCIe controller */ 612 reset_set_enable(PERIPH_ID_PCIEXCLK, 1); 613 reset_set_enable(PERIPH_ID_AFI, 1); 614 reset_set_enable(PERIPH_ID_PCIE, 1); 615 616 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 617 if (err < 0) { 618 pr_err("failed to power off PCIe partition: %d", err); 619 return err; 620 } 621 622 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, 623 PERIPH_ID_PCIE); 624 if (err < 0) { 625 pr_err("failed to power up PCIe partition: %d", err); 626 return err; 627 } 628 629 /* take AFI controller out of reset */ 630 reset_set_enable(PERIPH_ID_AFI, 0); 631 632 /* enable AFI clock */ 633 clock_enable(PERIPH_ID_AFI); 634 635 if (soc->has_cml_clk) { 636 /* enable CML clock */ 637 value = readl(NV_PA_CLK_RST_BASE + 0x48c); 638 value |= (1 << 0); 639 value &= ~(1 << 1); 640 writel(value, NV_PA_CLK_RST_BASE + 0x48c); 641 } 642 643 err = tegra_plle_enable(); 644 if (err < 0) { 645 pr_err("failed to enable PLLE: %d\n", err); 646 return err; 647 } 648 649 return 0; 650 } 651 652 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) 653 { 654 const struct tegra_pcie_soc *soc = pcie->soc; 655 unsigned long start = get_timer(0); 656 u32 value; 657 658 while (get_timer(start) < timeout) { 659 value = pads_readl(pcie, soc->pads_pll_ctl); 660 if (value & PADS_PLL_CTL_LOCKDET) 661 return 0; 662 } 663 664 return -ETIMEDOUT; 665 } 666 667 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 668 { 669 const struct tegra_pcie_soc *soc = pcie->soc; 670 u32 value; 671 int err; 672 673 /* initialize internal PHY, enable up to 16 PCIe lanes */ 674 pads_writel(pcie, 0, PADS_CTL_SEL); 675 676 /* override IDDQ to 1 on all 4 lanes */ 677 value = pads_readl(pcie, PADS_CTL); 678 value |= PADS_CTL_IDDQ_1L; 679 pads_writel(pcie, value, PADS_CTL); 680 681 /* 682 * Set up PHY PLL inputs select PLLE output as refclock, set TX 683 * ref sel to div10 (not div5). 684 */ 685 value = pads_readl(pcie, soc->pads_pll_ctl); 686 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); 687 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; 688 pads_writel(pcie, value, soc->pads_pll_ctl); 689 690 /* reset PLL */ 691 value = pads_readl(pcie, soc->pads_pll_ctl); 692 value &= ~PADS_PLL_CTL_RST_B4SM; 693 pads_writel(pcie, value, soc->pads_pll_ctl); 694 695 udelay(20); 696 697 /* take PLL out of reset */ 698 value = pads_readl(pcie, soc->pads_pll_ctl); 699 value |= PADS_PLL_CTL_RST_B4SM; 700 pads_writel(pcie, value, soc->pads_pll_ctl); 701 702 /* wait for the PLL to lock */ 703 err = tegra_pcie_pll_wait(pcie, 500); 704 if (err < 0) { 705 pr_err("PLL failed to lock: %d", err); 706 return err; 707 } 708 709 /* turn off IDDQ override */ 710 value = pads_readl(pcie, PADS_CTL); 711 value &= ~PADS_CTL_IDDQ_1L; 712 pads_writel(pcie, value, PADS_CTL); 713 714 /* enable TX/RX data */ 715 value = pads_readl(pcie, PADS_CTL); 716 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; 717 pads_writel(pcie, value, PADS_CTL); 718 719 return 0; 720 } 721 #endif 722 723 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) 724 { 725 const struct tegra_pcie_soc *soc = pcie->soc; 726 struct tegra_pcie_port *port; 727 u32 value; 728 int err; 729 730 #ifdef CONFIG_TEGRA186 731 { 732 #else 733 if (pcie->phy) { 734 #endif 735 value = afi_readl(pcie, AFI_PLLE_CONTROL); 736 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 737 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 738 afi_writel(pcie, value, AFI_PLLE_CONTROL); 739 } 740 741 if (soc->has_pex_bias_ctrl) 742 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); 743 744 value = afi_readl(pcie, AFI_PCIE_CONFIG); 745 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 746 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; 747 748 list_for_each_entry(port, &pcie->ports, list) 749 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); 750 751 afi_writel(pcie, value, AFI_PCIE_CONFIG); 752 753 value = afi_readl(pcie, AFI_FUSE); 754 755 if (soc->has_gen2) 756 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 757 else 758 value |= AFI_FUSE_PCIE_T0_GEN2_DIS; 759 760 afi_writel(pcie, value, AFI_FUSE); 761 762 #ifndef CONFIG_TEGRA186 763 if (pcie->phy) 764 err = tegra_xusb_phy_enable(pcie->phy); 765 else 766 err = tegra_pcie_phy_enable(pcie); 767 768 if (err < 0) { 769 pr_err("failed to power on PHY: %d\n", err); 770 return err; 771 } 772 #endif 773 774 /* take the PCIEXCLK logic out of reset */ 775 #ifdef CONFIG_TEGRA186 776 err = reset_deassert(&pcie->reset_pcie_x); 777 if (err) { 778 pr_err("reset_deassert(pcie_x) failed: %d\n", err); 779 return err; 780 } 781 #else 782 reset_set_enable(PERIPH_ID_PCIEXCLK, 0); 783 #endif 784 785 /* finally enable PCIe */ 786 value = afi_readl(pcie, AFI_CONFIGURATION); 787 value |= AFI_CONFIGURATION_EN_FPCI; 788 afi_writel(pcie, value, AFI_CONFIGURATION); 789 790 /* disable all interrupts */ 791 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); 792 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); 793 afi_writel(pcie, 0, AFI_INTR_MASK); 794 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); 795 796 return 0; 797 } 798 799 static int tegra_pcie_setup_translations(struct udevice *bus) 800 { 801 struct tegra_pcie *pcie = dev_get_priv(bus); 802 unsigned long fpci, axi, size; 803 struct pci_region *io, *mem, *pref; 804 int count; 805 806 /* BAR 0: type 1 extended configuration space */ 807 fpci = 0xfe100000; 808 size = resource_size(&pcie->cs); 809 axi = pcie->cs.start; 810 811 afi_writel(pcie, axi, AFI_AXI_BAR0_START); 812 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); 813 afi_writel(pcie, fpci, AFI_FPCI_BAR0); 814 815 count = pci_get_regions(bus, &io, &mem, &pref); 816 if (count != 3) 817 return -EINVAL; 818 819 /* BAR 1: downstream I/O */ 820 fpci = 0xfdfc0000; 821 size = io->size; 822 axi = io->phys_start; 823 824 afi_writel(pcie, axi, AFI_AXI_BAR1_START); 825 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); 826 afi_writel(pcie, fpci, AFI_FPCI_BAR1); 827 828 /* BAR 2: prefetchable memory */ 829 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; 830 size = pref->size; 831 axi = pref->phys_start; 832 833 afi_writel(pcie, axi, AFI_AXI_BAR2_START); 834 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); 835 afi_writel(pcie, fpci, AFI_FPCI_BAR2); 836 837 /* BAR 3: non-prefetchable memory */ 838 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; 839 size = mem->size; 840 axi = mem->phys_start; 841 842 afi_writel(pcie, axi, AFI_AXI_BAR3_START); 843 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); 844 afi_writel(pcie, fpci, AFI_FPCI_BAR3); 845 846 /* NULL out the remaining BARs as they are not used */ 847 afi_writel(pcie, 0, AFI_AXI_BAR4_START); 848 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); 849 afi_writel(pcie, 0, AFI_FPCI_BAR4); 850 851 afi_writel(pcie, 0, AFI_AXI_BAR5_START); 852 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); 853 afi_writel(pcie, 0, AFI_FPCI_BAR5); 854 855 /* map all upstream transactions as uncached */ 856 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); 857 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); 858 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); 859 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); 860 861 /* MSI translations are setup only when needed */ 862 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); 863 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 864 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); 865 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 866 867 return 0; 868 } 869 870 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) 871 { 872 unsigned long ret = 0; 873 874 switch (port->index) { 875 case 0: 876 ret = AFI_PEX0_CTRL; 877 break; 878 879 case 1: 880 ret = AFI_PEX1_CTRL; 881 break; 882 883 case 2: 884 ret = port->pcie->soc->afi_pex2_ctrl; 885 break; 886 } 887 888 return ret; 889 } 890 891 static void tegra_pcie_port_reset(struct tegra_pcie_port *port) 892 { 893 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 894 unsigned long value; 895 896 /* pulse reset signel */ 897 value = afi_readl(port->pcie, ctrl); 898 value &= ~AFI_PEX_CTRL_RST; 899 afi_writel(port->pcie, value, ctrl); 900 901 udelay(2000); 902 903 value = afi_readl(port->pcie, ctrl); 904 value |= AFI_PEX_CTRL_RST; 905 afi_writel(port->pcie, value, ctrl); 906 } 907 908 static void tegra_pcie_port_enable(struct tegra_pcie_port *port) 909 { 910 struct tegra_pcie *pcie = port->pcie; 911 const struct tegra_pcie_soc *soc = pcie->soc; 912 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 913 unsigned long value; 914 915 /* enable reference clock */ 916 value = afi_readl(pcie, ctrl); 917 value |= AFI_PEX_CTRL_REFCLK_EN; 918 919 if (pcie->soc->has_pex_clkreq_en) 920 value |= AFI_PEX_CTRL_CLKREQ_EN; 921 922 value |= AFI_PEX_CTRL_OVERRIDE_EN; 923 924 afi_writel(pcie, value, ctrl); 925 926 tegra_pcie_port_reset(port); 927 928 if (soc->force_pca_enable) { 929 value = rp_readl(port, RP_VEND_CTL2); 930 value |= RP_VEND_CTL2_PCA_ENABLE; 931 rp_writel(port, value, RP_VEND_CTL2); 932 } 933 934 /* configure the reference clock driver */ 935 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); 936 if (soc->num_ports > 2) 937 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); 938 } 939 940 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) 941 { 942 unsigned int retries = 3; 943 unsigned long value; 944 945 value = rp_readl(port, RP_PRIV_MISC); 946 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 947 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 948 rp_writel(port, value, RP_PRIV_MISC); 949 950 do { 951 unsigned int timeout = 200; 952 953 do { 954 value = rp_readl(port, RP_VEND_XP); 955 if (value & RP_VEND_XP_DL_UP) 956 break; 957 958 udelay(2000); 959 } while (--timeout); 960 961 if (!timeout) { 962 debug("link %u down, retrying\n", port->index); 963 goto retry; 964 } 965 966 timeout = 200; 967 968 do { 969 value = rp_readl(port, RP_LINK_CONTROL_STATUS); 970 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 971 return true; 972 973 udelay(2000); 974 } while (--timeout); 975 976 retry: 977 tegra_pcie_port_reset(port); 978 } while (--retries); 979 980 return false; 981 } 982 983 static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 984 { 985 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 986 unsigned long value; 987 988 /* assert port reset */ 989 value = afi_readl(port->pcie, ctrl); 990 value &= ~AFI_PEX_CTRL_RST; 991 afi_writel(port->pcie, value, ctrl); 992 993 /* disable reference clock */ 994 value = afi_readl(port->pcie, ctrl); 995 value &= ~AFI_PEX_CTRL_REFCLK_EN; 996 afi_writel(port->pcie, value, ctrl); 997 } 998 999 static void tegra_pcie_port_free(struct tegra_pcie_port *port) 1000 { 1001 list_del(&port->list); 1002 free(port); 1003 } 1004 1005 static int tegra_pcie_enable(struct tegra_pcie *pcie) 1006 { 1007 struct tegra_pcie_port *port, *tmp; 1008 1009 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1010 debug("probing port %u, using %u lanes\n", port->index, 1011 port->num_lanes); 1012 1013 tegra_pcie_port_enable(port); 1014 1015 if (tegra_pcie_port_check_link(port)) 1016 continue; 1017 1018 debug("link %u down, ignoring\n", port->index); 1019 1020 tegra_pcie_port_disable(port); 1021 tegra_pcie_port_free(port); 1022 } 1023 1024 return 0; 1025 } 1026 1027 static const struct tegra_pcie_soc pci_tegra_soc[] = { 1028 [TEGRA20_PCIE] = { 1029 .num_ports = 2, 1030 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, 1031 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, 1032 .pads_refclk_cfg0 = 0xfa5cfa5c, 1033 .has_pex_clkreq_en = false, 1034 .has_pex_bias_ctrl = false, 1035 .has_cml_clk = false, 1036 .has_gen2 = false, 1037 }, 1038 [TEGRA30_PCIE] = { 1039 .num_ports = 3, 1040 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1041 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1042 .afi_pex2_ctrl = AFI_PEX2_CTRL, 1043 .pads_refclk_cfg0 = 0xfa5cfa5c, 1044 .pads_refclk_cfg1 = 0xfa5cfa5c, 1045 .has_pex_clkreq_en = true, 1046 .has_pex_bias_ctrl = true, 1047 .has_cml_clk = true, 1048 .has_gen2 = false, 1049 }, 1050 [TEGRA124_PCIE] = { 1051 .num_ports = 2, 1052 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1053 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1054 .pads_refclk_cfg0 = 0x44ac44ac, 1055 .has_pex_clkreq_en = true, 1056 .has_pex_bias_ctrl = true, 1057 .has_cml_clk = true, 1058 .has_gen2 = true, 1059 }, 1060 [TEGRA210_PCIE] = { 1061 .num_ports = 2, 1062 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1063 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1064 .pads_refclk_cfg0 = 0x90b890b8, 1065 .has_pex_clkreq_en = true, 1066 .has_pex_bias_ctrl = true, 1067 .has_cml_clk = true, 1068 .has_gen2 = true, 1069 .force_pca_enable = true, 1070 }, 1071 [TEGRA186_PCIE] = { 1072 .num_ports = 3, 1073 .afi_pex2_ctrl = AFI_PEX2_CTRL_T186, 1074 .pads_refclk_cfg0 = 0x80b880b8, 1075 .pads_refclk_cfg1 = 0x000480b8, 1076 .has_pex_clkreq_en = true, 1077 .has_pex_bias_ctrl = true, 1078 .has_gen2 = true, 1079 }, 1080 }; 1081 1082 static int pci_tegra_ofdata_to_platdata(struct udevice *dev) 1083 { 1084 struct tegra_pcie *pcie = dev_get_priv(dev); 1085 enum tegra_pci_id id; 1086 1087 id = dev_get_driver_data(dev); 1088 pcie->soc = &pci_tegra_soc[id]; 1089 1090 INIT_LIST_HEAD(&pcie->ports); 1091 1092 if (tegra_pcie_parse_dt(dev, id, pcie)) 1093 return -EINVAL; 1094 1095 return 0; 1096 } 1097 1098 static int pci_tegra_probe(struct udevice *dev) 1099 { 1100 struct tegra_pcie *pcie = dev_get_priv(dev); 1101 int err; 1102 1103 #ifdef CONFIG_TEGRA186 1104 err = clk_get_by_name(dev, "afi", &pcie->clk_afi); 1105 if (err) { 1106 debug("clk_get_by_name(afi) failed: %d\n", err); 1107 return err; 1108 } 1109 1110 err = clk_get_by_name(dev, "pex", &pcie->clk_pex); 1111 if (err) { 1112 debug("clk_get_by_name(pex) failed: %d\n", err); 1113 return err; 1114 } 1115 1116 err = reset_get_by_name(dev, "afi", &pcie->reset_afi); 1117 if (err) { 1118 debug("reset_get_by_name(afi) failed: %d\n", err); 1119 return err; 1120 } 1121 1122 err = reset_get_by_name(dev, "pex", &pcie->reset_pex); 1123 if (err) { 1124 debug("reset_get_by_name(pex) failed: %d\n", err); 1125 return err; 1126 } 1127 1128 err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x); 1129 if (err) { 1130 debug("reset_get_by_name(pcie_x) failed: %d\n", err); 1131 return err; 1132 } 1133 1134 err = power_domain_get(dev, &pcie->pwrdom); 1135 if (err) { 1136 debug("power_domain_get() failed: %d\n", err); 1137 return err; 1138 } 1139 #endif 1140 1141 err = tegra_pcie_power_on(pcie); 1142 if (err < 0) { 1143 pr_err("failed to power on"); 1144 return err; 1145 } 1146 1147 err = tegra_pcie_enable_controller(pcie); 1148 if (err < 0) { 1149 pr_err("failed to enable controller"); 1150 return err; 1151 } 1152 1153 err = tegra_pcie_setup_translations(dev); 1154 if (err < 0) { 1155 pr_err("failed to decode ranges"); 1156 return err; 1157 } 1158 1159 err = tegra_pcie_enable(pcie); 1160 if (err < 0) { 1161 pr_err("failed to enable PCIe"); 1162 return err; 1163 } 1164 1165 return 0; 1166 } 1167 1168 static const struct dm_pci_ops pci_tegra_ops = { 1169 .read_config = pci_tegra_read_config, 1170 .write_config = pci_tegra_write_config, 1171 }; 1172 1173 static const struct udevice_id pci_tegra_ids[] = { 1174 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE }, 1175 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE }, 1176 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE }, 1177 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE }, 1178 { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE }, 1179 { } 1180 }; 1181 1182 U_BOOT_DRIVER(pci_tegra) = { 1183 .name = "pci_tegra", 1184 .id = UCLASS_PCI, 1185 .of_match = pci_tegra_ids, 1186 .ops = &pci_tegra_ops, 1187 .ofdata_to_platdata = pci_tegra_ofdata_to_platdata, 1188 .probe = pci_tegra_probe, 1189 .priv_auto_alloc_size = sizeof(struct tegra_pcie), 1190 }; 1191