1 /* 2 * SH7780 PCI Controller (PCIC) for U-Boot. 3 * (C) Dustin McIntire (dustin@sensoria.com) 4 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5 * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 28 #include <asm/processor.h> 29 #include <asm/io.h> 30 #include <pci.h> 31 32 #define SH7780_VENDOR_ID 0x1912 33 #define SH7780_DEVICE_ID 0x0002 34 #define SH7780_PCICR_PREFIX 0xA5000000 35 #define SH7780_PCICR_PFCS 0x00000800 36 #define SH7780_PCICR_FTO 0x00000400 37 #define SH7780_PCICR_PFE 0x00000200 38 #define SH7780_PCICR_TBS 0x00000100 39 #define SH7780_PCICR_ARBM 0x00000040 40 #define SH7780_PCICR_IOCS 0x00000004 41 #define SH7780_PCICR_PRST 0x00000002 42 #define SH7780_PCICR_CFIN 0x00000001 43 44 #define p4_in(addr) *((vu_long *)addr) 45 #define p4_out(data,addr) *(vu_long *)(addr) = (data) 46 #define p4_inw(addr) *((vu_short *)addr) 47 #define p4_outw(data,addr) *(vu_short *)(addr) = (data) 48 49 int pci_sh4_read_config_dword(struct pci_controller *hose, 50 pci_dev_t dev, int offset, u32 *value) 51 { 52 u32 par_data = 0x80000000 | dev; 53 54 p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR); 55 *value = p4_in(SH7780_PCIPDR); 56 57 return 0; 58 } 59 60 int pci_sh4_write_config_dword(struct pci_controller *hose, 61 pci_dev_t dev, int offset, u32 value) 62 { 63 u32 par_data = 0x80000000 | dev; 64 65 p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR); 66 p4_out(value, SH7780_PCIPDR); 67 return 0; 68 } 69 70 int pci_sh7780_init(struct pci_controller *hose) 71 { 72 p4_out(0x01, SH7780_PCIECR); 73 74 if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID 75 && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){ 76 printf("PCI: Unknown PCI host bridge.\n"); 77 return; 78 } 79 printf("PCI: SH7780 PCI host bridge found.\n"); 80 81 /* Toggle PCI reset pin */ 82 p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR); 83 udelay(100000); 84 p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR); 85 p4_outw(0x0047, SH7780_PCICMD); 86 87 p4_out(0x07F00001, SH7780_PCILSR0); 88 p4_out(0x08000000, SH7780_PCILAR0); 89 p4_out(0x00000000, SH7780_PCILSR1); 90 p4_out(0, SH7780_PCILAR1); 91 p4_out(0x08000000, SH7780_PCIMBAR0); 92 p4_out(0x00000000, SH7780_PCIMBAR1); 93 94 p4_out(0xFD000000, SH7780_PCIMBR0); 95 p4_out(0x00FC0000, SH7780_PCIMBMR0); 96 97 /* if use Operand Cache then enable PCICSCR Soonp bits. */ 98 p4_out(0x08000000, SH7780_PCICSAR0); 99 p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */ 100 101 p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM 102 | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE), 103 SH7780_PCICR); 104 105 pci_sh4_init(hose); 106 return 0; 107 } 108