1 /* 2 * SH7751 PCI Controller (PCIC) for U-Boot. 3 * (C) Dustin McIntire (dustin@sensoria.com) 4 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <pci.h> 11 #include <asm/processor.h> 12 #include <asm/io.h> 13 #include <asm/pci.h> 14 15 /* Register addresses and such */ 16 #define SH7751_BCR1 (vu_long *)0xFF800000 17 #define SH7751_BCR2 (vu_short *)0xFF800004 18 #define SH7751_WCR1 (vu_long *)0xFF800008 19 #define SH7751_WCR2 (vu_long *)0xFF80000C 20 #define SH7751_WCR3 (vu_long *)0xFF800010 21 #define SH7751_MCR (vu_long *)0xFF800014 22 #define SH7751_BCR3 (vu_short *)0xFF800050 23 #define SH7751_PCICONF0 (vu_long *)0xFE200000 24 #define SH7751_PCICONF1 (vu_long *)0xFE200004 25 #define SH7751_PCICONF2 (vu_long *)0xFE200008 26 #define SH7751_PCICONF3 (vu_long *)0xFE20000C 27 #define SH7751_PCICONF4 (vu_long *)0xFE200010 28 #define SH7751_PCICONF5 (vu_long *)0xFE200014 29 #define SH7751_PCICONF6 (vu_long *)0xFE200018 30 #define SH7751_PCICR (vu_long *)0xFE200100 31 #define SH7751_PCILSR0 (vu_long *)0xFE200104 32 #define SH7751_PCILSR1 (vu_long *)0xFE200108 33 #define SH7751_PCILAR0 (vu_long *)0xFE20010C 34 #define SH7751_PCILAR1 (vu_long *)0xFE200110 35 #define SH7751_PCIMBR (vu_long *)0xFE2001C4 36 #define SH7751_PCIIOBR (vu_long *)0xFE2001C8 37 #define SH7751_PCIPINT (vu_long *)0xFE2001CC 38 #define SH7751_PCIPINTM (vu_long *)0xFE2001D0 39 #define SH7751_PCICLKR (vu_long *)0xFE2001D4 40 #define SH7751_PCIBCR1 (vu_long *)0xFE2001E0 41 #define SH7751_PCIBCR2 (vu_long *)0xFE2001E4 42 #define SH7751_PCIWCR1 (vu_long *)0xFE2001E8 43 #define SH7751_PCIWCR2 (vu_long *)0xFE2001EC 44 #define SH7751_PCIWCR3 (vu_long *)0xFE2001F0 45 #define SH7751_PCIMCR (vu_long *)0xFE2001F4 46 #define SH7751_PCIBCR3 (vu_long *)0xFE2001F8 47 48 #define BCR1_BREQEN 0x00080000 49 #define PCI_SH7751_ID 0x35051054 50 #define PCI_SH7751R_ID 0x350E1054 51 #define SH7751_PCICONF1_WCC 0x00000080 52 #define SH7751_PCICONF1_PER 0x00000040 53 #define SH7751_PCICONF1_BUM 0x00000004 54 #define SH7751_PCICONF1_MES 0x00000002 55 #define SH7751_PCICONF1_CMDS 0x000000C6 56 #define SH7751_PCI_HOST_BRIDGE 0x6 57 #define SH7751_PCICR_PREFIX 0xa5000000 58 #define SH7751_PCICR_PRST 0x00000002 59 #define SH7751_PCICR_CFIN 0x00000001 60 #define SH7751_PCIPINT_D3 0x00000002 61 #define SH7751_PCIPINT_D0 0x00000001 62 #define SH7751_PCICLKR_PREFIX 0xa5000000 63 64 #define SH7751_PCI_MEM_BASE 0xFD000000 65 #define SH7751_PCI_MEM_SIZE 0x01000000 66 #define SH7751_PCI_IO_BASE 0xFE240000 67 #define SH7751_PCI_IO_SIZE 0x00040000 68 69 #define SH7751_PCIPAR (vu_long *)0xFE2001C0 70 #define SH7751_PCIPDR (vu_long *)0xFE200220 71 72 #define p4_in(addr) (*addr) 73 #define p4_out(data, addr) (*addr) = (data) 74 75 /* Double word */ 76 int pci_sh4_read_config_dword(struct pci_controller *hose, 77 pci_dev_t dev, int offset, u32 *value) 78 { 79 u32 par_data = 0x80000000 | dev; 80 81 p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR); 82 *value = p4_in(SH7751_PCIPDR); 83 84 return 0; 85 } 86 87 int pci_sh4_write_config_dword(struct pci_controller *hose, 88 pci_dev_t dev, int offset, u32 value) 89 { 90 u32 par_data = 0x80000000 | dev; 91 92 p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR); 93 p4_out(value, SH7751_PCIPDR); 94 95 return 0; 96 } 97 98 int pci_sh7751_init(struct pci_controller *hose) 99 { 100 /* Double-check that we're a 7751 or 7751R chip */ 101 if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID 102 && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) { 103 printf("PCI: Unknown PCI host bridge.\n"); 104 return 1; 105 } 106 printf("PCI: SH7751 PCI host bridge found.\n"); 107 108 /* Double-check some BSC config settings */ 109 /* (Area 3 non-MPX 32-bit, PCI bus pins) */ 110 if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) { 111 printf("SH7751_BCR1 value is wrong(0x%08X)\n", 112 (unsigned int)p4_in(SH7751_BCR1)); 113 return 2; 114 } 115 if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) { 116 printf("SH7751_BCR2 value is wrong(0x%08X)\n", 117 (unsigned int)p4_in(SH7751_BCR2)); 118 return 3; 119 } 120 if (p4_in(SH7751_BCR2) & 0x01) { 121 printf("SH7751_BCR2 value is wrong(0x%08X)\n", 122 (unsigned int)p4_in(SH7751_BCR2)); 123 return 4; 124 } 125 126 /* Force BREQEN in BCR1 to allow PCIC access */ 127 p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1); 128 129 /* Toggle PCI reset pin */ 130 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR); 131 udelay(32); 132 p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR); 133 134 /* Set cmd bits: WCC, PER, BUM, MES */ 135 /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */ 136 p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */ 137 138 /* Define this host as the host bridge */ 139 p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2); 140 141 /* Force PCI clock(s) on */ 142 p4_out(0, SH7751_PCICLKR); 143 p4_out(0x03, SH7751_PCICLKR); 144 145 /* Clear powerdown IRQs, also mask them (unused) */ 146 p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT); 147 p4_out(0, SH7751_PCIPINTM); 148 149 p4_out(0xab000001, SH7751_PCICONF4); 150 151 /* Set up target memory mappings (for external DMA access) */ 152 /* Map both P0 and P2 range to Area 3 RAM for ease of use */ 153 p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); 154 p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); 155 p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); 156 157 p4_out(0, SH7751_PCILSR1); 158 p4_out(0, SH7751_PCILAR1); 159 p4_out(0xd0000000, SH7751_PCICONF6); 160 161 /* Map memory window to same address on PCI bus */ 162 p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR); 163 164 /* Map IO window to same address on PCI bus */ 165 p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR); 166 167 /* set BREQEN */ 168 p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1); 169 170 /* Copy BSC registers into PCI BSC */ 171 p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1); 172 p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2); 173 p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3); 174 p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1); 175 p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2); 176 p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3); 177 p4_out(inl(SH7751_MCR), SH7751_PCIMCR); 178 179 /* Finally, set central function init complete */ 180 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR); 181 182 pci_sh4_init(hose); 183 184 return 0; 185 } 186