1 /* 2 * SH4 PCI Controller (PCIC) for U-Boot. 3 * (C) Dustin McIntire (dustin@sensoria.com) 4 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5 * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> 6 * 7 * u-boot/arch/sh/cpu/sh4/pci-sh4.c 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 14 #include <asm/processor.h> 15 #include <asm/io.h> 16 #include <asm/pci.h> 17 #include <pci.h> 18 19 int pci_sh4_init(struct pci_controller *hose) 20 { 21 hose->first_busno = 0; 22 hose->region_count = 0; 23 hose->last_busno = 0xff; 24 25 /* PCI memory space */ 26 pci_set_region(hose->regions + 0, 27 CONFIG_PCI_MEM_BUS, 28 CONFIG_PCI_MEM_PHYS, 29 CONFIG_PCI_MEM_SIZE, 30 PCI_REGION_MEM); 31 hose->region_count++; 32 33 /* PCI IO space */ 34 pci_set_region(hose->regions + 1, 35 CONFIG_PCI_IO_BUS, 36 CONFIG_PCI_IO_PHYS, 37 CONFIG_PCI_IO_SIZE, 38 PCI_REGION_IO); 39 hose->region_count++; 40 41 #if defined(CONFIG_PCI_SYS_BUS) 42 /* PCI System Memory space */ 43 pci_set_region(hose->regions + 2, 44 CONFIG_PCI_SYS_BUS, 45 CONFIG_PCI_SYS_PHYS, 46 CONFIG_PCI_SYS_SIZE, 47 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 48 hose->region_count++; 49 #endif 50 51 udelay(1000); 52 53 pci_set_ops(hose, 54 pci_hose_read_config_byte_via_dword, 55 pci_hose_read_config_word_via_dword, 56 pci_sh4_read_config_dword, 57 pci_hose_write_config_byte_via_dword, 58 pci_hose_write_config_word_via_dword, 59 pci_sh4_write_config_dword); 60 61 pci_register_hose(hose); 62 63 udelay(1000); 64 65 #ifdef CONFIG_PCI_SCAN_SHOW 66 printf("PCI: Bus Dev VenId DevId Class Int\n"); 67 #endif 68 hose->last_busno = pci_hose_scan(hose); 69 return 0; 70 } 71 72 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 73 { 74 return 0; 75 } 76 77 #ifdef CONFIG_PCI_SCAN_SHOW 78 int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) 79 { 80 return 1; 81 } 82 #endif /* CONFIG_PCI_SCAN_SHOW */ 83