1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Marvell MVEBU SoCs 4 * 5 * Based on Barebox drivers/pci/pci-mvebu.c 6 * 7 * Ported to U-Boot by: 8 * Anton Schubert <anton.schubert@gmx.de> 9 * Stefan Roese <sr@denx.de> 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <dm/lists.h> 16 #include <dm/of_access.h> 17 #include <pci.h> 18 #include <asm/io.h> 19 #include <asm/arch/cpu.h> 20 #include <asm/arch/soc.h> 21 #include <linux/errno.h> 22 #include <linux/ioport.h> 23 #include <linux/mbus.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /* PCIe unit register offsets */ 28 #define SELECT(x, n) ((x >> n) & 1UL) 29 30 #define PCIE_DEV_ID_OFF 0x0000 31 #define PCIE_CMD_OFF 0x0004 32 #define PCIE_DEV_REV_OFF 0x0008 33 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) 34 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) 35 #define PCIE_CAPAB_OFF 0x0060 36 #define PCIE_CTRL_STAT_OFF 0x0068 37 #define PCIE_HEADER_LOG_4_OFF 0x0128 38 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) 39 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) 40 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) 41 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) 42 #define PCIE_WIN5_CTRL_OFF 0x1880 43 #define PCIE_WIN5_BASE_OFF 0x1884 44 #define PCIE_WIN5_REMAP_OFF 0x188c 45 #define PCIE_CONF_ADDR_OFF 0x18f8 46 #define PCIE_CONF_ADDR_EN BIT(31) 47 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) 48 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) 49 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) 50 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) 51 #define PCIE_CONF_ADDR(dev, reg) \ 52 (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \ 53 PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \ 54 PCIE_CONF_ADDR_EN) 55 #define PCIE_CONF_DATA_OFF 0x18fc 56 #define PCIE_MASK_OFF 0x1910 57 #define PCIE_MASK_ENABLE_INTS (0xf << 24) 58 #define PCIE_CTRL_OFF 0x1a00 59 #define PCIE_CTRL_X1_MODE BIT(0) 60 #define PCIE_STAT_OFF 0x1a04 61 #define PCIE_STAT_BUS (0xff << 8) 62 #define PCIE_STAT_DEV (0x1f << 16) 63 #define PCIE_STAT_LINK_DOWN BIT(0) 64 #define PCIE_DEBUG_CTRL 0x1a60 65 #define PCIE_DEBUG_SOFT_RESET BIT(20) 66 67 struct mvebu_pcie { 68 struct pci_controller hose; 69 void __iomem *base; 70 void __iomem *membase; 71 struct resource mem; 72 void __iomem *iobase; 73 u32 port; 74 u32 lane; 75 int devfn; 76 u32 lane_mask; 77 pci_dev_t dev; 78 char name[16]; 79 unsigned int mem_target; 80 unsigned int mem_attr; 81 }; 82 83 /* 84 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped 85 * into SoCs address space. Each controller will map 128M of MEM 86 * and 64K of I/O space when registered. 87 */ 88 static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE; 89 #define PCIE_MEM_SIZE (128 << 20) 90 91 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) 92 { 93 u32 val; 94 val = readl(pcie->base + PCIE_STAT_OFF); 95 return !(val & PCIE_STAT_LINK_DOWN); 96 } 97 98 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) 99 { 100 u32 stat; 101 102 stat = readl(pcie->base + PCIE_STAT_OFF); 103 stat &= ~PCIE_STAT_BUS; 104 stat |= busno << 8; 105 writel(stat, pcie->base + PCIE_STAT_OFF); 106 } 107 108 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno) 109 { 110 u32 stat; 111 112 stat = readl(pcie->base + PCIE_STAT_OFF); 113 stat &= ~PCIE_STAT_DEV; 114 stat |= devno << 16; 115 writel(stat, pcie->base + PCIE_STAT_OFF); 116 } 117 118 static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie) 119 { 120 u32 stat; 121 122 stat = readl(pcie->base + PCIE_STAT_OFF); 123 return (stat & PCIE_STAT_BUS) >> 8; 124 } 125 126 static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie) 127 { 128 u32 stat; 129 130 stat = readl(pcie->base + PCIE_STAT_OFF); 131 return (stat & PCIE_STAT_DEV) >> 16; 132 } 133 134 static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose) 135 { 136 return container_of(hose, struct mvebu_pcie, hose); 137 } 138 139 static int mvebu_pcie_read_config(struct udevice *bus, pci_dev_t bdf, 140 uint offset, ulong *valuep, 141 enum pci_size_t size) 142 { 143 struct mvebu_pcie *pcie = dev_get_platdata(bus); 144 int local_bus = PCI_BUS(pcie->dev); 145 int local_dev = PCI_DEV(pcie->dev); 146 u32 reg; 147 u32 data; 148 149 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", 150 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 151 152 /* Only allow one other device besides the local one on the local bus */ 153 if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) { 154 if (local_dev == 0 && PCI_DEV(bdf) != 1) { 155 debug("- out of range\n"); 156 /* 157 * If local dev is 0, the first other dev can 158 * only be 1 159 */ 160 *valuep = pci_get_ff(size); 161 return 0; 162 } else if (local_dev != 0 && PCI_DEV(bdf) != 0) { 163 debug("- out of range\n"); 164 /* 165 * If local dev is not 0, the first other dev can 166 * only be 0 167 */ 168 *valuep = pci_get_ff(size); 169 return 0; 170 } 171 } 172 173 /* write address */ 174 reg = PCIE_CONF_ADDR(bdf, offset); 175 writel(reg, pcie->base + PCIE_CONF_ADDR_OFF); 176 data = readl(pcie->base + PCIE_CONF_DATA_OFF); 177 debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data); 178 *valuep = pci_conv_32_to_size(data, offset, size); 179 180 return 0; 181 } 182 183 static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, 184 uint offset, ulong value, 185 enum pci_size_t size) 186 { 187 struct mvebu_pcie *pcie = dev_get_platdata(bus); 188 int local_bus = PCI_BUS(pcie->dev); 189 int local_dev = PCI_DEV(pcie->dev); 190 u32 data; 191 192 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", 193 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 194 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 195 196 /* Only allow one other device besides the local one on the local bus */ 197 if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) { 198 if (local_dev == 0 && PCI_DEV(bdf) != 1) { 199 /* 200 * If local dev is 0, the first other dev can 201 * only be 1 202 */ 203 return 0; 204 } else if (local_dev != 0 && PCI_DEV(bdf) != 0) { 205 /* 206 * If local dev is not 0, the first other dev can 207 * only be 0 208 */ 209 return 0; 210 } 211 } 212 213 writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF); 214 data = pci_conv_size_to_32(0, value, offset, size); 215 writel(data, pcie->base + PCIE_CONF_DATA_OFF); 216 217 return 0; 218 } 219 220 /* 221 * Setup PCIE BARs and Address Decode Wins: 222 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks 223 * WIN[0-3] -> DRAM bank[0-3] 224 */ 225 static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie) 226 { 227 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info(); 228 u32 size; 229 int i; 230 231 /* First, disable and clear BARs and windows. */ 232 for (i = 1; i < 3; i++) { 233 writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i)); 234 writel(0, pcie->base + PCIE_BAR_LO_OFF(i)); 235 writel(0, pcie->base + PCIE_BAR_HI_OFF(i)); 236 } 237 238 for (i = 0; i < 5; i++) { 239 writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i)); 240 writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i)); 241 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i)); 242 } 243 244 writel(0, pcie->base + PCIE_WIN5_CTRL_OFF); 245 writel(0, pcie->base + PCIE_WIN5_BASE_OFF); 246 writel(0, pcie->base + PCIE_WIN5_REMAP_OFF); 247 248 /* Setup windows for DDR banks. Count total DDR size on the fly. */ 249 size = 0; 250 for (i = 0; i < dram->num_cs; i++) { 251 const struct mbus_dram_window *cs = dram->cs + i; 252 253 writel(cs->base & 0xffff0000, 254 pcie->base + PCIE_WIN04_BASE_OFF(i)); 255 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i)); 256 writel(((cs->size - 1) & 0xffff0000) | 257 (cs->mbus_attr << 8) | 258 (dram->mbus_dram_target_id << 4) | 1, 259 pcie->base + PCIE_WIN04_CTRL_OFF(i)); 260 261 size += cs->size; 262 } 263 264 /* Round up 'size' to the nearest power of two. */ 265 if ((size & (size - 1)) != 0) 266 size = 1 << fls(size); 267 268 /* Setup BAR[1] to all DRAM banks. */ 269 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1)); 270 writel(0, pcie->base + PCIE_BAR_HI_OFF(1)); 271 writel(((size - 1) & 0xffff0000) | 0x1, 272 pcie->base + PCIE_BAR_CTRL_OFF(1)); 273 } 274 275 static int mvebu_pcie_probe(struct udevice *dev) 276 { 277 struct mvebu_pcie *pcie = dev_get_platdata(dev); 278 struct udevice *ctlr = pci_get_controller(dev); 279 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 280 static int bus; 281 u32 reg; 282 283 debug("%s: PCIe %d.%d - up, base %08x\n", __func__, 284 pcie->port, pcie->lane, (u32)pcie->base); 285 286 /* Read Id info and local bus/dev */ 287 debug("direct conf read %08x, local bus %d, local dev %d\n", 288 readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie), 289 mvebu_pcie_get_local_dev_nr(pcie)); 290 291 mvebu_pcie_set_local_bus_nr(pcie, bus); 292 mvebu_pcie_set_local_dev_nr(pcie, 0); 293 pcie->dev = PCI_BDF(bus, 0, 0); 294 295 pcie->mem.start = (u32)mvebu_pcie_membase; 296 pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1; 297 mvebu_pcie_membase += PCIE_MEM_SIZE; 298 299 if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr, 300 (phys_addr_t)pcie->mem.start, 301 PCIE_MEM_SIZE)) { 302 printf("PCIe unable to add mbus window for mem at %08x+%08x\n", 303 (u32)pcie->mem.start, PCIE_MEM_SIZE); 304 } 305 306 /* Setup windows and configure host bridge */ 307 mvebu_pcie_setup_wins(pcie); 308 309 /* Master + slave enable. */ 310 reg = readl(pcie->base + PCIE_CMD_OFF); 311 reg |= PCI_COMMAND_MEMORY; 312 reg |= PCI_COMMAND_MASTER; 313 reg |= BIT(10); /* disable interrupts */ 314 writel(reg, pcie->base + PCIE_CMD_OFF); 315 316 /* Set BAR0 to internal registers */ 317 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); 318 writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); 319 320 /* PCI memory space */ 321 pci_set_region(hose->regions + 0, pcie->mem.start, 322 pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM); 323 pci_set_region(hose->regions + 1, 324 0, 0, 325 gd->ram_size, 326 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 327 hose->region_count = 2; 328 329 bus++; 330 331 return 0; 332 } 333 334 static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie) 335 { 336 const u32 *addr; 337 int len; 338 339 addr = ofnode_get_property(node, "assigned-addresses", &len); 340 if (!addr) { 341 pr_err("property \"assigned-addresses\" not found"); 342 return -FDT_ERR_NOTFOUND; 343 } 344 345 pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE); 346 347 return 0; 348 } 349 350 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) 351 #define DT_TYPE_IO 0x1 352 #define DT_TYPE_MEM32 0x2 353 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) 354 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) 355 356 static int mvebu_get_tgt_attr(ofnode node, int devfn, 357 unsigned long type, 358 unsigned int *tgt, 359 unsigned int *attr) 360 { 361 const int na = 3, ns = 2; 362 const __be32 *range; 363 int rlen, nranges, rangesz, pna, i; 364 365 *tgt = -1; 366 *attr = -1; 367 368 range = ofnode_get_property(node, "ranges", &rlen); 369 if (!range) 370 return -EINVAL; 371 372 /* 373 * Linux uses of_n_addr_cells() to get the number of address cells 374 * here. Currently this function is only available in U-Boot when 375 * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in 376 * general, lets't hardcode the "pna" value in the U-Boot code. 377 */ 378 pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */ 379 rangesz = pna + na + ns; 380 nranges = rlen / sizeof(__be32) / rangesz; 381 382 for (i = 0; i < nranges; i++, range += rangesz) { 383 u32 flags = of_read_number(range, 1); 384 u32 slot = of_read_number(range + 1, 1); 385 u64 cpuaddr = of_read_number(range + na, pna); 386 unsigned long rtype; 387 388 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) 389 rtype = IORESOURCE_IO; 390 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) 391 rtype = IORESOURCE_MEM; 392 else 393 continue; 394 395 /* 396 * The Linux code used PCI_SLOT() here, which expects devfn 397 * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(), 398 * only expects devfn in 15..8, where its saved in this driver. 399 */ 400 if (slot == PCI_DEV(devfn) && type == rtype) { 401 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); 402 *attr = DT_CPUADDR_TO_ATTR(cpuaddr); 403 return 0; 404 } 405 } 406 407 return -ENOENT; 408 } 409 410 static int mvebu_pcie_ofdata_to_platdata(struct udevice *dev) 411 { 412 struct mvebu_pcie *pcie = dev_get_platdata(dev); 413 int ret = 0; 414 415 /* Get port number, lane number and memory target / attr */ 416 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port", 417 &pcie->port)) { 418 ret = -ENODEV; 419 goto err; 420 } 421 422 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane)) 423 pcie->lane = 0; 424 425 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane); 426 427 /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */ 428 pcie->devfn = pci_get_devfn(dev); 429 if (pcie->devfn < 0) { 430 ret = -ENODEV; 431 goto err; 432 } 433 434 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn, 435 IORESOURCE_MEM, 436 &pcie->mem_target, &pcie->mem_attr); 437 if (ret < 0) { 438 printf("%s: cannot get tgt/attr for mem window\n", pcie->name); 439 goto err; 440 } 441 442 /* Parse PCIe controller register base from DT */ 443 ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie); 444 if (ret < 0) 445 goto err; 446 447 /* Check link and skip ports that have no link */ 448 if (!mvebu_pcie_link_up(pcie)) { 449 debug("%s: %s - down\n", __func__, pcie->name); 450 ret = -ENODEV; 451 goto err; 452 } 453 454 return 0; 455 456 err: 457 return ret; 458 } 459 460 static const struct dm_pci_ops mvebu_pcie_ops = { 461 .read_config = mvebu_pcie_read_config, 462 .write_config = mvebu_pcie_write_config, 463 }; 464 465 static struct driver pcie_mvebu_drv = { 466 .name = "pcie_mvebu", 467 .id = UCLASS_PCI, 468 .ops = &mvebu_pcie_ops, 469 .probe = mvebu_pcie_probe, 470 .ofdata_to_platdata = mvebu_pcie_ofdata_to_platdata, 471 .platdata_auto_alloc_size = sizeof(struct mvebu_pcie), 472 }; 473 474 /* 475 * Use a MISC device to bind the n instances (child nodes) of the 476 * PCIe base controller in UCLASS_PCI. 477 */ 478 static int mvebu_pcie_bind(struct udevice *parent) 479 { 480 struct mvebu_pcie *pcie; 481 struct uclass_driver *drv; 482 struct udevice *dev; 483 ofnode subnode; 484 485 /* Lookup eth driver */ 486 drv = lists_uclass_lookup(UCLASS_PCI); 487 if (!drv) { 488 puts("Cannot find PCI driver\n"); 489 return -ENOENT; 490 } 491 492 ofnode_for_each_subnode(subnode, dev_ofnode(parent)) { 493 if (!ofnode_is_available(subnode)) 494 continue; 495 496 pcie = calloc(1, sizeof(*pcie)); 497 if (!pcie) 498 return -ENOMEM; 499 500 /* Create child device UCLASS_PCI and bind it */ 501 device_bind_ofnode(parent, &pcie_mvebu_drv, pcie->name, pcie, 502 subnode, &dev); 503 } 504 505 return 0; 506 } 507 508 static const struct udevice_id mvebu_pcie_ids[] = { 509 { .compatible = "marvell,armada-xp-pcie" }, 510 { .compatible = "marvell,armada-370-pcie" }, 511 { } 512 }; 513 514 U_BOOT_DRIVER(pcie_mvebu_base) = { 515 .name = "pcie_mvebu_base", 516 .id = UCLASS_MISC, 517 .of_match = mvebu_pcie_ids, 518 .bind = mvebu_pcie_bind, 519 }; 520