1 /* 2 * arch/powerpc/kernel/pci_auto.c 3 * 4 * PCI autoconfiguration library 5 * 6 * Author: Matt Porter <mporter@mvista.com> 7 * 8 * Copyright 2000 MontaVista Software Inc. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <pci.h> 16 17 #undef DEBUG 18 #ifdef DEBUG 19 #define DEBUGF(x...) printf(x) 20 #else 21 #define DEBUGF(x...) 22 #endif /* DEBUG */ 23 24 #define PCIAUTO_IDE_MODE_MASK 0x05 25 26 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ 27 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE 28 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 29 #endif 30 31 /* 32 * 33 */ 34 35 void pciauto_region_init(struct pci_region *res) 36 { 37 /* 38 * Avoid allocating PCI resources from address 0 -- this is illegal 39 * according to PCI 2.1 and moreover, this is known to cause Linux IDE 40 * drivers to fail. Use a reasonable starting value of 0x1000 instead. 41 */ 42 res->bus_lower = res->bus_start ? res->bus_start : 0x1000; 43 } 44 45 void pciauto_region_align(struct pci_region *res, pci_size_t size) 46 { 47 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; 48 } 49 50 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 51 pci_addr_t *bar) 52 { 53 pci_addr_t addr; 54 55 if (!res) { 56 DEBUGF("No resource"); 57 goto error; 58 } 59 60 addr = ((res->bus_lower - 1) | (size - 1)) + 1; 61 62 if (addr - res->bus_start + size > res->size) { 63 DEBUGF("No room in resource"); 64 goto error; 65 } 66 67 res->bus_lower = addr + size; 68 69 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower); 70 71 *bar = addr; 72 return 0; 73 74 error: 75 *bar = (pci_addr_t)-1; 76 return -1; 77 } 78 79 /* 80 * 81 */ 82 83 void pciauto_setup_device(struct pci_controller *hose, 84 pci_dev_t dev, int bars_num, 85 struct pci_region *mem, 86 struct pci_region *prefetch, 87 struct pci_region *io) 88 { 89 u32 bar_response; 90 pci_size_t bar_size; 91 u16 cmdstat = 0; 92 int bar, bar_nr = 0; 93 #ifndef CONFIG_PCI_ENUM_ONLY 94 pci_addr_t bar_value; 95 struct pci_region *bar_res; 96 int found_mem64 = 0; 97 #endif 98 99 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 100 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; 101 102 for (bar = PCI_BASE_ADDRESS_0; 103 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { 104 /* Tickle the BAR and get the response */ 105 #ifndef CONFIG_PCI_ENUM_ONLY 106 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 107 #endif 108 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 109 110 /* If BAR is not implemented go to the next BAR */ 111 if (!bar_response) 112 continue; 113 114 #ifndef CONFIG_PCI_ENUM_ONLY 115 found_mem64 = 0; 116 #endif 117 118 /* Check the BAR type and set our address mask */ 119 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 120 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 121 & 0xffff) + 1; 122 #ifndef CONFIG_PCI_ENUM_ONLY 123 bar_res = io; 124 #endif 125 126 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size); 127 } else { 128 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 129 PCI_BASE_ADDRESS_MEM_TYPE_64) { 130 u32 bar_response_upper; 131 u64 bar64; 132 133 #ifndef CONFIG_PCI_ENUM_ONLY 134 pci_hose_write_config_dword(hose, dev, bar + 4, 135 0xffffffff); 136 #endif 137 pci_hose_read_config_dword(hose, dev, bar + 4, 138 &bar_response_upper); 139 140 bar64 = ((u64)bar_response_upper << 32) | bar_response; 141 142 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 143 #ifndef CONFIG_PCI_ENUM_ONLY 144 found_mem64 = 1; 145 #endif 146 } else { 147 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 148 } 149 #ifndef CONFIG_PCI_ENUM_ONLY 150 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) 151 bar_res = prefetch; 152 else 153 bar_res = mem; 154 #endif 155 156 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size); 157 } 158 159 #ifndef CONFIG_PCI_ENUM_ONLY 160 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) { 161 /* Write it out and update our limit */ 162 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value); 163 164 if (found_mem64) { 165 bar += 4; 166 #ifdef CONFIG_SYS_PCI_64BIT 167 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32)); 168 #else 169 /* 170 * If we are a 64-bit decoder then increment to the 171 * upper 32 bits of the bar and force it to locate 172 * in the lower 4GB of memory. 173 */ 174 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 175 #endif 176 } 177 178 } 179 #endif 180 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 181 PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 182 183 DEBUGF("\n"); 184 185 bar_nr++; 186 } 187 188 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); 189 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 190 CONFIG_SYS_PCI_CACHE_LINE_SIZE); 191 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 192 } 193 194 int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev) 195 { 196 pci_addr_t bar_value; 197 pci_size_t bar_size; 198 u32 bar_response; 199 u16 cmdstat = 0; 200 201 pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe); 202 pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response); 203 if (!bar_response) 204 return -ENOENT; 205 206 bar_size = -(bar_response & ~1); 207 DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size); 208 if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) { 209 pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 210 bar_value); 211 } 212 DEBUGF("\n"); 213 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 214 cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 215 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); 216 217 return 0; 218 } 219 220 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 221 pci_dev_t dev, int sub_bus) 222 { 223 struct pci_region *pci_mem = hose->pci_mem; 224 struct pci_region *pci_prefetch = hose->pci_prefetch; 225 struct pci_region *pci_io = hose->pci_io; 226 u16 cmdstat, prefechable_64; 227 228 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 229 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 230 &prefechable_64); 231 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 232 233 /* Configure bus number registers */ 234 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, 235 PCI_BUS(dev) - hose->first_busno); 236 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, 237 sub_bus - hose->first_busno); 238 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); 239 240 if (pci_mem) { 241 /* Round memory allocator to 1MB boundary */ 242 pciauto_region_align(pci_mem, 0x100000); 243 244 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 245 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, 246 (pci_mem->bus_lower & 0xfff00000) >> 16); 247 248 cmdstat |= PCI_COMMAND_MEMORY; 249 } 250 251 if (pci_prefetch) { 252 /* Round memory allocator to 1MB boundary */ 253 pciauto_region_align(pci_prefetch, 0x100000); 254 255 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 256 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 257 (pci_prefetch->bus_lower & 0xfff00000) >> 16); 258 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 259 #ifdef CONFIG_SYS_PCI_64BIT 260 pci_hose_write_config_dword(hose, dev, 261 PCI_PREF_BASE_UPPER32, 262 pci_prefetch->bus_lower >> 32); 263 #else 264 pci_hose_write_config_dword(hose, dev, 265 PCI_PREF_BASE_UPPER32, 266 0x0); 267 #endif 268 269 cmdstat |= PCI_COMMAND_MEMORY; 270 } else { 271 /* We don't support prefetchable memory for now, so disable */ 272 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); 273 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); 274 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { 275 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0); 276 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0); 277 } 278 } 279 280 if (pci_io) { 281 /* Round I/O allocator to 4KB boundary */ 282 pciauto_region_align(pci_io, 0x1000); 283 284 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, 285 (pci_io->bus_lower & 0x0000f000) >> 8); 286 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, 287 (pci_io->bus_lower & 0xffff0000) >> 16); 288 289 cmdstat |= PCI_COMMAND_IO; 290 } 291 292 /* Enable memory and I/O accesses, enable bus master */ 293 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 294 cmdstat | PCI_COMMAND_MASTER); 295 } 296 297 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 298 pci_dev_t dev, int sub_bus) 299 { 300 struct pci_region *pci_mem = hose->pci_mem; 301 struct pci_region *pci_prefetch = hose->pci_prefetch; 302 struct pci_region *pci_io = hose->pci_io; 303 304 /* Configure bus number registers */ 305 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 306 sub_bus - hose->first_busno); 307 308 if (pci_mem) { 309 /* Round memory allocator to 1MB boundary */ 310 pciauto_region_align(pci_mem, 0x100000); 311 312 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, 313 (pci_mem->bus_lower - 1) >> 16); 314 } 315 316 if (pci_prefetch) { 317 u16 prefechable_64; 318 319 pci_hose_read_config_word(hose, dev, 320 PCI_PREF_MEMORY_LIMIT, 321 &prefechable_64); 322 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 323 324 /* Round memory allocator to 1MB boundary */ 325 pciauto_region_align(pci_prefetch, 0x100000); 326 327 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 328 (pci_prefetch->bus_lower - 1) >> 16); 329 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 330 #ifdef CONFIG_SYS_PCI_64BIT 331 pci_hose_write_config_dword(hose, dev, 332 PCI_PREF_LIMIT_UPPER32, 333 (pci_prefetch->bus_lower - 1) >> 32); 334 #else 335 pci_hose_write_config_dword(hose, dev, 336 PCI_PREF_LIMIT_UPPER32, 337 0x0); 338 #endif 339 } 340 341 if (pci_io) { 342 /* Round I/O allocator to 4KB boundary */ 343 pciauto_region_align(pci_io, 0x1000); 344 345 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, 346 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); 347 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, 348 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); 349 } 350 } 351 352 /* 353 * 354 */ 355 356 void pciauto_config_init(struct pci_controller *hose) 357 { 358 int i; 359 360 hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL; 361 362 for (i = 0; i < hose->region_count; i++) { 363 switch(hose->regions[i].flags) { 364 case PCI_REGION_IO: 365 if (!hose->pci_io || 366 hose->pci_io->size < hose->regions[i].size) 367 hose->pci_io = hose->regions + i; 368 break; 369 case PCI_REGION_MEM: 370 if (!hose->pci_mem || 371 hose->pci_mem->size < hose->regions[i].size) 372 hose->pci_mem = hose->regions + i; 373 break; 374 case (PCI_REGION_MEM | PCI_REGION_PREFETCH): 375 if (!hose->pci_prefetch || 376 hose->pci_prefetch->size < hose->regions[i].size) 377 hose->pci_prefetch = hose->regions + i; 378 break; 379 } 380 } 381 382 383 if (hose->pci_mem) { 384 pciauto_region_init(hose->pci_mem); 385 386 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n" 387 "\t\tPhysical Memory [%llx-%llxx]\n", 388 (u64)hose->pci_mem->bus_start, 389 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1), 390 (u64)hose->pci_mem->phys_start, 391 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1)); 392 } 393 394 if (hose->pci_prefetch) { 395 pciauto_region_init(hose->pci_prefetch); 396 397 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n" 398 "\t\tPhysical Memory [%llx-%llx]\n", 399 (u64)hose->pci_prefetch->bus_start, 400 (u64)(hose->pci_prefetch->bus_start + 401 hose->pci_prefetch->size - 1), 402 (u64)hose->pci_prefetch->phys_start, 403 (u64)(hose->pci_prefetch->phys_start + 404 hose->pci_prefetch->size - 1)); 405 } 406 407 if (hose->pci_io) { 408 pciauto_region_init(hose->pci_io); 409 410 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n" 411 "\t\tPhysical Memory: [%llx-%llx]\n", 412 (u64)hose->pci_io->bus_start, 413 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1), 414 (u64)hose->pci_io->phys_start, 415 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1)); 416 417 } 418 } 419 420 /* 421 * HJF: Changed this to return int. I think this is required 422 * to get the correct result when scanning bridges 423 */ 424 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) 425 { 426 unsigned int sub_bus = PCI_BUS(dev); 427 unsigned short class; 428 unsigned char prg_iface; 429 int n; 430 431 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 432 433 switch (class) { 434 case PCI_CLASS_BRIDGE_PCI: 435 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", 436 PCI_DEV(dev)); 437 438 pciauto_setup_device(hose, dev, 2, hose->pci_mem, 439 hose->pci_prefetch, hose->pci_io); 440 441 #ifdef CONFIG_DM_PCI 442 n = dm_pci_hose_probe_bus(hose, dev); 443 if (n < 0) 444 return n; 445 sub_bus = (unsigned int)n; 446 #else 447 /* Passing in current_busno allows for sibling P2P bridges */ 448 hose->current_busno++; 449 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 450 /* 451 * need to figure out if this is a subordinate bridge on the bus 452 * to be able to properly set the pri/sec/sub bridge registers. 453 */ 454 n = pci_hose_scan_bus(hose, hose->current_busno); 455 456 /* figure out the deepest we've gone for this leg */ 457 sub_bus = max((unsigned int)n, sub_bus); 458 pciauto_postscan_setup_bridge(hose, dev, sub_bus); 459 460 sub_bus = hose->current_busno; 461 #endif 462 break; 463 464 case PCI_CLASS_STORAGE_IDE: 465 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); 466 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { 467 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n"); 468 return sub_bus; 469 } 470 471 pciauto_setup_device(hose, dev, 6, hose->pci_mem, 472 hose->pci_prefetch, hose->pci_io); 473 break; 474 475 case PCI_CLASS_BRIDGE_CARDBUS: 476 /* 477 * just do a minimal setup of the bridge, 478 * let the OS take care of the rest 479 */ 480 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 481 hose->pci_prefetch, hose->pci_io); 482 483 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", 484 PCI_DEV(dev)); 485 486 #ifndef CONFIG_DM_PCI 487 hose->current_busno++; 488 #endif 489 break; 490 491 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) 492 case PCI_CLASS_BRIDGE_OTHER: 493 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n", 494 PCI_DEV(dev)); 495 break; 496 #endif 497 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) 498 case PCI_CLASS_BRIDGE_OTHER: 499 /* 500 * The host/PCI bridge 1 seems broken in 8349 - it presents 501 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 502 * device claiming resources io/mem/irq.. we only allow for 503 * the PIMMR window to be allocated (BAR0 - 1MB size) 504 */ 505 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n"); 506 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 507 hose->pci_prefetch, hose->pci_io); 508 break; 509 #endif 510 511 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 512 DEBUGF("PCI AutoConfig: Found PowerPC device\n"); 513 514 default: 515 pciauto_setup_device(hose, dev, 6, hose->pci_mem, 516 hose->pci_prefetch, hose->pci_io); 517 break; 518 } 519 520 return sub_bus; 521 } 522