1 /* 2 * arch/powerpc/kernel/pci_auto.c 3 * 4 * PCI autoconfiguration library 5 * 6 * Author: Matt Porter <mporter@mvista.com> 7 * 8 * Copyright 2000 MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #include <common.h> 17 18 #include <pci.h> 19 20 #undef DEBUG 21 #ifdef DEBUG 22 #define DEBUGF(x...) printf(x) 23 #else 24 #define DEBUGF(x...) 25 #endif /* DEBUG */ 26 27 #define PCIAUTO_IDE_MODE_MASK 0x05 28 29 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ 30 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE 31 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 32 #endif 33 34 /* 35 * 36 */ 37 38 void pciauto_region_init(struct pci_region *res) 39 { 40 /* 41 * Avoid allocating PCI resources from address 0 -- this is illegal 42 * according to PCI 2.1 and moreover, this is known to cause Linux IDE 43 * drivers to fail. Use a reasonable starting value of 0x1000 instead. 44 */ 45 res->bus_lower = res->bus_start ? res->bus_start : 0x1000; 46 } 47 48 void pciauto_region_align(struct pci_region *res, pci_size_t size) 49 { 50 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; 51 } 52 53 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 54 pci_addr_t *bar) 55 { 56 pci_addr_t addr; 57 58 if (!res) { 59 DEBUGF("No resource"); 60 goto error; 61 } 62 63 addr = ((res->bus_lower - 1) | (size - 1)) + 1; 64 65 if (addr - res->bus_start + size > res->size) { 66 DEBUGF("No room in resource"); 67 goto error; 68 } 69 70 res->bus_lower = addr + size; 71 72 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower); 73 74 *bar = addr; 75 return 0; 76 77 error: 78 *bar = (pci_addr_t)-1; 79 return -1; 80 } 81 82 /* 83 * 84 */ 85 86 void pciauto_setup_device(struct pci_controller *hose, 87 pci_dev_t dev, int bars_num, 88 struct pci_region *mem, 89 struct pci_region *prefetch, 90 struct pci_region *io) 91 { 92 u32 bar_response; 93 pci_size_t bar_size; 94 u16 cmdstat = 0; 95 int bar, bar_nr = 0; 96 #ifndef CONFIG_PCI_ENUM_ONLY 97 pci_addr_t bar_value; 98 struct pci_region *bar_res; 99 int found_mem64 = 0; 100 #endif 101 102 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 103 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; 104 105 for (bar = PCI_BASE_ADDRESS_0; 106 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { 107 /* Tickle the BAR and get the response */ 108 #ifndef CONFIG_PCI_ENUM_ONLY 109 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 110 #endif 111 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 112 113 /* If BAR is not implemented go to the next BAR */ 114 if (!bar_response) 115 continue; 116 117 #ifndef CONFIG_PCI_ENUM_ONLY 118 found_mem64 = 0; 119 #endif 120 121 /* Check the BAR type and set our address mask */ 122 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 123 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 124 & 0xffff) + 1; 125 #ifndef CONFIG_PCI_ENUM_ONLY 126 bar_res = io; 127 #endif 128 129 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size); 130 } else { 131 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 132 PCI_BASE_ADDRESS_MEM_TYPE_64) { 133 u32 bar_response_upper; 134 u64 bar64; 135 136 #ifndef CONFIG_PCI_ENUM_ONLY 137 pci_hose_write_config_dword(hose, dev, bar + 4, 138 0xffffffff); 139 #endif 140 pci_hose_read_config_dword(hose, dev, bar + 4, 141 &bar_response_upper); 142 143 bar64 = ((u64)bar_response_upper << 32) | bar_response; 144 145 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 146 #ifndef CONFIG_PCI_ENUM_ONLY 147 found_mem64 = 1; 148 #endif 149 } else { 150 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 151 } 152 #ifndef CONFIG_PCI_ENUM_ONLY 153 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) 154 bar_res = prefetch; 155 else 156 bar_res = mem; 157 #endif 158 159 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size); 160 } 161 162 #ifndef CONFIG_PCI_ENUM_ONLY 163 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) { 164 /* Write it out and update our limit */ 165 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value); 166 167 if (found_mem64) { 168 bar += 4; 169 #ifdef CONFIG_SYS_PCI_64BIT 170 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32)); 171 #else 172 /* 173 * If we are a 64-bit decoder then increment to the 174 * upper 32 bits of the bar and force it to locate 175 * in the lower 4GB of memory. 176 */ 177 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 178 #endif 179 } 180 181 } 182 #endif 183 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 184 PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 185 186 DEBUGF("\n"); 187 188 bar_nr++; 189 } 190 191 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); 192 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 193 CONFIG_SYS_PCI_CACHE_LINE_SIZE); 194 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 195 } 196 197 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 198 pci_dev_t dev, int sub_bus) 199 { 200 struct pci_region *pci_mem = hose->pci_mem; 201 struct pci_region *pci_prefetch = hose->pci_prefetch; 202 struct pci_region *pci_io = hose->pci_io; 203 u16 cmdstat; 204 205 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 206 207 /* Configure bus number registers */ 208 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, 209 PCI_BUS(dev) - hose->first_busno); 210 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, 211 sub_bus - hose->first_busno); 212 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); 213 214 if (pci_mem) { 215 /* Round memory allocator to 1MB boundary */ 216 pciauto_region_align(pci_mem, 0x100000); 217 218 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 219 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, 220 (pci_mem->bus_lower & 0xfff00000) >> 16); 221 222 cmdstat |= PCI_COMMAND_MEMORY; 223 } 224 225 if (pci_prefetch) { 226 /* Round memory allocator to 1MB boundary */ 227 pciauto_region_align(pci_prefetch, 0x100000); 228 229 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 230 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 231 (pci_prefetch->bus_lower & 0xfff00000) >> 16); 232 233 cmdstat |= PCI_COMMAND_MEMORY; 234 } else { 235 /* We don't support prefetchable memory for now, so disable */ 236 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); 237 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); 238 } 239 240 if (pci_io) { 241 /* Round I/O allocator to 4KB boundary */ 242 pciauto_region_align(pci_io, 0x1000); 243 244 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, 245 (pci_io->bus_lower & 0x0000f000) >> 8); 246 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, 247 (pci_io->bus_lower & 0xffff0000) >> 16); 248 249 cmdstat |= PCI_COMMAND_IO; 250 } 251 252 /* Enable memory and I/O accesses, enable bus master */ 253 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 254 cmdstat | PCI_COMMAND_MASTER); 255 } 256 257 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 258 pci_dev_t dev, int sub_bus) 259 { 260 struct pci_region *pci_mem = hose->pci_mem; 261 struct pci_region *pci_prefetch = hose->pci_prefetch; 262 struct pci_region *pci_io = hose->pci_io; 263 264 /* Configure bus number registers */ 265 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 266 sub_bus - hose->first_busno); 267 268 if (pci_mem) { 269 /* Round memory allocator to 1MB boundary */ 270 pciauto_region_align(pci_mem, 0x100000); 271 272 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, 273 (pci_mem->bus_lower - 1) >> 16); 274 } 275 276 if (pci_prefetch) { 277 /* Round memory allocator to 1MB boundary */ 278 pciauto_region_align(pci_prefetch, 0x100000); 279 280 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 281 (pci_prefetch->bus_lower - 1) >> 16); 282 } 283 284 if (pci_io) { 285 /* Round I/O allocator to 4KB boundary */ 286 pciauto_region_align(pci_io, 0x1000); 287 288 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, 289 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); 290 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, 291 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); 292 } 293 } 294 295 /* 296 * 297 */ 298 299 void pciauto_config_init(struct pci_controller *hose) 300 { 301 int i; 302 303 hose->pci_io = hose->pci_mem = NULL; 304 305 for (i = 0; i < hose->region_count; i++) { 306 switch(hose->regions[i].flags) { 307 case PCI_REGION_IO: 308 if (!hose->pci_io || 309 hose->pci_io->size < hose->regions[i].size) 310 hose->pci_io = hose->regions + i; 311 break; 312 case PCI_REGION_MEM: 313 if (!hose->pci_mem || 314 hose->pci_mem->size < hose->regions[i].size) 315 hose->pci_mem = hose->regions + i; 316 break; 317 case (PCI_REGION_MEM | PCI_REGION_PREFETCH): 318 if (!hose->pci_prefetch || 319 hose->pci_prefetch->size < hose->regions[i].size) 320 hose->pci_prefetch = hose->regions + i; 321 break; 322 } 323 } 324 325 326 if (hose->pci_mem) { 327 pciauto_region_init(hose->pci_mem); 328 329 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n" 330 "\t\tPhysical Memory [%llx-%llxx]\n", 331 (u64)hose->pci_mem->bus_start, 332 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1), 333 (u64)hose->pci_mem->phys_start, 334 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1)); 335 } 336 337 if (hose->pci_prefetch) { 338 pciauto_region_init(hose->pci_prefetch); 339 340 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n" 341 "\t\tPhysical Memory [%llx-%llx]\n", 342 (u64)hose->pci_prefetch->bus_start, 343 (u64)(hose->pci_prefetch->bus_start + 344 hose->pci_prefetch->size - 1), 345 (u64)hose->pci_prefetch->phys_start, 346 (u64)(hose->pci_prefetch->phys_start + 347 hose->pci_prefetch->size - 1)); 348 } 349 350 if (hose->pci_io) { 351 pciauto_region_init(hose->pci_io); 352 353 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n" 354 "\t\tPhysical Memory: [%llx-%llx]\n", 355 (u64)hose->pci_io->bus_start, 356 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1), 357 (u64)hose->pci_io->phys_start, 358 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1)); 359 360 } 361 } 362 363 /* 364 * HJF: Changed this to return int. I think this is required 365 * to get the correct result when scanning bridges 366 */ 367 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) 368 { 369 unsigned int sub_bus = PCI_BUS(dev); 370 unsigned short class; 371 unsigned char prg_iface; 372 int n; 373 374 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 375 376 switch (class) { 377 case PCI_CLASS_BRIDGE_PCI: 378 hose->current_busno++; 379 pciauto_setup_device(hose, dev, 2, hose->pci_mem, 380 hose->pci_prefetch, hose->pci_io); 381 382 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); 383 384 /* Passing in current_busno allows for sibling P2P bridges */ 385 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 386 /* 387 * need to figure out if this is a subordinate bridge on the bus 388 * to be able to properly set the pri/sec/sub bridge registers. 389 */ 390 n = pci_hose_scan_bus(hose, hose->current_busno); 391 392 /* figure out the deepest we've gone for this leg */ 393 sub_bus = max(n, sub_bus); 394 pciauto_postscan_setup_bridge(hose, dev, sub_bus); 395 396 sub_bus = hose->current_busno; 397 break; 398 399 case PCI_CLASS_STORAGE_IDE: 400 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); 401 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { 402 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n"); 403 return sub_bus; 404 } 405 406 pciauto_setup_device(hose, dev, 6, hose->pci_mem, 407 hose->pci_prefetch, hose->pci_io); 408 break; 409 410 case PCI_CLASS_BRIDGE_CARDBUS: 411 /* 412 * just do a minimal setup of the bridge, 413 * let the OS take care of the rest 414 */ 415 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 416 hose->pci_prefetch, hose->pci_io); 417 418 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", 419 PCI_DEV(dev)); 420 421 hose->current_busno++; 422 break; 423 424 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) 425 case PCI_CLASS_BRIDGE_OTHER: 426 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n", 427 PCI_DEV(dev)); 428 break; 429 #endif 430 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) 431 case PCI_CLASS_BRIDGE_OTHER: 432 /* 433 * The host/PCI bridge 1 seems broken in 8349 - it presents 434 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 435 * device claiming resources io/mem/irq.. we only allow for 436 * the PIMMR window to be allocated (BAR0 - 1MB size) 437 */ 438 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n"); 439 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 440 hose->pci_prefetch, hose->pci_io); 441 break; 442 #endif 443 444 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 445 DEBUGF("PCI AutoConfig: Found PowerPC device\n"); 446 447 default: 448 pciauto_setup_device(hose, dev, 6, hose->pci_mem, 449 hose->pci_prefetch, hose->pci_io); 450 break; 451 } 452 453 return sub_bus; 454 } 455