1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCI autoconfiguration library 4 * 5 * Author: Matt Porter <mporter@mvista.com> 6 * 7 * Copyright 2000 MontaVista Software Inc. 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <pci.h> 14 15 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ 16 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE 17 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 18 #endif 19 20 void dm_pciauto_setup_device(struct udevice *dev, int bars_num, 21 struct pci_region *mem, 22 struct pci_region *prefetch, struct pci_region *io, 23 bool enum_only) 24 { 25 u32 bar_response; 26 pci_size_t bar_size; 27 u16 cmdstat = 0; 28 int bar, bar_nr = 0; 29 u8 header_type; 30 int rom_addr; 31 pci_addr_t bar_value; 32 struct pci_region *bar_res = NULL; 33 int found_mem64 = 0; 34 u16 class; 35 36 aspeed_pcie_workaround(); 37 38 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); 39 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | 40 PCI_COMMAND_MASTER; 41 42 for (bar = PCI_BASE_ADDRESS_0; 43 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { 44 /* Tickle the BAR and get the response */ 45 if (!enum_only) 46 dm_pci_write_config32(dev, bar, 0xffffffff); 47 dm_pci_read_config32(dev, bar, &bar_response); 48 49 /* If BAR is not implemented go to the next BAR */ 50 if (!bar_response) 51 continue; 52 53 found_mem64 = 0; 54 55 /* Check the BAR type and set our address mask */ 56 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 57 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 58 & 0xffff) + 1; 59 if (!enum_only) 60 bar_res = io; 61 62 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", 63 bar_nr, (unsigned long long)bar_size); 64 } else { 65 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 66 PCI_BASE_ADDRESS_MEM_TYPE_64) { 67 u32 bar_response_upper; 68 u64 bar64; 69 70 if (!enum_only) { 71 dm_pci_write_config32(dev, bar + 4, 72 0xffffffff); 73 } 74 dm_pci_read_config32(dev, bar + 4, 75 &bar_response_upper); 76 77 bar64 = ((u64)bar_response_upper << 32) | 78 bar_response; 79 80 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) 81 + 1; 82 if (!enum_only) 83 found_mem64 = 1; 84 } else { 85 bar_size = (u32)(~(bar_response & 86 PCI_BASE_ADDRESS_MEM_MASK) + 1); 87 } 88 if (!enum_only) { 89 if (prefetch && (bar_response & 90 PCI_BASE_ADDRESS_MEM_PREFETCH)) { 91 bar_res = prefetch; 92 } else { 93 bar_res = mem; 94 } 95 } 96 97 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", 98 bar_nr, bar_res == prefetch ? "Prf" : "Mem", 99 (unsigned long long)bar_size); 100 } 101 102 if (!enum_only && pciauto_region_allocate(bar_res, bar_size, 103 &bar_value, 104 found_mem64) == 0) { 105 /* Write it out and update our limit */ 106 dm_pci_write_config32(dev, bar, (u32)bar_value); 107 108 if (found_mem64) { 109 bar += 4; 110 #ifdef CONFIG_SYS_PCI_64BIT 111 dm_pci_write_config32(dev, bar, 112 (u32)(bar_value >> 32)); 113 #else 114 /* 115 * If we are a 64-bit decoder then increment to 116 * the upper 32 bits of the bar and force it to 117 * locate in the lower 4GB of memory. 118 */ 119 dm_pci_write_config32(dev, bar, 0x00000000); 120 #endif 121 } 122 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 123 PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 124 } 125 126 debug("\n"); 127 128 bar_nr++; 129 } 130 131 if (!enum_only) { 132 /* Configure the expansion ROM address */ 133 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); 134 header_type &= 0x7f; 135 if (header_type != PCI_HEADER_TYPE_CARDBUS) { 136 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? 137 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; 138 dm_pci_write_config32(dev, rom_addr, 0xfffffffe); 139 dm_pci_read_config32(dev, rom_addr, &bar_response); 140 if (bar_response) { 141 bar_size = -(bar_response & ~1); 142 debug("PCI Autoconfig: ROM, size=%#x, ", 143 (unsigned int)bar_size); 144 if (pciauto_region_allocate(mem, bar_size, 145 &bar_value, 146 false) == 0) { 147 dm_pci_write_config32(dev, rom_addr, 148 bar_value); 149 } 150 cmdstat |= PCI_COMMAND_MEMORY; 151 debug("\n"); 152 } 153 } 154 } 155 156 /* PCI_COMMAND_IO must be set for VGA device */ 157 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); 158 if (class == PCI_CLASS_DISPLAY_VGA) 159 cmdstat |= PCI_COMMAND_IO; 160 161 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat); 162 dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 163 CONFIG_SYS_PCI_CACHE_LINE_SIZE); 164 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); 165 } 166 167 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) 168 { 169 struct pci_region *pci_mem; 170 struct pci_region *pci_prefetch; 171 struct pci_region *pci_io; 172 u16 cmdstat, prefechable_64; 173 struct udevice *ctlr = pci_get_controller(dev); 174 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 175 176 pci_mem = ctlr_hose->pci_mem; 177 pci_prefetch = ctlr_hose->pci_prefetch; 178 pci_io = ctlr_hose->pci_io; 179 180 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); 181 dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); 182 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 183 184 /* Configure bus number registers */ 185 dm_pci_write_config8(dev, PCI_PRIMARY_BUS, 186 PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq); 187 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq); 188 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); 189 190 if (pci_mem) { 191 /* Round memory allocator to 1MB boundary */ 192 pciauto_region_align(pci_mem, 0x100000); 193 194 /* 195 * Set up memory and I/O filter limits, assume 32-bit 196 * I/O space 197 */ 198 dm_pci_write_config16(dev, PCI_MEMORY_BASE, 199 (pci_mem->bus_lower & 0xfff00000) >> 16); 200 201 cmdstat |= PCI_COMMAND_MEMORY; 202 } 203 204 if (pci_prefetch) { 205 /* Round memory allocator to 1MB boundary */ 206 pciauto_region_align(pci_prefetch, 0x100000); 207 208 /* 209 * Set up memory and I/O filter limits, assume 32-bit 210 * I/O space 211 */ 212 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 213 (pci_prefetch->bus_lower & 0xfff00000) >> 16); 214 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 215 #ifdef CONFIG_SYS_PCI_64BIT 216 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 217 pci_prefetch->bus_lower >> 32); 218 #else 219 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0); 220 #endif 221 222 cmdstat |= PCI_COMMAND_MEMORY; 223 } else { 224 /* We don't support prefetchable memory for now, so disable */ 225 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); 226 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); 227 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { 228 dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); 229 dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); 230 } 231 } 232 233 if (pci_io) { 234 /* Round I/O allocator to 4KB boundary */ 235 pciauto_region_align(pci_io, 0x1000); 236 237 dm_pci_write_config8(dev, PCI_IO_BASE, 238 (pci_io->bus_lower & 0x0000f000) >> 8); 239 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 240 (pci_io->bus_lower & 0xffff0000) >> 16); 241 242 cmdstat |= PCI_COMMAND_IO; 243 } 244 245 /* Enable memory and I/O accesses, enable bus master */ 246 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); 247 } 248 249 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) 250 { 251 struct pci_region *pci_mem; 252 struct pci_region *pci_prefetch; 253 struct pci_region *pci_io; 254 struct udevice *ctlr = pci_get_controller(dev); 255 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 256 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 257 258 pci_mem = ctlr_hose->pci_mem; 259 pci_prefetch = ctlr_hose->pci_prefetch; 260 pci_io = ctlr_hose->pci_io; 261 262 /* Configure bus number registers */ 263 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq); 264 265 //ast2600 0x1a03 0x1150 pcie re-train for gen 2 config 266 if((pplat->vendor == 0x1a03) && (pplat->device == 0x1150)) 267 dm_pci_write_config8(dev, 0x90, 0x20); 268 269 if (pci_mem) { 270 /* Round memory allocator to 1MB boundary */ 271 pciauto_region_align(pci_mem, 0x100000); 272 273 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, 274 (pci_mem->bus_lower - 1) >> 16); 275 } 276 277 if (pci_prefetch) { 278 u16 prefechable_64; 279 280 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT, 281 &prefechable_64); 282 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 283 284 /* Round memory allocator to 1MB boundary */ 285 pciauto_region_align(pci_prefetch, 0x100000); 286 287 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 288 (pci_prefetch->bus_lower - 1) >> 16); 289 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 290 #ifdef CONFIG_SYS_PCI_64BIT 291 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 292 (pci_prefetch->bus_lower - 1) >> 32); 293 #else 294 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0); 295 #endif 296 } 297 298 if (pci_io) { 299 /* Round I/O allocator to 4KB boundary */ 300 pciauto_region_align(pci_io, 0x1000); 301 302 dm_pci_write_config8(dev, PCI_IO_LIMIT, 303 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); 304 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 305 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); 306 } 307 } 308 309 /* 310 * HJF: Changed this to return int. I think this is required 311 * to get the correct result when scanning bridges 312 */ 313 int dm_pciauto_config_device(struct udevice *dev) 314 { 315 struct pci_region *pci_mem; 316 struct pci_region *pci_prefetch; 317 struct pci_region *pci_io; 318 unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev)); 319 unsigned short class; 320 bool enum_only = false; 321 struct udevice *ctlr = pci_get_controller(dev); 322 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 323 int n; 324 325 #ifdef CONFIG_PCI_ENUM_ONLY 326 enum_only = true; 327 #endif 328 329 pci_mem = ctlr_hose->pci_mem; 330 pci_prefetch = ctlr_hose->pci_prefetch; 331 pci_io = ctlr_hose->pci_io; 332 333 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); 334 335 switch (class) { 336 case PCI_CLASS_BRIDGE_PCI: 337 debug("PCI Autoconfig: Found P2P bridge, device %d\n", 338 PCI_DEV(dm_pci_get_bdf(dev))); 339 340 dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io, 341 enum_only); 342 343 n = dm_pci_hose_probe_bus(dev); 344 if (n < 0) 345 return n; 346 sub_bus = (unsigned int)n; 347 break; 348 349 case PCI_CLASS_BRIDGE_CARDBUS: 350 /* 351 * just do a minimal setup of the bridge, 352 * let the OS take care of the rest 353 */ 354 dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io, 355 enum_only); 356 357 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", 358 PCI_DEV(dm_pci_get_bdf(dev))); 359 360 break; 361 362 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) 363 case PCI_CLASS_BRIDGE_OTHER: 364 debug("PCI Autoconfig: Skipping bridge device %d\n", 365 PCI_DEV(dm_pci_get_bdf(dev))); 366 break; 367 #endif 368 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) 369 case PCI_CLASS_BRIDGE_OTHER: 370 /* 371 * The host/PCI bridge 1 seems broken in 8349 - it presents 372 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 373 * device claiming resources io/mem/irq.. we only allow for 374 * the PIMMR window to be allocated (BAR0 - 1MB size) 375 */ 376 debug("PCI Autoconfig: Broken bridge found, only minimal config\n"); 377 dm_pciauto_setup_device(dev, 0, hose->pci_mem, 378 hose->pci_prefetch, hose->pci_io, 379 enum_only); 380 break; 381 #endif 382 383 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 384 debug("PCI AutoConfig: Found PowerPC device\n"); 385 /* fall through */ 386 387 default: 388 dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io, 389 enum_only); 390 break; 391 } 392 393 return sub_bus; 394 } 395