1 /* 2 * arch/ppc/kernel/pci_auto.c 3 * 4 * PCI autoconfiguration library 5 * 6 * Author: Matt Porter <mporter@mvista.com> 7 * 8 * Copyright 2000 MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #include <common.h> 17 18 #ifdef CONFIG_PCI 19 20 #include <pci.h> 21 22 #undef DEBUG 23 #ifdef DEBUG 24 #define DEBUGF(x...) printf(x) 25 #else 26 #define DEBUGF(x...) 27 #endif /* DEBUG */ 28 29 #define PCIAUTO_IDE_MODE_MASK 0x05 30 31 /* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */ 32 #ifndef CFG_PCI_CACHE_LINE_SIZE 33 #define CFG_PCI_CACHE_LINE_SIZE 8 34 #endif 35 36 /* 37 * 38 */ 39 40 void pciauto_region_init(struct pci_region* res) 41 { 42 /* 43 * Avoid allocating PCI resources from address 0 -- this is illegal 44 * according to PCI 2.1 and moreover, this is known to cause Linux IDE 45 * drivers to fail. Use a reasonable starting value of 0x1000 instead. 46 */ 47 res->bus_lower = res->bus_start ? res->bus_start : 0x1000; 48 } 49 50 void pciauto_region_align(struct pci_region *res, unsigned long size) 51 { 52 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; 53 } 54 55 int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar) 56 { 57 unsigned long addr; 58 59 if (!res) { 60 DEBUGF("No resource"); 61 goto error; 62 } 63 64 addr = ((res->bus_lower - 1) | (size - 1)) + 1; 65 66 if (addr - res->bus_start + size > res->size) { 67 DEBUGF("No room in resource"); 68 goto error; 69 } 70 71 res->bus_lower = addr + size; 72 73 DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower); 74 75 *bar = addr; 76 return 0; 77 78 error: 79 *bar = 0xffffffff; 80 return -1; 81 } 82 83 /* 84 * 85 */ 86 87 void pciauto_setup_device(struct pci_controller *hose, 88 pci_dev_t dev, int bars_num, 89 struct pci_region *mem, 90 struct pci_region *prefetch, 91 struct pci_region *io) 92 { 93 unsigned int bar_value, bar_response, bar_size; 94 unsigned int cmdstat = 0; 95 struct pci_region *bar_res; 96 int bar, bar_nr = 0; 97 int found_mem64 = 0; 98 99 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); 100 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; 101 102 for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) { 103 /* Tickle the BAR and get the response */ 104 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 105 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 106 107 /* If BAR is not implemented go to the next BAR */ 108 if (!bar_response) 109 continue; 110 111 found_mem64 = 0; 112 113 /* Check the BAR type and set our address mask */ 114 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 115 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 116 & 0xffff) + 1; 117 bar_res = io; 118 119 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size); 120 } else { 121 if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 122 PCI_BASE_ADDRESS_MEM_TYPE_64) 123 found_mem64 = 1; 124 125 bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1; 126 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) 127 bar_res = prefetch; 128 else 129 bar_res = mem; 130 131 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size); 132 } 133 134 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) { 135 /* Write it out and update our limit */ 136 pci_hose_write_config_dword(hose, dev, bar, bar_value); 137 138 /* 139 * If we are a 64-bit decoder then increment to the 140 * upper 32 bits of the bar and force it to locate 141 * in the lower 4GB of memory. 142 */ 143 if (found_mem64) { 144 bar += 4; 145 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 146 } 147 148 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 149 PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 150 } 151 152 DEBUGF("\n"); 153 154 bar_nr++; 155 } 156 157 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); 158 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 159 CFG_PCI_CACHE_LINE_SIZE); 160 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 161 } 162 163 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 164 pci_dev_t dev, int sub_bus) 165 { 166 struct pci_region *pci_mem = hose->pci_mem; 167 struct pci_region *pci_prefetch = hose->pci_prefetch; 168 struct pci_region *pci_io = hose->pci_io; 169 unsigned int cmdstat; 170 171 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); 172 173 /* Configure bus number registers */ 174 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, 175 PCI_BUS(dev) - hose->first_busno); 176 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, 177 sub_bus - hose->first_busno); 178 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); 179 180 if (pci_mem) { 181 /* Round memory allocator to 1MB boundary */ 182 pciauto_region_align(pci_mem, 0x100000); 183 184 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 185 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, 186 (pci_mem->bus_lower & 0xfff00000) >> 16); 187 188 cmdstat |= PCI_COMMAND_MEMORY; 189 } 190 191 if (pci_prefetch) { 192 /* Round memory allocator to 1MB boundary */ 193 pciauto_region_align(pci_prefetch, 0x100000); 194 195 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 196 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 197 (pci_prefetch->bus_lower & 0xfff00000) >> 16); 198 199 cmdstat |= PCI_COMMAND_MEMORY; 200 } else { 201 /* We don't support prefetchable memory for now, so disable */ 202 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); 203 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); 204 } 205 206 if (pci_io) { 207 /* Round I/O allocator to 4KB boundary */ 208 pciauto_region_align(pci_io, 0x1000); 209 210 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, 211 (pci_io->bus_lower & 0x0000f000) >> 8); 212 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, 213 (pci_io->bus_lower & 0xffff0000) >> 16); 214 215 cmdstat |= PCI_COMMAND_IO; 216 } 217 218 /* Enable memory and I/O accesses, enable bus master */ 219 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); 220 } 221 222 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 223 pci_dev_t dev, int sub_bus) 224 { 225 struct pci_region *pci_mem = hose->pci_mem; 226 struct pci_region *pci_prefetch = hose->pci_prefetch; 227 struct pci_region *pci_io = hose->pci_io; 228 229 /* Configure bus number registers */ 230 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 231 sub_bus - hose->first_busno); 232 233 if (pci_mem) { 234 /* Round memory allocator to 1MB boundary */ 235 pciauto_region_align(pci_mem, 0x100000); 236 237 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, 238 (pci_mem->bus_lower-1) >> 16); 239 } 240 241 if (pci_prefetch) { 242 /* Round memory allocator to 1MB boundary */ 243 pciauto_region_align(pci_prefetch, 0x100000); 244 245 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 246 (pci_prefetch->bus_lower-1) >> 16); 247 } 248 249 if (pci_io) { 250 /* Round I/O allocator to 4KB boundary */ 251 pciauto_region_align(pci_io, 0x1000); 252 253 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, 254 ((pci_io->bus_lower-1) & 0x0000f000) >> 8); 255 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, 256 ((pci_io->bus_lower-1) & 0xffff0000) >> 16); 257 } 258 } 259 260 /* 261 * 262 */ 263 264 void pciauto_config_init(struct pci_controller *hose) 265 { 266 int i; 267 268 hose->pci_io = hose->pci_mem = NULL; 269 270 for (i=0; i<hose->region_count; i++) { 271 switch(hose->regions[i].flags) { 272 case PCI_REGION_IO: 273 if (!hose->pci_io || 274 hose->pci_io->size < hose->regions[i].size) 275 hose->pci_io = hose->regions + i; 276 break; 277 case PCI_REGION_MEM: 278 if (!hose->pci_mem || 279 hose->pci_mem->size < hose->regions[i].size) 280 hose->pci_mem = hose->regions + i; 281 break; 282 case (PCI_REGION_MEM | PCI_REGION_PREFETCH): 283 if (!hose->pci_prefetch || 284 hose->pci_prefetch->size < hose->regions[i].size) 285 hose->pci_prefetch = hose->regions + i; 286 break; 287 } 288 } 289 290 291 if (hose->pci_mem) { 292 pciauto_region_init(hose->pci_mem); 293 294 DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n" 295 "\t\tPhysical Memory [%x-%x]\n", 296 hose->pci_mem->bus_start, 297 hose->pci_mem->bus_start + hose->pci_mem->size - 1, 298 hose->pci_mem->phys_start, 299 hose->pci_mem->phys_start + hose->pci_mem->size - 1); 300 } 301 302 if (hose->pci_prefetch) { 303 pciauto_region_init(hose->pci_prefetch); 304 305 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n" 306 "\t\tPhysical Memory [%x-%x]\n", 307 hose->pci_prefetch->bus_start, 308 hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1, 309 hose->pci_prefetch->phys_start, 310 hose->pci_prefetch->phys_start + 311 hose->pci_prefetch->size - 1); 312 } 313 314 if (hose->pci_io) { 315 pciauto_region_init(hose->pci_io); 316 317 DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n" 318 "\t\tPhysical Memory: [%x-%x]\n", 319 hose->pci_io->bus_start, 320 hose->pci_io->bus_start + hose->pci_io->size - 1, 321 hose->pci_io->phys_start, 322 hose->pci_io->phys_start + hose->pci_io->size - 1); 323 324 } 325 } 326 327 /* HJF: Changed this to return int. I think this is required 328 * to get the correct result when scanning bridges 329 */ 330 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) 331 { 332 unsigned int sub_bus = PCI_BUS(dev); 333 unsigned short class; 334 unsigned char prg_iface; 335 int n; 336 337 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 338 339 switch(class) { 340 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 341 DEBUGF("PCI AutoConfig: Found PowerPC device\n"); 342 pciauto_setup_device(hose, dev, 6, hose->pci_mem, 343 hose->pci_prefetch, hose->pci_io); 344 break; 345 346 case PCI_CLASS_BRIDGE_PCI: 347 hose->current_busno++; 348 pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io); 349 350 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); 351 352 /* Passing in current_busno allows for sibling P2P bridges */ 353 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 354 /* 355 * need to figure out if this is a subordinate bridge on the bus 356 * to be able to properly set the pri/sec/sub bridge registers. 357 */ 358 n = pci_hose_scan_bus(hose, hose->current_busno); 359 360 /* figure out the deepest we've gone for this leg */ 361 sub_bus = max(n, sub_bus); 362 pciauto_postscan_setup_bridge(hose, dev, sub_bus); 363 364 sub_bus = hose->current_busno; 365 break; 366 367 case PCI_CLASS_STORAGE_IDE: 368 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); 369 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { 370 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n"); 371 return sub_bus; 372 } 373 374 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); 375 break; 376 377 case PCI_CLASS_BRIDGE_CARDBUS: 378 /* just do a minimal setup of the bridge, let the OS take care of the rest */ 379 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); 380 381 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev)); 382 383 hose->current_busno++; 384 break; 385 386 #ifdef CONFIG_MPC5200 387 case PCI_CLASS_BRIDGE_OTHER: 388 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n", 389 PCI_DEV(dev)); 390 break; 391 #endif 392 #ifdef CONFIG_MPC834X 393 case PCI_CLASS_BRIDGE_OTHER: 394 /* 395 * The host/PCI bridge 1 seems broken in 8349 - it presents 396 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 397 * device claiming resources io/mem/irq.. we only allow for 398 * the PIMMR window to be allocated (BAR0 - 1MB size) 399 */ 400 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n"); 401 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); 402 break; 403 #endif 404 default: 405 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); 406 break; 407 } 408 409 return sub_bus; 410 } 411 412 #endif /* CONFIG_PCI */ 413